JPH05183169A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce in size a cell of a nonvolatile memory. CONSTITUTION:An insulating film is laminated on a conductive band film to become a control gate, the insulating film, the conductive band film to become a control gate, a conductive band film to become a floating gate are etched, and a gate electrode is patterned. Thereafter, an insulating film is formed on the sidewall of the gate electrode, and wiring in formed on a source and a drain in a self-alignment manner. In a selection view, numerals 3, 5, 6, 9, 10, 11 are the floating gate, the control gate, the insulating film, the source and the drain, the sidewall insulating film and the wiring, respectively. Thus, since the source and the drain are brought into contact with the wiring in a self- alignment manner, it is not necessary to consider a distance between the gate electrode and a contact hole, and a size of a nonvolatile memory is very reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a non-volatile memory.

[0002]

2. Description of the Related Art In FIG. 12, 21 is a silicon substrate,
Reference numeral 22 is a gate insulating film, 23 is a conductive band layer serving as a floating gate electrode, 24 is a thin insulating film, and 25 is a conductive band layer serving as a control gate electrode.
Next, as shown in FIG. 13, using the photoresist film 26 as a mask, the conductive band layer 25, the thin insulating film 24, and the conductive band layer 23 are sequentially patterned. Next, as shown in FIG. 14, after removing the photoresist film 26, the sidewalls of the control gate electrode 25 and the floating gate electrode 23 are oxidized to form an oxide film 27. Next, after forming the source / drain 28 as shown in FIG.
9 are stacked and a contact hole 30 is further formed. Next, as shown in FIG. 16, the wiring 31 is formed.

[0003]

Problems to be Solved by the Invention As shown in FIG.
When the length of the gate electrode is 1, the distance between the gate electrode and the contact hole is m, and the size of the contact hole is n, the size p of the nonvolatile memory is expressed by the following formula. p = 1 + m + n These 1, m and n must be larger than the minimum size of the technology for manufacturing a semiconductor device. For example, in the 0.8 micron rule technology, the minimum dimensions of m and n are 0.8 and 0.8 (respectively micron), so p = 1 +
It becomes 1.6 (micron), which is a considerably large memory. That is, a certain size other than the gate of the non-volatile memory is required.

[0004]

In order to solve the above problems, according to the present invention, an insulating film is laminated on a conductive band film to be a control gate, and then a gate electrode is patterned. After that, an insulating film is formed on the side wall of the gate electrode, and wiring is formed on the source / drain in a self-aligned manner.

[0005]

Since the source / drain contacts the wiring in a self-aligned manner, it is not necessary to consider the distance between the gate electrode and the contact hole. That is, since m = 0, the size of the nonvolatile memory becomes very small.

[0006]

Embodiments of the present invention will be described with reference to FIGS. As shown in FIG. 1, a gate insulating film 2 is formed on a semiconductor substrate 1, a film 3 to be a floating gate electrode film is stacked on the gate insulating film 2, and a floating gate electrode film 3 is formed. Then, a thin interlayer insulating film 4 is formed, a film 5 serving as a control gate electrode film is laminated on the thin interlayer insulating film 4, and an insulating film 6 is formed on the thin interlayer insulating film 4. The semiconductor substrate 1 is a semiconductor such as silicon (Si). The gate insulating film 2 is also called a tunnel insulating film. The floating gate electrode film 3 is generally formed of a polycrystalline silicon (PolySilicon) film, but other conductors can also be used. As the control gate electrode film 5, a polycrystalline silicon film, a silicide film, a polycide film, a metal film, or the like can be used. The insulating film 6 is a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like.

Next, as shown in FIG. 2, the photoresist film 7 is patterned to form a pattern to be a gate electrode. Next, as shown in FIG. 3, the insulating film 6, the film 5 serving as the control gate electrode film, the thin interlayer insulating film 4 and the film 3 serving as the floating gate electrode film are sequentially etched using the photoresist film 7 as a mask. These etchings may be performed by one etching device or different devices. After the etching, the gate insulating film 2 is also partially or wholly removed.

After removing the photoresist film 7, the semiconductor substrate 1 is oxidized to form an oxide film 8 as shown in FIG. Further, the impurity diffusion layer 9 is formed by using the gate electrodes 3, 4, 5 and 6 as a mask. The impurity diffusion layer 9 is, of course, a conductor opposite to the semiconductor substrate 1. Generally, the semiconductor substrate 1 is P
And the impurity diffusion layer 9 is N-type. Since the impurity diffusion layer 9 serves as a source / drain, its impurity concentration is high. The purpose of oxidizing the semiconductor substrate 1 to form the oxide film 8 is to damage the electrode film during etching (damage).
And the like, or to remove or recover damages and the like that have entered the base substrate 1. Therefore, the oxide film 8 may be formed after the impurity diffusion layer 9 is formed. When the impurity diffusion layer 9 is formed by ion implantation, the oxidation of the semiconductor substrate 1 also removes or recovers damaging of ion implantation. However, if the damage or the like caused by etching or ion implantation is small, or if it is removed or recovered in a later step, this oxidation step can be omitted.

Next, as shown in FIG. 5, an insulating film 10 serving as a sidewall insulating film is laminated. The insulating film 10 is an insulating film such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or alumina. The insulating film 10 is laminated by a chemical vapor deposition (CVD) method or a physical vapor deposition (PVD) method. Subsequently, as shown in FIG. 6, the insulating film 10 serving as the sidewall insulating film is etched to form the sidewall insulating film 10 on the sidewall of the electrode. Since the etched surface of the electrode is vertical and the thickness of the insulating film on the side wall of the electrode is considerably thicker than that on the flat portion, anisotropic etching is performed to remove the insulating film on the flat portion. The insulating film on the side wall of can be left. Of course, if the etching is performed too much, the side wall insulating film is also lost. Therefore, it is necessary to finish the etching after the insulating film 10 on the flat surface is etched. As shown in FIG. 6, the sidewall insulating film 10 must necessarily cover the sidewalls of the floating gate electrode 3 and the control gate electrode 5. In order to remove damaging or the like generated during this etching, heat treatment may be performed after the etching.

Then, after removing the thin insulating film (residual after etching of the gate insulating film 2) 2 on the impurity diffused layer 9 to expose the impurity diffused layer 9, as shown in FIG. The wiring layer 11 is laminated. The first wiring layer 11 is a conductor film, such as a polycrystalline silicon film doped with an impurity element, a silicide film, a metal film, or a composite film thereof. Since the first wiring layer 11 is in contact with the exposed impurity diffusion layer 9, it is electrically connected. The first wiring layer 11 is laminated by the CVD method or the PVD method.

Next, as shown in FIG. 8, the photoresist film 1
2 is used as a mask to pattern the first wiring layer 11 into a desired shape. In FIG. 1, since the impurity diffusion layers 9 alternately serve as the source and the drain with respect to the gate electrode, the adjacent wiring layers 11 are generally not connected. Next in FIG.
As shown in, the interlayer insulating film 13 is laminated. Since the electrodes and the wiring have irregularities, the interlayer insulating film 13 is generally flattened. A PSG film (Phosphoru) is used as the interlayer insulating film 13.
s Silicate Glass) and BPSG film (Boron Phosphorus Si)
licate glass) and ASG film (Arsenic Silicate Glass) are used.

Next, as shown in FIG. 10, the interlayer insulating film 13 is formed.
A contact hole 14 is formed in the. The contact hole 14 may be formed anywhere on the first wiring layer 11, and need not be directly above the impurity diffusion layer 9. The width of the first wiring layer 11 can be generally larger than the distance between the electrodes. For these reasons, it is not necessary to provide a margin for alignment other than the contact holes in the distance between the electrodes. Therefore,
The distance between the electrodes can be greatly reduced.

Next, as shown in FIG. 11, the second wiring layer 1
5 is formed. The second wiring layer 15 is in contact with the first wiring layer 11 in the contact hole 14. The second wiring layer 15 is a conductor film, such as a polycrystalline silicon film doped with an impurity element, a silicide film, a metal film, or a composite film of these. As described above, the nonvolatile memory including the gate insulating film 2, the floating gate electrode 3, the thin interlayer insulating film 4, the control gate electrode 5, and the source / drain 9 is prepared.

[0014]

As described with reference to FIGS. 1 to 11, according to the present invention, the contact holes can be formed in a self-aligned manner, so that the element size of the nonvolatile memory can be remarkably reduced. That is, in the conventional manufacturing method, there was a relation of p = 1 + m + n as shown in FIGS. 12 to 16, but as shown in FIG. 11, in the present invention, it is not necessary to consider the distance between the gate electrode and the contact hole. , You don't have to think about alignment. Therefore, the size p of the nonvolatile memory is given by the following equation.

P = 1 + n For example, in the 0.8 micron rule, 1 = 0.8 micron and n = 0.8 micron, p = 1.6 micron. (Conventionally 2.4 micron) Further, in the 0.6 micron rule, 1 = 0.6 micron and n = 0.6 micron, p = 1.2 micron. (Conventional 1.8 micron)
Furthermore, in the 0.4 micron rule, 1 = 0.4 micron,
When n = 0.4 μm, p = 0.8 μm.
(Conventionally, 1.2 μm) Further, in the 0.2 μm rule, p = 0.4 μm with 1 = 0.2 μm and n = 0.2 μm. (Conventional 0.6 micron) As can be seen from the above, the size of the nonvolatile memory according to the present invention is reduced to about 65% in size and about 40% in area as compared with the conventional method.

Furthermore, since the formation of the contact hole 14 with the impurity diffusion layer 9 does not require a mask process, the number of processes is greatly reduced. This has a great advantage that the manufacturing cost of the nonvolatile memory is reduced.

[Brief description of drawings]

FIG. 1 is a first process sectional view showing a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a second process sectional view showing the method for manufacturing the semiconductor device of the present invention.

FIG. 3 is a third process sectional view showing the method for manufacturing the semiconductor device of the present invention.

FIG. 4 is a fourth process sectional view showing the method of manufacturing the semiconductor device of the invention.

FIG. 5 is a fifth step cross-sectional view showing the method of manufacturing a semiconductor device of the present invention.

FIG. 6 is a sixth process sectional view showing the method for manufacturing the semiconductor device of the present invention.

FIG. 7 is a sectional view of a seventh step showing the method for manufacturing the semiconductor device of the present invention.

FIG. 8 is an eighth process sectional view showing the method for manufacturing the semiconductor device of the present invention.

FIG. 9 is a cross sectional view of a ninth step showing the method for manufacturing the semiconductor device of the present invention.

FIG. 10 shows a tenth method of manufacturing a semiconductor device according to the present invention.
FIG.

FIG. 11 is an eleventh method of manufacturing a semiconductor device according to the present invention.
FIG.

FIG. 12 is a twelfth process sectional view showing the method of manufacturing the conventional semiconductor device.

FIG. 13 is a thirteenth step sectional view showing the method of manufacturing the conventional semiconductor device.

FIG. 14 is a cross-sectional view of a fourteenth step showing the conventional method of manufacturing a semiconductor device.

FIG. 15 is a fifteenth step sectional view showing the method of manufacturing the conventional semiconductor device.

FIG. 16 is a sixteenth step sectional view showing the method of manufacturing the conventional semiconductor device.

[Explanation of Codes] 1, 21 Semiconductor (silicon) substrate 2, 22 Gate insulating film 3, 23 Floating gate electrode film 4, 24 Thin interlayer insulating film 5, 25 Control gate electrode film 6 Insulating film 7 , 26 photoresist film 8, 27 oxide film 9, 28 source / drain (impurity diffusion layer) 10 sidewall insulating film 11 first wiring layer 12 photoresist layer 13, 29 interlayer insulating film 14, 30 contact hole 15 second Wiring layer 31 Wiring layer l Length of gate electrode m Distance between gate electrode and contact hole m n Size of contact hole

Claims (1)

[Claims] 1. In a nonvolatile memory having a floating gate electrode film and a control gate electrode film, a step of forming an insulating film on a conductor film which will be a control gate electrode film in the future, and a shape of a gate electrode of the nonvolatile memory. A step of etching the insulating film, a step of etching the conductor film to be the control gate electrode film using the patterned insulating film as a mask, and a step of etching the conductor film to be the floating gate electrode film, A step of forming an insulating film to be a sidewall insulating film on the gate electrode of the nonvolatile memory; a step of etching the insulating film to be a sidewall insulating film to form a sidewall insulating film on the sidewall of the gate electrode; Exposing the surface of the source or drain, stacking a conductor film and contacting the exposed surface of the source or drain of the nonvolatile memory, A step of patterning a conductor film to form a wiring layer, and a method for manufacturing a semiconductor device.