JPH05182906A - Hetero epitaxially growing method - Google Patents

Hetero epitaxially growing method

Info

Publication number
JPH05182906A
JPH05182906A JP34664691A JP34664691A JPH05182906A JP H05182906 A JPH05182906 A JP H05182906A JP 34664691 A JP34664691 A JP 34664691A JP 34664691 A JP34664691 A JP 34664691A JP H05182906 A JPH05182906 A JP H05182906A
Authority
JP
Japan
Prior art keywords
layer
gaas
growing
substrate
growth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP34664691A
Other languages
Japanese (ja)
Inventor
Hisao Nakajima
尚男 中島
Shigehiko Hasegawa
繁彦 長谷川
Kenzo Maehashi
兼三 前橋
Kouichi Koukado
浩一 香門
Hiroya Kimura
浩也 木村
Mitsuru Shimazu
充 嶋津
Futatsu Shirakawa
二 白川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP34664691A priority Critical patent/JPH05182906A/en
Publication of JPH05182906A publication Critical patent/JPH05182906A/en
Pending legal-status Critical Current

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  • Crystals, And After-Treatments Of Crystals (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To obtain a GaAs epitaxial layer having a low dislocation and high quality by growing a group II element single atomic layer on an As single atomic layer, growing a low temperature GaAs buffer layer thereon and epitaxially growing a GaAs layer on the buffer layer. CONSTITUTION:An Si (100) board 1 is heated to 250 deg.C, and an As single atomic layer 2 is formed thereon. Then, a single atomic layer 3 of group II element such as Zn, Be, Mg, etc., is formed thereon. Thereafter, while a growing temperature remains at 250 deg.C, a low temperature GaAs buffer layer 4 is grown on the layer 3. Then, the growing temperature is raised to 550 deg.C, and a GaAs epitaxial layer 5 is grown. Thus, a two-dimensional grown can be controlled in an initial step of the GaAs epitaxial growth on the board.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、Si基板上に良質のG
aAs層をエピタキシャル成長させるヘテロエピタキシ
ャル成長法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention
The present invention relates to a heteroepitaxial growth method for epitaxially growing an aAs layer.

【0002】[0002]

【従来の技術】GaAs等の化合物半導体は、Siに比
べて電子移動度が高く、直接遷移型のバンド構造を持つ
ため、高速電子デバイスや発光、受光デバイス等に広く
利用されている。電子デバイスの分野では、高電子移動
度トランジスター(HEMT)を利用した集積回路の開
発、試作等がなされている。このような複数の素子を集
積化するGaAsデバイスを実現するためには、GaA
s等の化合物半導体の薄膜結晶を大面積に、かつ均一に
制御しながら成長する必要がある。大面積基板上に化合
物半導体の薄膜結晶を成長させる場合、同一材料種であ
るGaAs基板が用られるが、GaAs結晶は比重が大
きく、また脆いという物性上の弱点が、基板の大口径化
にともなってデバイスプロセスを制約するという問題が
新たに生ずる。そこで、大口径基板の入手が容易で、比
重が小さく、機械的強度の強いSi基板を用いて、化合
物半導体の薄膜結晶を成長させるヘテロエピタキシャル
成長技術が注目されるようになった。
2. Description of the Related Art A compound semiconductor such as GaAs has a higher electron mobility than Si and has a direct transition type band structure, and is therefore widely used for high speed electronic devices, light emitting devices, light receiving devices and the like. In the field of electronic devices, development and trial production of integrated circuits using high electron mobility transistors (HEMTs) are being carried out. In order to realize a GaAs device that integrates a plurality of such elements, GaA
It is necessary to grow a thin film crystal of a compound semiconductor such as s in a large area while controlling it uniformly. When growing a thin film crystal of a compound semiconductor on a large-area substrate, a GaAs substrate of the same material type is used, but GaAs crystals have a large specific gravity and are fragile. A new problem arises that the device process is restricted. Therefore, a hetero-epitaxial growth technique for growing a thin film crystal of a compound semiconductor using an Si substrate having a large diameter substrate which is easily available, has a low specific gravity and a high mechanical strength has been attracting attention.

【0003】しかし、GaAsは、Siより格子定数が
約4%大きく、熱膨張率が約3倍と大きいために、Ga
As基板を用いるときに比べて、Si基板上に良質なG
aAs結晶をエピタキシャル成長させることは不可能で
あった。例えば、格子定数の差が大きいために格子不整
合によるミスフィット転位が発生したり、また、熱膨張
率の違いによ理成長後の冷却工程でウエハに反りが発生
し、平坦なウエハを得ることができなかった。
However, since GaAs has a lattice constant larger than Si by about 4% and a thermal expansion coefficient about three times larger than that of Si, Ga is
Good quality G on Si substrate compared to when using As substrate
It was impossible to epitaxially grow an aAs crystal. For example, a large difference in lattice constant causes misfit dislocations due to lattice mismatch, and a difference in thermal expansion coefficient causes warp in the wafer in the cooling step after physical growth, so that a flat wafer is obtained. I couldn't.

【0004】これらの問題を解決するために、Si基板
の上にアモルファス状の低温GaAsバッファ層を介し
てGaAsエピタキシャル層を成長させる2段階法と呼
ばれる成長法が提案されている。(M.Akiyama 等"Jpn.A
ppl.Phsys.,23,(1984)L843参照) また、低温バッファ層の代わりに中間層として超格子を
用いた成長法も提案されている。(特開昭62─58616 号
公報) これらの方法により、現在までにミスフィト転位は10
6 cm-2程度まで低減されたが、通常のGaAs系化合
物半導体デバイスにおいて許容される転位密度104
-2、レーザーダイオードで許容される転位密度103
cm-2と比較して2〜3桁以上多く、なお改善する必要
があった。
In order to solve these problems, a growth method called a two-step method has been proposed in which a GaAs epitaxial layer is grown on a Si substrate via an amorphous low-temperature GaAs buffer layer. (M.Akiyama et al. "Jpn.A
ppl.Phsys., 23, (1984) L843) Also, a growth method using a superlattice as an intermediate layer instead of the low temperature buffer layer has been proposed. (Unexamined-Japanese-Patent No. 62-58616) By these methods, the misphyto rearrangement is 10 by now.
Although reduced to about 6 cm -2, the dislocation density is 10 4 c, which is allowable in a normal GaAs compound semiconductor device.
m -2 , dislocation density allowed by laser diode 10 3
Compared with cm -2 , there are more than two or three digits, and it was necessary to improve.

【0005】[0005]

【発明が解決しようとする課題】そこで、本発明は、上
記の問題点を解消し、Si基板上に低転位で良質のGa
Asエピタキシャル層が得られるヘテロエピタキシャル
成長方法を提供しようとするものである。
SUMMARY OF THE INVENTION Therefore, the present invention solves the above-mentioned problems, and has a low dislocation and good quality Ga on a Si substrate.
It is intended to provide a heteroepitaxial growth method capable of obtaining an As epitaxial layer.

【0006】[0006]

【課題を解決するためき手段】本発明は、Si基板上に
GaAs層をエピタキシャル成長させる方法において、
Si基板表面にAs単原子層を成長する第1工程と、A
s単原子層の上にZn、Be、Mg等のII族元素の単原
子層を成長する第2工程と、その上に低温GaAsバッ
ファ層を成長する第3工程と、該バッファ層の上にGa
As層をエピタキシャル成長する第4工程とを有するこ
とを特徴とするヘテロエピタキシャル成長法である。
The present invention provides a method for epitaxially growing a GaAs layer on a Si substrate, comprising:
A first step of growing an As monoatomic layer on the surface of the Si substrate,
s a second step of growing a monoatomic layer of a Group II element such as Zn, Be, Mg, etc. on the monoatomic layer, a third step of growing a low temperature GaAs buffer layer thereon, and a third step of Ga
And a fourth step of epitaxially growing the As layer, which is a heteroepitaxial growth method.

【0007】[0007]

【作用】本発明者等は、上記の格子不整合や熱膨張率の
差異による技術的課題の他に、Si基板上のGaAs成
長における初期段階の成長形式に着目した。Si基板上
にGaAsを成長させると、GaAsは島状に成長し、
次いで島同士が合体するときにミツフィット転位等の欠
陥が入ることが分かっていた。この3次元島状成長の起
こる原因がSi基板とGaAs層との界面に発生する電
荷の不整合にあると考えられる。即ち、非極性半導体で
あるSi表面にIII 族ないしV族原子が結合して結晶格
子が形成される過程で、結合手であるダングリングボン
ドが生ずることになるが、このダングリングボンド一つ
には電荷が一つ伴うため、Si基板との界面に極めて大
きな電荷不整合が発生することになり、この電荷不整合
をエネルギー的に安定させるためには、界面付近におけ
るGaAs成長は3次元島状成長が起こると考えられ
る。そこで、Si基板上とGaAs層との界面の電荷中
性化を行うことにより、GaAs成長初期の時点から2
次元層状成長を促進させることができ、良質なGaAs
薄膜を得ることに成功し、本発明を完成するに至った。
The present inventors have paid attention to the growth mode at the initial stage of GaAs growth on the Si substrate, in addition to the above technical problems due to the lattice mismatch and the difference in the coefficient of thermal expansion. When GaAs is grown on a Si substrate, GaAs grows like islands,
It was then known that defects such as Mitsufit dislocations would be introduced when the islands coalesce. It is considered that the cause of this three-dimensional island-like growth is the mismatch of charges generated at the interface between the Si substrate and the GaAs layer. That is, a dangling bond, which is a bond, is generated in the process in which a group III or V atom is bonded to the surface of Si, which is a nonpolar semiconductor, to form a crystal lattice. Causes an extremely large charge mismatch at the interface with the Si substrate, and in order to stabilize this charge mismatch in terms of energy, GaAs growth near the interface is a three-dimensional island shape. Growth is believed to occur. Therefore, by neutralizing the charge on the interface between the Si substrate and the GaAs layer, it is possible to reduce the charge from the initial stage of GaAs growth to 2
High-quality GaAs that can promote three-dimensional layered growth
We succeeded in obtaining a thin film and completed the present invention.

【0008】本発明では、Si基板とGaAs層の界面
にII族原子を単原子層で挿入することにより、SiとII
I 族あるいはV族原子との間で発生する電荷不整合を解
消することができ、低転位で良質のGaAsエピタキシ
ャル層を得ることができるのである。図1は、本発明の
1具体例である、Si基板上のAs単原子層、Zn単原
子層、及び低温GaAsバッファ層の上にGaAsエピ
タキシャル層を形成した積層の断面構造を示したもので
あり、図2は、Si基板界面付近における原子の結合状
態を示したものである。
In the present invention, Si and II are formed by inserting a group II atom as a monoatomic layer at the interface between the Si substrate and the GaAs layer.
It is possible to eliminate the charge mismatch generated between the group I atom and the group V atom, and obtain a high-quality GaAs epitaxial layer with low dislocation. FIG. 1 shows a sectional structure of an As monoatomic layer, a Zn monoatomic layer on a Si substrate, and a laminated structure in which a GaAs epitaxial layer is formed on a low-temperature GaAs buffer layer, which is one embodiment of the present invention. FIG. 2 shows the bonding state of atoms in the vicinity of the Si substrate interface.

【0009】[0009]

【実施例】分子線エピタキシャル法(MBE法)を用
い、図1の積層構造でSi基板上にGaAs層をエピタ
キシャル成長させた。第1工程として、MBE装置にセ
ットしたSi(100)基板1を250℃に加熱した
後、As分子線のみを基板に照射し、Si基板上にAs
単原子層2を形成した。次いで、第2工程として、II族
原子源のZn分子線を同じ温度で照射してAs単原子層
2の上にZn単原子層3を形成した。第3工程では、成
長温度を250℃に保持したままAs分子線とGa分子
線を同時に照射し、Zn単原子層3の上に低温GaAs
バッファ層4を200Å成長させた。この時のAsとG
aの分子線強度比(フラックス比)は10であり、成長
時間は5分であった。その後、成長温度を550℃まで
昇温させ、GaAsエピタキシャル層5を約3μm成長
させた。この時のAs/Gaフラックス比は10であ
り、成長速度は1μm/hであった。(得られたGaA
sエピタキシャル層の転位密度、2次元成長の確認など
の実験結果を記載することができませんか。)
EXAMPLE A GaAs layer was epitaxially grown on a Si substrate in the laminated structure shown in FIG. 1 by using the molecular beam epitaxial method (MBE method). As the first step, after heating the Si (100) substrate 1 set in the MBE apparatus to 250 ° C., the substrate is irradiated with only As molecular beams, and the As substrate is irradiated with As.
The monoatomic layer 2 was formed. Then, as a second step, a Zn monoatomic layer 3 was formed on the As monoatomic layer 2 by irradiating a Zn molecular beam of a group II atom source at the same temperature. In the third step, the As molecular beam and the Ga molecular beam are simultaneously irradiated while keeping the growth temperature at 250 ° C., and low temperature GaAs is formed on the Zn monoatomic layer 3.
The buffer layer 4 was grown to 200Å. As and G at this time
The molecular beam intensity ratio (flux ratio) of a was 10, and the growth time was 5 minutes. After that, the growth temperature was raised to 550 ° C. and the GaAs epitaxial layer 5 was grown to about 3 μm. At this time, the As / Ga flux ratio was 10, and the growth rate was 1 μm / h. (Obtained GaA
Could you describe the experimental results such as dislocation density of s epitaxial layer and confirmation of two-dimensional growth? )

【0010】[0010]

【発明の効果】本発明は、上記の構成を採用することに
より、Si基板とGaAsエピタキシャル層との界面で
発生する電荷不整合を解消することができ、Si基板上
へのGaAsエピタキシャル成長の初期過程において3
次元島状成長を抑制し、2次元成長を支配的にすること
ができるために、低転位で良質のGaAsエピタキシャ
ル層を得ることができるようになった。
According to the present invention, by adopting the above structure, the charge mismatch generated at the interface between the Si substrate and the GaAs epitaxial layer can be eliminated, and the initial process of GaAs epitaxial growth on the Si substrate can be eliminated. At 3
Since the two-dimensional growth can be controlled by suppressing the three-dimensional island growth, it has become possible to obtain a high-quality GaAs epitaxial layer with low dislocation.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明のヘテロエピタキシャル成長法で得た、
Si基板上にGaAsエピタキシャル層を形成した積層
構造の1例を示した断面図である。
FIG. 1 was obtained by the heteroepitaxial growth method of the present invention,
FIG. 3 is a cross-sectional view showing an example of a laminated structure in which a GaAs epitaxial layer is formed on a Si substrate.

【図2】図1のSi基板界面付近の原子の結合状態を示
した説明図である。
FIG. 2 is an explanatory diagram showing a bonded state of atoms in the vicinity of the interface of the Si substrate of FIG.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 木村 浩也 兵庫県伊丹市昆陽北一丁目1番1号 住友 電気工業株式会社伊丹製作所内 (72)発明者 嶋津 充 兵庫県伊丹市昆陽北一丁目1番1号 住友 電気工業株式会社伊丹製作所内 (72)発明者 白川 二 兵庫県伊丹市昆陽北一丁目1番1号 住友 電気工業株式会社伊丹製作所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroya Kimura 1-1-1 Kunyo Kita, Itami City, Hyogo Prefecture Sumitomo Electric Industries, Ltd. Itami Works (72) Inventor Mitsuru Shimazu 1-1 Kunyo Kita, Itami City, Hyogo Prefecture No. 1 Sumitomo Electric Industries, Ltd. Itami Works (72) Inventor Two Shirakawa 1-1, Kunyo Kita, Itami City, Hyogo Prefecture Sumitomo Electric Industries Itami Works

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 Si基板上にGaAs層をエピタキシャ
ル成長させる方法において、Si基板表面にAs単原子
層を成長する第1工程と、As単原子層の上にZn、B
e、Mg等のII族元素の単原子層を成長する第2工程
と、その上に低温GaAsバッファ層を成長する第3工
程と、該バッファ層の上にGaAs層をエピタキシャル
成長する第4工程とを有することを特徴とするヘテロエ
ピタキシャル成長法。
1. A method of epitaxially growing a GaAs layer on a Si substrate, comprising: a first step of growing an As monoatomic layer on a Si substrate surface; and Zn, B on the As monoatomic layer.
e, a second step of growing a group II element monoatomic layer such as Mg, a third step of growing a low-temperature GaAs buffer layer thereon, and a fourth step of epitaxially growing a GaAs layer on the buffer layer. A heteroepitaxial growth method comprising:
JP34664691A 1991-12-27 1991-12-27 Hetero epitaxially growing method Pending JPH05182906A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP34664691A JPH05182906A (en) 1991-12-27 1991-12-27 Hetero epitaxially growing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP34664691A JPH05182906A (en) 1991-12-27 1991-12-27 Hetero epitaxially growing method

Publications (1)

Publication Number Publication Date
JPH05182906A true JPH05182906A (en) 1993-07-23

Family

ID=18384857

Family Applications (1)

Application Number Title Priority Date Filing Date
JP34664691A Pending JPH05182906A (en) 1991-12-27 1991-12-27 Hetero epitaxially growing method

Country Status (1)

Country Link
JP (1) JPH05182906A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7732325B2 (en) 2002-01-26 2010-06-08 Applied Materials, Inc. Plasma-enhanced cyclic layer deposition process for barrier layers
US7781326B2 (en) 2001-02-02 2010-08-24 Applied Materials, Inc. Formation of a tantalum-nitride layer
US10280509B2 (en) 2001-07-16 2019-05-07 Applied Materials, Inc. Lid assembly for a processing system to facilitate sequential deposition techniques

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7781326B2 (en) 2001-02-02 2010-08-24 Applied Materials, Inc. Formation of a tantalum-nitride layer
US10280509B2 (en) 2001-07-16 2019-05-07 Applied Materials, Inc. Lid assembly for a processing system to facilitate sequential deposition techniques
US7732325B2 (en) 2002-01-26 2010-06-08 Applied Materials, Inc. Plasma-enhanced cyclic layer deposition process for barrier layers

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