JPH05181938A - Peeling rewiring processor - Google Patents

Abstract

PURPOSE:To obtain a peeling rewiring processor which minimizes the number of electric conductors to be peeled and effectively suppresses a delay violation. CONSTITUTION:This processor is equipped with a violation network input means 2 which inputs information on a violation network requiring a rewiring process by a delay analysis, etc., in the rewiring process of a network making a delay violation on an LSI, a printed board, etc., after an arrangement wiring process, a wiring path setting means 3 which sets a rewiring path by mutually relating and specifying wiring paths having the same virtual wiring length as the inputted network, a delay value calculating means 4 which calculates a delay value as to an electric conductor present in the area wherein, and a peeled electric conductor extraction means 5 which extracts the electric conductor having the largest margin extents of the calculated delay value and a limited delay value as an object of peeling.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a peeling rewiring processing device for an LSI, a printed circuit board or the like, and more particularly to a peeling rewiring processing device in consideration of a peeling wiring selection method.

[0002]

2. Description of the Related Art When performing rewiring processing for a given net, some wirings may be peeled off. In the conventional peeling and rewiring processing method, a certain amount of wire is placed around the terminals of the net. A region having a size is provided, and all the wirings in the region are to be peeled off. After peeling, a given net is wired, and then the peeled wiring is re-wired.

FIG. 8 and FIG. 9 show an example of peeling wiring according to the conventional method. Areas 601 and 602 having a certain width are generated around the terminals 301 and 302 of the violation net.
All the wirings included in these regions 601 and 602 are the targets of the wirings to be stripped. FIG. 9 shows a state in which all of this wiring is deleted. Since most of the wiring is stripped off, there is no obstacle and the violation net 201 can be re-wired with a wiring length equal to the virtual wiring length.

[0004]

In the conventional peeling rewiring processing method, when the given net is wired, all the wirings existing in the set area are peeled off. A lot of T
There was a drawback that it cost AT. Further, when there is a critical net in the stripped wiring, rewiring causes the wiring length to change from the previous wiring pattern, resulting in a delay violation.

[0005]

SUMMARY OF THE INVENTION An object of the present invention is to provide a peeling rewiring processing apparatus which can improve the disadvantages of the conventional example, and particularly can set the number of wirings to be peeled to a minimum and effectively suppress the occurrence of delay violation. That is the purpose.

[0006]

According to the present invention, a violation net input means for inputting violation net information that needs rewiring processing by delay analysis or the like and a virtual wiring length of the input net are made equal in length. Route setting means for designating a re-routing route by designating various wiring routes in association with each other, and delay value calculation for calculating a delay value for a wiring existing in the area with a certain width in the set route The present invention employs a configuration in which a means and a peeling wiring extracting means for extracting a wiring having the largest margin between the calculated delay value and the limited delay value to be peeled are provided. This aims to achieve the above-mentioned object.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of a peeling rewiring processing system according to an embodiment of the present invention. This processing is composed of several processing procedures, which are controlled by the control means 1. As a premise, here, the background, the delay of the block, and the physical information 10 have already been input, and the placement of the block on the LSI and the printed circuit board based on the logical connection information 11 and the wiring process of the inter-block net have been completed. It is assumed that the information 12 has been generated. In order to perform a delay analysis based on the placement / routing information 12 and, as a result, to perform a rerouting process for a net that has a delay violation,
The violation net is input by the violation net input means 2 and the wiring pattern of this violation net is deleted.

Next, the wiring route is set by interactively designating the wiring route having the same length as the virtual wiring length of the violation net input by the wiring route setting means 3. The wiring path set by the means 3 has a certain width, and the delay value calculating means 4 calculates the delay value for all the wirings existing in the area. From the result,
In the peeling wiring extracting means 5, the wiring having the largest margin between the calculated actual delay value and the limited delay value is extracted and used as a peeling target. Then, the wiring peeling means 6 peels off the wiring extracted by the means 5, and the violation net input by the violation net rewiring processing means 7 is wired in the area of the designated route.

As a result, the violation net becomes a wire whose length is substantially equal to the virtual wire length. Here, the violating net rewiring control means 8 judges whether or not the wiring of the violating net is completed, and if the wiring of the violating net is not completed due to being disturbed by other existing wiring, the wiring is re-established. Returning to the route setting means 3, the violation net rewiring processing means 7 are sequentially repeated. When the wiring of the violating net is completed, the peeling / rewiring processing means 9 rewires the wiring peeled by the wiring peeling means 6.

FIG. 2 shows the layout of blocks on the LSI and the printed circuit board, and the wiring state of a part at the time when the wiring process of the inter-block net is completed. 101 in the figure
Indicates a wiring prohibited area. First, delay analysis is performed from these pieces of wiring information, and as a result, a net that has a delay violation is input by the violation net input means 2.
In the figure, 201 is a wire for violating nets 301 and 302 are terminals of this wire. Therefore, the wiring 201 of the violation net is deleted. Next, as shown in FIG. 3, the wiring route setting means 33 interactively designates a wiring route having the same length as the virtual wiring length of the violation net 201, and sets the wiring route 401. Wiring route 4 set here
In 01, a wiring path area 501 having a certain width is generated, and the delay value calculation means 4 calculates delay values for all the wirings existing in the area.

As a result, the peeling-wiring extracting means 5 extracts the wiring having the largest margin between the calculated actual delay value and the limited delay value and sets it as a peeling target. In FIG. 4, 202 is the wiring having the largest margin in the wiring route area 501. Then, the wiring peeling means 6 peels off the wiring 202 extracted by the means 5. FIG. 5 shows a state in which the wiring 202 is peeled off. Next, the result of wiring the violating net 201 in the wiring route area 501 by the violating net rewiring processing means 7 is Wiring 2 in FIG.
Eleven. The wiring 211 has a designated wiring pattern and is substantially equal to the virtual latitude line length. Here, since the wiring 211 of this violating net is already completed, the repeating processing in the violating net rewiring control means 8 is not performed. Finally, the peeling rewiring processing means 9 re-wires the wiring 202 peeled by the wiring peeling means 6. This result is shown by the wiring 212 in FIG. 7.

[0012]

As described above, according to the present invention, in order to peel off the existing wiring and re-route the wiring which has become the delay violation, first, the path of the violating net is given and the path is given a width. Generate a region, calculate the delay time for the wiring in that region, compare it with the limited delay value, extract the wiring with the largest margin, peel off that wiring, and reroute the violating net. Since the last peeled wire is re-wired, the number of wires to be peeled off is minimized, the TAT in the peel-off and re-wiring is reduced, and the net that is a delay violation satisfies the limit delay time. Further, since the critical wiring is excluded from the target of the peeling wiring, it is possible to provide an excellent peeling and rewiring processing device which does not have a delay time and is kept.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an initial wiring state in FIG.

FIG. 3 is an explanatory diagram showing wiring route setting of a violation net in FIG.

4A and 4B are explanatory diagrams showing generation of a wiring route area and extraction of a peeled wiring in FIG.

FIG. 5 is an explanatory diagram showing a result of stripping the wiring 202 in FIG.

6 is an explanatory diagram showing a violating net rewiring processing result of the wiring 201 in FIG. 1;

7 is an explanatory diagram showing a result of peeling and rewiring processing of the wiring 202 in FIG.

FIG. 8 is an explanatory diagram showing setting of peeling wiring by a conventional method.

FIG. 9 is an explanatory diagram showing stripping of wiring by a conventional method.

[Explanation of symbols]

1 Control Means 2 Violation Net Input Means 3 Wiring Route Setting Means 4 Delay Value Calculation Means 5 Peeling Wiring Extracting Means 6 Wiring Peeling Means 7 Violation Net Rewiring Processing Means 8 Violation Net Rewiring Control Means 9 Peeling Rewiring Means 101 Wiring prohibited area 201 Wiring of delay violation net 202 Wiring having the largest margin between the limit delay value and the current delay value 211 Rewiring result of delay violation net 212 Rewiring result of peeled wire 202 301, 302 Delay violation net terminal 401 Specified wiring route 501 Routing route area 601, 602 Area around terminals

Claims (3)

[Claims] 1. A violating net input means for inputting violating net information which requires re-wiring processing by delay analysis or the like in re-wiring processing of a net which is a delay violation in an LSI, a printed circuit board or the like after placement and routing processing. , A wiring route setting means for setting a rerouting route by associating and designing a wiring route that is equal in length to the virtual wiring length of the input net, and an area having a certain width in the set route Delay value calculating means for calculating a delay value for the wiring existing therein, and peeling wiring extracting means for extracting the wiring having the largest margin between the calculated delay value and the limiting delay value for peeling. A peeling and rewiring processing device comprising: 2. Violation net input means for inputting violating net information that requires rewiring processing by delay analysis or the like in rewiring processing of a net that has a delay violation in an LSI, a printed circuit board or the like after placement and routing processing. , A wiring route setting means for setting a rerouting route by associating and designing a wiring route that is equal in length to the virtual wiring length of the input net, and an area having a certain width in the set route Delay value calculating means for calculating a delay value for the wiring existing therein, and peeling wiring extracting means for extracting the wiring having the largest margin between the calculated delay value and the limiting delay value for peeling. And stripping the wiring extracted by the stripping wiring extracting means, and a stripping means for stripping off the wiring, and a resolving violation net for routing the input violation net within the area of the designated route. A stripping and rewiring processing device comprising wiring processing means. 3. Violation net input means for inputting violating net information that requires rewiring processing by delay analysis or the like in rewiring processing of a net that has a delay violation in an LSI, a printed circuit board or the like after placement and routing processing. , A wiring route setting means for setting a rerouting route by associating and designing a wiring route that is equal in length to the virtual wiring length of the input net, and an area having a certain width in the set route Delay value calculating means for calculating a delay value for the wiring existing therein, and peeling wiring extracting means for extracting the wiring having the largest margin between the calculated delay value and the limiting delay value for peeling. And stripping the wiring extracted by the stripping wiring extracting means, and a stripping means for stripping off the wiring, and a resolving violation net for routing the input violation net within the area of the designated route. Equipped with a wiring processing means, the violating net rewiring control means for repeatedly controlling the rewiring path setting means to the violating net rewiring processing means until the wiring of the violating net is completed, and the peeling wiring extracting means, A peeling rewiring processing device comprising: peeling rewiring processing means for rewiring the peeled wiring.