JPH05181778A - Input/output processor - Google Patents

Abstract

PURPOSE:To provide an I/O processor reduced at its overrun by the addition of the small number of hardwares. CONSTITUTION:An address buffer 122a stores addresses. A count buffer 123 stores a count value. An address buffer 121a stores a prefetched address. A count buffer 121b stores a prefetched count value. A part 151 stores a prefetched flag. A valid flag 160 indicates the validity of each prefetched information. At the time of outputting a data transfer request from a channel part, a count value read out from the buffer 123a is subtracted, and if all the values of the flag 160 are '1' when the subtracted result becomes zero, the data of the buffer 121a are written in the buffer 122a, the data of the buffer 121b are written in the buffer 123a and the data of the 1st flag 151 are written in the 2nd flag 152, so that data transfer is continued.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input / output processing device, and more particularly to an input / output processing device capable of realizing a prefetching method in data transfer with a small amount of hardware without overrun.

[0002]

2. Description of the Related Art Conventionally, this type of input / output processing device is connected between a main storage device and a plurality of input / output control devices, and transfers data between the main storage device and the plurality of input / output control devices. Is controlling. In such an input / output processing device, a preemptive method is used for data transfer. As a prefetching method in this data transfer, there are roughly two methods adopted.

As a first prefetching method, a channel program word is prefetched by a microprogram without storing any special hardware for prefetching, and this is stored in a work memory or the like inside the processor. When a break in a data chain occurs, the microprogram is interrupted, the stored prefetch information (data address and data count) is set in a predetermined buffer or the like, and data transfer is restarted.

The second pre-fetching method is to have dedicated hardware for pre-fetching, and set the data transfer control information (address and count) required next one after another by a microprogram.

[0005]

However, the first pre-emption method adopted in the above-mentioned conventional input / output processing device must suspend the data transfer and process the microprogram during that time. In order to control without data overrun, there is a drawback that the data buffer size is made very large or a high performance microprogram controller is required.

Further, although the second prefetching method adopted in the above-mentioned conventional input / output processing device is very advantageous in terms of performance, it has a drawback that the amount of hardware becomes large.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above-mentioned drawbacks and to provide an input / output processing device capable of executing data transfer without overrun with a small amount of hardware.

[0008]

In order to achieve the above object, the input / output processing device of the present invention is connected between a main storage device which is an upper device and a plurality of input / output control devices which are lower devices. And a common section including a plurality of channel sections that connect a plurality of input / output control apparatuses, a microprogram control section that is controlled by a microprogram, and a data transfer control section that controls data transfer between the channel section and the main storage device. In the input / output processing device including the above, the data transfer control unit stores prefetch information storage means for storing prefetch address information and prefetch data length, and address information and data length of the transfer data in the main storage device. The storage means, the updating means for updating the address information and the data length of the storage means each time the main storage device for data transfer is accessed, and the data chain are instructed. The prefetch first flag that stores whether or not the data is stored, the address information of the next transfer data and the data length when the data chain is instructed, and the information that stores whether or not the data chain is continued. A flag and a prefetch valid flag indicating that each content of the flag is valid, and when the value of the data length of the storage means is subtracted by the updating means to become zero, the prefetch is performed if all the valid flags are set. It is characterized in that the data in the information storage means is written in the storage means so that the data transfer is continued.

The prefetch storage means may be composed of a prefetch address buffer for storing the prefetched address and a prefetch count buffer for storing the prefetch data length. Further, the storage means may be composed of a count buffer for storing the number of remaining bytes of the data currently being transferred and an address buffer for storing the address currently being transferred.

In the present invention, when the count value read from the storage means is updated by the updating means in response to a data transfer request from the channel section and the update result becomes zero, the value of the effective flag is When all are "1", the prefetch address data and the prefetch count value (data length) from the prefetch information storage means are written in the storage means, and the data from the first flag is written in the second flag, thereby transferring the data. Will continue.

On the other hand, according to the present invention, if any of the valid flags is "0", the data transfer is interrupted, and then the micro program control unit is interrupted to set the prefetch data in the prefetch information storage means. After that, the data transfer is restarted and activated.

[0012]

EXAMPLES The present invention will be described in detail below with reference to examples.

FIG. 1 is a block diagram showing a data transfer system including an embodiment of an input / output processing device of the present invention.

In the data transfer system shown in FIG. 1, the input / output processing device 10 is connected via a memory bus 32 to a central processing device 30 and a main storage device 31, which are upper devices of the input / output processing device 10. Further, the input / output processing device 10 includes a plurality of input / output control devices 50 _A , 50 _B , which are subordinate devices thereof.
..., 50 _H is connected. The input / output control device 50 _A is a magnetic disk control device, and the magnetic disk drive device 5
I / O of 1 is controlled. The input / output control device 50 _B is a unit record control device and controls the input / output of the man-machine interface device 52, the printer device 53, and the floppy disk device 54. I / O controller 5
0 _H is a magnetic tape controller, and the magnetic tape device 55
I / O is controlled.

The input / output processing device 10 includes a common section 11 for performing various processes related to data transfer, and a plurality of input / output control devices 30 _A , 30 _B , ..., 30 _H for input / output control of data. Channel parts 12 _A , 12 _B , ..., 12 _H. The common unit 11 includes a micro program control unit 110 controlled by a micro program, and a data transfer control unit 111 that transfers data asynchronously with the micro program.

FIG. 2 is a block diagram showing a detailed structure of a common part of the input / output processing device.

In FIG. 2, the micro program control unit 11
0 and the detailed configuration of the data transfer control unit 111 are shown. Therefore, first, the configuration of the data transfer control unit 111 will be described.

The data transfer control section 111 controls the transfer data.
Stores address information and data length on the main memory 31
Prefetch information storage means (prefetch address buffer 12
1_a, Pre-emption buffer 121_b) And the transfer date
Stores address information and data length on the main memory of the computer
Storage means (address buffer 113_a, Count buff
A 113_a) And a main storage device 31 for data transfer.
Updates address information and data length each time it is accessed
Updating means (address updating means [address register 1
22_b, Subtractor 122_c], Data length updating means [count
Register 132_b, Subtractor 132_c]) And the data
The first in a data chain that stores whether or not the chain is indicated
A flag (first flag 151) and a data chain are instructed.
Address information and data of the next transfer data
Stores the data length and whether or not the data chain continues
The second flag (second flag 152)
Preemption valid flag (valid)
Flag 160) and pre-emption enabled flag (pre-emption enabled)
Preemption when each information of flag 160) is written
Means for setting a valid first flag corresponding to the information,
Channel part 12_A, 12 _B, ..., 12_HData transfer from
Main memory device based on the address information described above in response to a transmission request
31 to access the channel section 12_A, 12_B, ..., 1
Two_HWrite data to main memory 31 or
Ia means for reading data and sending it to the channel section
(Data transfer control circuit 180, data transfer priority determination circuit
190) and the update result of the data length from the updating means is zero.
Zero detection means (count zero detection
Output circuit 131) and zero detection means (count zero detection times).
Channel 131) output and the value of the data chain flag
Means to notify the department (flag 141_a~ 141_c, 14
Two_a~ 142c), the output of the zero detection means is activated.
If the first flag is "1" and all preemption
The valid flag (valid flag 160) is set
If the address of the pre-fetching flag is
Information and data chain flag
One of the means to reset the lag and the valid flag
If none is set, the data transfer will be interrupted.
Instructing means for instructing the channel section (preemption effectiveness detection circuit 1
33) and. In addition, the data transfer control unit 111
Is an interrupt priority determination circuit 1100, registers 1110, 1
120, 171_a~ 171_d, Decoders 172,173
And so on.

The main structure will be described in detail. Prefetch address buffer 121 _a stores the prefetched data address. Prefetch cans out buffer 121 _b stores the data length of prefetch. Address buffer 122 _a
Is a count buffer that stores the number of remaining bytes of data currently being transferred. Address register 122 _b updates the address for storing the data currently transferred.
The above four types exist for each channel. Second flag 15
2 consists of a data chain flag of the channel command word currently being processed and a page mode flag for storing whether or not the data transfer is in page mode. First flag 151
Stores the data chain flag of the prefetched channel command word. These also store information for each channel.

The zero detection circuit 131 detects that the remaining count of transfer data has reached 0. The page boundary detection circuit 132 detects whether or not the memory address has reached a page boundary (which is previously determined to be 4 kbytes) during data transfer. The valid flag 160 is a valid flag indicating whether or not the prefetched data address, data length, and data chain flag are valid. V _{0 corresponds} to the data address, V _{1 corresponds} to the data length, and V ₂ corresponds to the data chain flag. To do. The data transfer control circuit 180 controls the entire data transfer operation, and also controls the interface with the main storage device 31. Data transfer priority determination circuit 1
Reference numeral 90 determines the priority of data transfer, and when data transfer requests are simultaneously received from a plurality of channels, one of them is selected based on a predetermined priority order. The interrupt priority determination circuit 1100 determines the priority of an interrupt request to the microprogram coming from the channel unit 12 and transmits an interrupt signal to the microprogram control unit 110. The buffer register 1110 temporarily holds write data when writing the data from the channel unit 12 to the main storage device 31. The output data buffer register 1120 holds temporary data when writing the data read from the main storage device 31 into the data buffer 200 of the channel unit 12.

[0021] In this embodiment, the prefetch address buffer 121 _a as described above, prefetch cans out buffer 121
_The feature is that _b , the first flag 151, the effective flag 160 and the like are newly added.

Further, the micro program control unit 110
Is composed of a micro program controller 110 _A for executing a micro program and a control memory device 110 _B for storing a micro program. Then, the micro program controller 110 _A includes the channel units 12 _A , 1
In response to the interrupt signal from 2 _B , ..., 12 _H , the prefetch information storage means (prefetch address buffer 121 _a , prefetch count buffer 121 _b ) stores the address information, the data length, and the value of the data chain flag regarding the next transfer data. After writing, after writing, the channel sections 12 _A , 12 _B ,
The contents of the storage means _12H described later are reset.

FIG. 3 is a block diagram showing the configuration of one of the plurality of channel units of the input / output processing device.

The channel unit 12 is a data transfer control unit 1.
11, the output of the zero detection means 131 notified from 11, and the value of the data chain flag from the page boundary detection circuit 132,
Storage means (flags 261-263, 27) for storing a data transfer interruption instruction from the prefetch validity detection circuit 133.
1-273), and means for generating an interrupt request signal and interrupting the microprogram controller when the data chain flag of the storage means is "1" and the output from the zero detection means 131 is activated. Interrupt request generation circuit 201) and means for suppressing a data transfer request from the channel data transfer control circuit 202 of the channel section (flags 263, 273, AND circuit 233, NAND circuit 232, AND Circuit 231). The channel unit 12 also includes a data buffer 200, a data buffer control unit 203, a decoding circuit 204, a register 208, a register 209, and an I / O.
It has an O interface control unit 210 and the like.

Next, the structure of the main part will be described. The data buffer 200 temporarily buffers data sent or received via the 1/0 interface, and has a capacity of 64 bytes. In the case of output data transfer, this data buffer 200 is read byte by byte from the main storage device 31 via the register 1120 and then read out byte by byte on the data path L11. Sent out.
Further, in the case of input data transfer, data of each byte received via the data path L11 is written to the data buffer 200, and when data of 4 bytes or more remains in the buffer, 4 bytes are written to the main storage device 31. Write in units. The data buffer control unit 203 performs busy management and the like of the data buffer 200.

The command register 208 temporarily stores the instruction contents (such as flag reset) from the microprogram control unit 110. The channel number register 209 is
It indicates to which channel section 12 the command stored in the command register 208 is instructed. The channel unit 12 compares its own channel number information with the contents of this register 208, and if they match, recognizes that it is an instruction to itself and decodes the command by the decoding circuit 204 and executes it. In addition, 251-253, 261-263, 271-
A flag group 273 stores information instructed in synchronization with the data transfer operation from the data transfer control unit 111. Next, the operation of the above-described embodiment will be described below.

First, the data transfer operation will be described.

The input / output processing unit 10 is a central processing unit 30.
The channel program created in the main storage device 31 is retrieved from the main storage device 31. The channel program is composed of a header part including a channel number and a device number, and a channel command word that defines an input / output operation. The channel command word consists of 8 bytes, and consists of a channel command, a data transfer address, and a data length. The data transfer address is given as a physical address of the central processing unit 30 in the non-page mode, but is given as a logical address which is a virtual address on a virtual memory in the page mode, so that it is an input / output processing unit. The conversion from the logical address to the physical address of the main storage device 31 must be performed inside 10. Whether the page mode or not is determined by an instruction issued by the central processing unit 30 to issue the channel program. An example of the format of the channel command word is shown in FIG.

In the format of the channel command word 600 shown in FIG. 6, 0 to 7 bits are commands, and 8 to 15 bits are DC.
Is a data chain (DATA CHAINING), or CC is a command chain (COMMAND CHAINNING).
ING) is shown in 16 to 31 bits and the data address is shown in 0 to 31 bits.

From the central processing unit 30, the physical address, the channel number and the device number on the main storage device 31 in which the channel program is stored are transferred to the input / output processing device 10 through the communication area (fixed address) of the main storage device 31. Given.

The input / output processing unit 10 is a central processing unit 30.
When the I / O operation is started by the device, the request is once placed in the queue. The queue exists for each channel and links device numbers (details of which are not shown in this embodiment).
Thereafter, the corresponding specific signal line on the channel output interface of it to "1", a predetermined input-output control unit 50 _A which is connected under, 50 _B, ..., 50 _H
Informs that there is an I / O request.

When the input / output processing device 10 detects that the signal line has become "1", it informs that the input / output operation is ready to start via the input / output interface, so that 1 byte of information is transmitted. (Service code) is transmitted. Predetermined channel part 12 _A , 1 of the input / output processing device 10
2 _B , ..., 12 _H are input / output control devices 30 _A , 30 _B ,
.., 30 _H , the I / O interface controller 210 requests the interrupt controller 201 to generate an interrupt. Micro program control unit 1
10 indicates the service code when it is interrupted
_{2 A, 12 B, ...,} 12 and analyzed removed from the _H, the first word of that value, if the channel program that instructs the start of the output is taken out from the main memory 31, the command word of 8 bytes with the device number Input / output control device 50 _A , 50
_B , ..., 50 _H.

Input / output control devices 30 _A , 30 _B , ..., 30
_{If H} decodes the command word sent from the input / output processing device 10 and instructs the data transfer, again,
The service code is sent to the input / output processing device 10.

The service code of this time is an instruction to start the data transfer. Input / output control device 50 _A , 50
At the same time, _B , ..., 50 _H also activate their own devices to prepare for data transfer.

In the input / output processing device 10, an interrupt is issued to the micro program control unit 110 as described above. This time, the micro program control unit 110
The channel command is analyzed, and if it does not indicate data transfer, the error signal on the I / O interface control unit 210 is set to "1" to notify that it is abnormal. Further, if the analysis result of the channel command indicates data transfer, the input / output processing device 10 causes the microprogram control unit 110 to perform the following to the data transfer control unit 111.

[0036] (1) writing to the address Baa file 121 _a the address contained in the channel command word. If the address at this time is a logical address, the microprogram controller 110, set in the address buffer 122 _a on which is translated to a physical address of the main storage device on 31 using a conversion table that exists in the main storage device 31 To do.

[0037] (2) channel command word written to the count value contained in the count buffer 123 _a (see FIG. 5).

(3) Next, if the result of checking the data chain flag is "1", the DC bit of the second flag 152 is set to "1", and if the check result is "0", the second flag 1 is set.
The DC bit of 52 is set to "0". Also, it is checked whether or not the data transfer is in the page mode. If the page mode, the PGMD bit of the second flag 152 is set to "1", and if it is not the page mode, the PGMD bit of the second flag 152 is set to "0". ..

(4) In the input / output processing device 10, the microprogram control unit 110 causes the P of the second flag 152 to be changed.
If the GMD bit is "1", calculation is performed to add the count value to the address, and it is checked whether the result exceeds the page boundary, for example, 4 [K bytes]. If, if exceeding a page boundary, determine the starting address of the next page (logical address), converts it to a physical address, and writes the prefetch address buffer 121 _a. At this time, “1” is set to the valid bit V ₀ bit of the valid flag 160.

(5) If the PGMD bit of the second flag 152 is "0" or does not cross the page boundary during data transfer, the I / O processor 10 checks the data chain bit. If the data chain bit is "1", the second channel command word is extracted.

[0041] (6) the address of the second channel command word (converted to naturally physical address if the logical address), is set to prefetch address buffer 121 _a. Similarly, the count value and the data chaining flag is set to the count buffer 123 _a and the first flag 151. At this time, the valid bits from the valid bit V ₀ to V ₂ of the valid flag 160 are set.

(7) The input / output processing device 10 is further
In the I / O interface control unit 210 of the channel unit 12,
To a count register (not shown)
23 _aSet the same value as the
The buffer 200 is set to an empty state.

(8) All the control flag groups 251-253, 261-263, 271-273 in the channel section 12 are reset.

When the above steps (1) to (8) have been set, the phase shifts from service code processing to data transfer by setting a predetermined signal line on the I / O interface to "0". To do.

When the channel command word indicates the output data transfer, the data buffer 20 of the channel unit 12
The data buffer control unit 203 detects that 0 is empty, and the channel data transfer control circuit 202 causes the signal line 9
To "1" to 1 _a to request data transfer to the data transfer control unit 111 of the input-output processor 10 (FIGS. 4 (a) timing T _1).

The request is the data transfer priority determination circuit 19
When it is 0, the competition with the request from another channel is judged. The priority here is uniquely determined by the channel number. When the request is selected by the data transfer priority determination circuit 190, the request and the selected channel number are assigned to the signal line 92.
Channel number is transmitted to the data transfer control circuit 180 by entering the reception channel register 171 _a (FIG. 4 (c)
Timing T ₂ ). Accepts channel register 171 _a is either one of an accept signal 172 _a ~172n the channel portion 12 which has received the decoded request is returned (see FIG. 4 (b) timing T _2).

When receiving the accept signal, the channel section 12 drops the request signal 91a to "0". Channel number entered the reception channel register 171 _a is transferred to the register 171 _b at the next timing (FIG. 4 (d) timing T _3).

[0048] Simultaneously, the register 171 the value of the address buffer 122 _a count buffer 123 _a at the output of _a is read out, is set in the address register 122 _b and the count register 123 _b (FIG. 4 (g) (h) timing T _3), the channel number of register 171 _b is transferred to the register 171 _c (FIG. 4 (e) timing T _4).
At this time, the data transfer control circuit 180
Data is requested using the request signal line 81 and the command line 82 (FIG. 4 (i) (j) timing T ₃ ). At this time, the address of the main memory 31, sent contents of the address register 122 _b is the main storage device 31, the contents of the command line 82 the contents for instructing the data reading is generated by the data transfer control circuit 180.

The contents of the address buffer 122 _a are summed by the number of bytes transferred by the computing unit 122 _c,
Written back to the address buffer 122 _a. The contents of the count register 123 _b is the number of bytes transferred is subtracted by the calculator 123 _c count buffer 123
written back to _a. Address buffer 122 at this time
The contents of the register 171 _c are used as the write addresses of _a and the count buffer 123 _a .

The data read from the main memory 31 is temporarily stored in the register 1120, and the data line L22
Will be sent to the data buffer 200 of the channel section 12 (timing T _{5 in} FIG. 4 (l)).

The channel number is further sent from the register 171 _c to the register 171 _d (timing T _{5 in} FIG. 4 (f)), the contents of the register 171 _d are decoded and signaled to the channel section 12 to indicate the completion of a series of operations. Line 73 _a ~
Only one of 73 _n is set to "1".

[0052] channel section 12, the signal line 73 _a is "1"
Therefore, the data of the data line L22 is written to the data buffer 200, the first byte of the data buffer 200 is read, and the data is sent to the data path L11 on the I / O interface. The tag) line is activated to start a data transfer sequence with the input / output control device 12.

If the channel command word indicates input data transfer, 1 [byte] is sent through the data path L11.
When the data buffer control unit 203 detects that the data received in units remains in the data buffer for 4 [bytes] or more, it issues a data transfer request rq to the channel data transfer control circuit 202.

Main memory 31 to input / output controller 5
Data transfer for 0 _A , 50 _B , ..., 50 _H is performed as described above.

On the other hand, the input / output control devices 50 _A , 50 _B ,
The writing operation from the 50 _H to the main memory device 31 is similar to the output data transfer, except that the contents of the data buffer 200 are read into the register 1110 and sent to the main memory device 31 (see FIG. 4 (k) timing T ₃ ), the memory command generated by the data transfer control circuit 180 only instructs writing.

[0056] The above-mentioned operation is the case also the address not to count 0 by the data transfer does not reach the page boundary, the flag 141 _a ~143 _a, 141 _b ~
To 143 _b, 141 _c ~143 _c are all 0 is set.

<Operation of Count 0>

Next, the operation when the count becomes 0 by data transfer will be described.

(Operation when pre-emption is in time)

[0060] count register 123 _b result of subtracting the contents of the can in checked by counting the zero detection circuit result is 0 and the DC bits of the second flag 152 is "1", set the flag 141 _a 1 is a prefetch address buffer 121 _a, prefetch address buffer 12
1 _a and all valid flags V ₀ of the prefetch flag 151
V ₂ is checked by the prefetch validity judgment circuit 133. Result of the test, when the prefetch all V bits of the flag 151 is "1", the address buffer 122 _a count buffer 123 _a, preemption instead of the output of the output operation unit 123 _c of the arithmetic unit 122 _c the contents of the prefetch count buffer 121 _b and the address buffer 121 _a is written, the flag 143 _a and the flag 142 _a "0"
Is set. In addition, all V bits in valid flag 160 are reset.

[0061] the content of the flag 141 _a ~143 _a is moved to the flag 141 _b ~143 _b at the next timing, is transmitted to the channel unit 12 via the signal line 41 _c ~ 43 _c.
In the channel section 12, the flags 271 to 273 are set through the gates 251 to 253. In this case, only the flag 271 becomes "1".

The interrupt request generation circuit 201 uses the flag 2
When data other than “0” is set in 71 to 273, an interrupt signal is generated, and the signal line L01 _a (this signal line includes information indicating the content of the interrupt in addition to the interrupt request, but (Not shown) is activated to request an interrupt to the input / output processing device 10. In the input / output processing device 10, the interrupt signal L02 is transmitted to the micro program control unit 110 through the interrupt priority determination circuit 1100.

[0063] microprogram control unit 110, when the interrupt occurs, prefetch memory address and data count and data chaining flag for the next data transfer retained therein and prefetch address buffer 112 _a and prefetch count buffer 112 _b Set to the effective flag 160. Regarding the prefetch information set by the microprogram control unit 110, if the next data transfer is a data chain, the above-mentioned three types of prefetch information sets are necessary, but they are related to page breaks. If there is, set only the address. That is, if it is related to page breaks, the effective flag 16
Only the V ₀ bit of ₀ becomes “1”. When the above setting is completed, the microprogram control unit 110 further prepares prefetch information regarding the next data transfer and stores it in the microprogram control unit 110. Next, the micro program control unit 110 gives an instruction to reset the contents of the flags 271 to 273 of the channel unit 12. This instruction is issued from the micro program control unit 110 through the signal line S2 _a.
Indicates the channel designated by S2 _b .

The data on the signal line S2 _a and the signal line S2 _b are
After being stored in the register 208 and the register 209 in the channel 12, it is decoded by the decoding circuit 204 and executed. Upon receiving the reset instruction, the channel 12 transfers the contents of the flags 261 to 263 to the flags 271 to 272.

Data transfer between the channel unit 12 and the main storage device 31 is continued while the above processing is being performed.

(Operation when pre-emption is not in time)

[0067] With reference to FIG. 5, the count register 123 _b of the operation result is 0, and the second flag 15
When the DC bit of 2 is "1", and any one bit of V _{0 to} V ₂ of the prefetch valid flag 160 is "0"
If it is, it is determined that the pre-emption process is not in time for some reason (process conflict, etc.), and the flag 141
_a flag 143 _a is set with a flag 141 at the next timing _b, the flag 143 _b is set.
In this case, the value of the V bit of the prefetch valid flag 160 is retained. As a result, the flag 26 of the channel unit 12
1 and the flag 263 are set, the flag 271 and the flag 273 are set at the next next timing, and an interrupt is generated at the next timing as in the above description. However, since the flag 273 is "1", data transfer between the channel unit 12 and the main storage device 31 during this period is suppressed.

Since the microprogram control unit 110 does not accept the interrupt from the channel 12 until the prefetch processing is completed, all the prefetch valid flags 1 are accepted at the time when the interrupt is accepted.
60 V-bits have been set. In this case, the micro program controller 110 executes a special micro instruction. Its microinstruction execution result, V bit of the effective flag 160 is "1" prefetch buffer prefetch address buffer 121 _a, prefetch cans out buffer 121 _b, the first flag is data chaining flag 151
Is written to the address buffer 122 _a , the count buffer 122 _b, and the DC bit of the second flag 152. When the micro program control unit 110 gives an instruction to reset the flag of the channel unit 12 after finishing the above processing, the flag 273 becomes "0" and the data transfer is restarted.

As a result of data transfer, the count buffer 12
Even if the subtraction result of 3 _a does not become 0, the page boundary detection circuit 132 detects that the addition result of the address register 122 _b has reached the page boundary, and the second flag 1
If the PGMD bit of 52 is "1", the flag 142
_a is set. At the same time, the preemptive effectiveness determination circuit 13
3, it is checked whether the V ₀ bit is “1”, and if the check result is “1”, the flag 143 _{a is set} to “0”.
If V ₀ of the effective flag 160 is “0”, it is set to “1”. V ₀ bit of valid flag 160 is “1”
If it is, the address buffer 122 _a, an adder 12
It is not the addition result of 2 _c , but the prefetch address buffer 12
The content of 1 _a is written, the subtraction result is written in the count buffer 123 _a, and the V ₀ bit of the valid flag 160 is reset to “0”. Otherwise, V ₀ bit of the effective flag 160, the flag 141 _a ~143
The contents of _a is set to the flag 141 _c ~143 _c, will be conveyed to the channel portion 12.

[0070] The following operation is performed as in the aforementioned flag 141 _a is set, ahead of the information required to interrupt occurs next prefetch to the micro program control unit 110 address buffer 121 _a prefetch Kan'uto After writing to the buffer 121 _b and the second flag 152 for prefetching, the flag of the channel unit 12 is reset. Also at this time, if the flag 173 is "1", the data transfer between the channel unit 12 and the main storage device 31 is interrupted, and if the flag 173 is "1", the data transfer is continued.

Next, the operation of the two sets of flags in the channel section will be described.

During data transfer, the data count value becomes 0, and the flag 271 of the channel section 12 is set (see FIG. 5).
(J) Timing T ₆ ), microprogram controller 1
If an interrupt occurs in 10 (timing T _{7 in} FIG. 5 (n)) and the count reaches 0 again before the microprogram controller 110 writes the next prefetch buffer, the flags 141 _a and 143 _a are set ( Figure 5
(G) Timing T ₉ ) and flag 14 at the next timing
1 _c and 143 _c are set (timing T _{10 in} FIG. 5 (i)) and sent to the channel section 12.

The channel section 12 has the first set of flags 271.
～273 because not "0" (FIG. 5 (j) (k) Timing T _15), the contents of this flag second set of flags 26
1 to 262 (FIG. 5 (j) (k) timing T ₁₂ ). At this time, since the flag 263 is "1",
Data transfer is suppressed by the AND gate 231 via the OR gate 233 and the NAND gate 232.

The microprogram control unit 110 uses the prefetch address buffer 121 _a and the prefetch count buffer 1
21 _b , when the writing of the second flag for prefetching is completed (that is, after the corresponding V bit becomes “1”) and the microprogram control unit 110 issues a reset instruction of the channel flag, the channel unit 12 Flags 271-273 under the control of the instruction decoding unit 204 of
The contents of the flags 261 to 263 are transferred to (see FIG. 5).
(J) (k) Timing T ₁₂ ). Since the flag 273 is “1” after the data is transferred, the data transfer inhibition state continues, and the interrupt request generation circuit 201 requests the microprogram control unit 110 again for an interrupt.

The microprogram control unit 110 responds to the interrupt by the prefetch address buffer 1 as described above.
21 _a , the prefetch counter 121 _b and the effective flag 160, after writing necessary information, the channel unit 1
2 instruct the flag to reset. In the second reset instruction, since the flags 261 to 263 are "0", the flag 2
71 to 273 will be "0" in the future, the cause of the interrupt will disappear, the data transfer inhibition state will be released, and the data transfer will resume.

As described above, when the data transfer is performed and all the data transfers are completed, that is, the data count value becomes 0 and the DC bit of the second flag 152 is "0".
Then, the data transfer control unit 111 instructs the channel unit 12 to complete the data transfer by a signal line (this signal line is not shown). Upon receiving the data transfer completion signal, the channel unit 12 stops sending the data transfer request regardless of whether the data buffer 200 is empty or clogged, sets a predetermined signal line on the I / O interface to "1", and sets the predetermined signal line to "1". The end of transfer is notified to the input / output control device 50.

When the CC bit of the channel command word is "1", the input / output control device 50 sends a service code requesting the input / output processing device to send the next channel command word. Further, when the CC bit is "0", the input / output control device 50 sends the service code instructing the end of the I / O operation to the input / output processing device 10 together with 3 bytes of the status byte indicating the end status.

If the service code requesting the next command word, the I / O processor 10 fetches it from the next command word memory and sends it to the I / O controller 50. If the service code is an instruction to terminate, the termination report information is created in the main storage device 31 to report the termination,
Link to the end report queue. (A queue is built on memory and there is only one for all I / O devices. Details are not shown here.)

[0079]

As described above, according to the present invention,
High performance, less data overrun, and less hardware required.

[Brief description of drawings]

FIG. 1 is a block diagram showing a data transfer system including an embodiment of an input / output processing device of the present invention.

FIG. 2 is a block diagram showing a configuration of a data transfer control unit of the input / output processing device according to the embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a channel unit of the input / output processing device according to the embodiment of the present invention.

FIG. 4 is a timing chart for explaining the operation of this embodiment.

FIG. 5 is a timing chart for explaining the operation of this embodiment.

FIG. 6 is an explanatory diagram showing an example of channel commands used in the embodiment of the present invention.

[Explanation of symbols]

10 input / output processing unit 30 central processing unit 31 main storage unit 50 _A input / output control unit 50 _B input / output control unit 50 _H input / output control unit 110 micro program control unit 110 _A micro program control unit 110 _B control storage unit 111 data transfer Control unit 121 _a Prefetch address buffer 121 _b Prefetch counter buffer 122 _a Address buffer 122 _b Address register 122 _c Adder 123 _a Count buffer 123 _b Count register 123 _c Subtractor 131 Count zero detection circuit 132 Page boundary detection circuit 133 Prefetch enabled Property detection circuit 151 First flag 152 Second flag 160 Effective flag 180 Data transfer control circuit 190 Data transfer priority determination circuit

Claims (3)

[Claims] 1. A plurality of channel units, which are connected between a main storage device, which is a higher-level device, and a plurality of input / output control devices, which are lower-level devices, and which connect the plurality of input / output control devices, and a microprogram. In an input / output processing device comprising a controlled microprogram control unit and a common unit including a data transfer control unit that controls data transfer between the channel unit and the main storage device, the data transfer control unit includes a prefetch Preemption information storage means for storing address information and prefetch data length, storage means for storing address information and data length of the transfer data on the main storage device, and each time the main storage device for data transfer is accessed once An updating means for updating the address information and the data length of the storage means, a prefetch first flag for storing whether or not a data chain is instructed, If a data chain is instructed, a second flag that stores the address information and data length of the next transfer data and information whether the data chain continues or not, and that each content of the flag is valid When the value of the data length of the storage means is subtracted by the updating means and becomes zero, the data of the prefetch information storage means is stored in the storage means if all the valid flags are set. The input / output processing device is characterized in that the data transfer is continued by being written in. 2. The input / output processing device according to claim 1, wherein the prefetch storage means comprises a prefetch address buffer for storing a prefetched address and a prefetch count buffer for storing a prefetch data length. 3. The storage means comprises a count buffer for storing the number of remaining bytes of data currently being transferred and an address buffer for storing an address currently being transferred. I / O processor.