JPH05175794A - M series generating circuit - Google Patents

Abstract

PURPOSE:To generate the M series with a small scale circuit configuration at a low speed. CONSTITUTION:Adders 11a-11h of mod.2 are formed to-generate an output of a consecutive timing in the case of shift register configuration. Thus, outputs of the 8 adders 11a-11h are given to flip-flops 12a-12h to obtain a parallel 8-bit M series. The M series is extracted as an output and fed back to the input side of the adders 11a-11h.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an M-sequence generation circuit for generating an M-sequence used for randomizing a transmitted digital video signal.

[0002]

2. Description of the Related Art Digital video signals are recorded / recorded via an electromagnetic conversion system including, for example, a rotary head and a magnetic tape.
When reproducing, reduce the DC component of the recorded / reproduced data,
As a result, randomization (also called scrambling) is performed to prevent waveform distortion of the reproduced signal.

FIG. 2 shows a randomized structure.
A digital video signal to be recorded is supplied to the input terminal 1. This digital video signal is mod.2
(Addition modulo 2) is supplied to the adder 2. This adder 2 can be realized by an exclusive OR gate.
As another input of the adder 2, the M sequence from the M sequence generation circuit 3a is supplied. Randomized data is obtained at the output of the adder 2.

The M-sequence generation circuit 3a includes registers D1 to D
7 includes a shift register connected in cascade, an adder A of mod.2 and a feedback path. The M sequence is one of binary periodic sequences, and has a maximum length period (maximum length) sequence.
Abbreviation for shift register sequence). The M-sequence generation circuit 3a is composed of a feedback shift register. In the example shown in the figure, the primitive polynomial of H (x) = x ⁷ + x ⁶ +1 is used, the number of stages of the shift register is equal to its degree, and the adder A of mod.2 corresponds to the term of x ^6. is doing. A parallel preset value from the input terminal 5 is supplied to each register of the shift register. The preset value is given, for example, at the timing of the sync signal inserted at every predetermined length of the input digital video signal. Presets can also be done in series. The order of the polynomial H (x) described above defines the period of the M sequence as 2 ⁷ −1 = 127.

For the shift registers (D1 to D7),
After x1 to x7 are preset, each time the shift register shifts by the data rate clock,
As shown in FIG. 3, the contents of D1 to D7 change. Timing t0 is a timing at which presetting is performed.
At the next timing, the contents of D7 are (x7 + x6) (+
Means addition of mod.2. And so on)
Data from the previous stage is fetched to D6 to D2, and D1
The contents of D7 are returned to. Thereafter, the shift operation is sequentially performed, and after the above cycle, the initial state is restored. The contents of D7 are supplied to the adder 2 as the M series.

Another example of the randomizing circuit is shown in FIG. The input data is supplied to the adder 9 of mod. 2 in parallel with 8 bits. The M-sequence generation circuit 3b includes a counter 6 and a ROM.
It is composed of 8. A clear pulse synchronized with the synchronization signal is supplied to the counter 6 from the input terminal 7. Counter 6
Counts a clock (not shown) and increments its output. The output of the counter 6 is supplied to the ROM 8 as an address. The ROM 8 generates an 8-bit parallel output in which the M series is divided in order. The output of the ROM 8 is supplied to the adder 9. A randomized output signal is generated from the adder 9 in parallel with 8 bits.

[0007]

In the M-sequence generation circuit 3a shown in FIG. 2, the shift register needs to perform the shift operation with the clock having the same rate as the transmission bit rate of the input digital signal. Therefore, when handling data having a high transmission bit rate such as a digital video signal, there is a problem that a shift register with a considerably high speed is required. Since the M-sequence generation circuit 3b shown in FIG. 4 is a byte parallel process, there is little speed problem, but the ROM is
There is a problem in increasing the circuit scale when integrated into an IC.

Therefore, an object of the present invention is to provide a high-speed circuit,
An object is to provide an M-sequence generation circuit that does not require ROM.

[0009]

SUMMARY OF THE INVENTION The present invention mods to generate a number corresponding to the order of a polynomial for generating M sequences, each corresponding to a series of outputs in the case of a shift register configuration. Adder (11a-
11h) and the output of the plurality of adders (11a to 11h) as parallel data, and a path for feeding back the parallel data to the input side of the adders (11a to 11h). is there.

[0010]

Since the adders 11a to 11h generate M series in parallel, high speed operation is not required. Further, since no ROM is used, there is an advantage that the circuit scale can be small.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In this embodiment, H (x) = x ⁷ + x
^This is an example of ⁶ +1. When the shift register realizes the M-sequence generating circuit corresponding to this polynomial H (x), 7-stage shift register is required. As described above, the 7-stage shift register repeats the operation, for example, with 8 clock cycles of t0 to t7. This invention
Paying attention to this point, operations performed in a period of 8 clocks are performed in parallel.

In FIG. 1, 11a, 11b, ...
Reference numerals 11h denote mod.2 adders that generate a 1-bit output. The output signals of the adders 11a to 11h are supplied to the flip-flops 12a to 12h, respectively. The flip-flops 12a to 12h receive the output of the adder in synchronization with the clock input. The outputs x0 to x7 of the flip-flops 12a to 12h are taken out as 8-bit parallel outputs and fed back to the input side of the adders 11a to 11h. In the initial state, a non-zero 8-bit pattern is stored in the flip-flops 12a to 12h as a preset value. Although the configuration for storing the preset value is omitted in FIG. 1, a switch may be provided on the input side of the flip-flops 12a to 12h to perform presetting in parallel, or the flip-flops 12a to 12h may be configured. The shift register may be configured and preset may be performed in series.

8 is fed back to the adders 11a to 11h.
Bits are selectively supplied and are configured by an exclusive OR gate so as to generate a mod.2 addition output as described below. Adder 11a: x7 + x5 + x4 + x3 + x2 +
x1 adder 11b: x7 + x6 adder 11c: x7 + x6 + x5 adder 11d: x7 + x6 + x5 + x4 adder 11e: x7 + x6 + x5 + x4 + x3 adder 11f: x7 + x6 + x5 + x4 + x3 + x2 + x4 + x5 + x6 + x5 + x6 + x6 + x5 + x6 + x6 + x5 + x6 + x6 + x5
x1 adder 11h: x6 + x5 + x4 + x3 + x2 +
x1

The outputs of these adders 11a to 11h are
As can be seen from FIG. 3 described above, the outputs of eight consecutive clock periods in the configuration using the shift register are arranged in order. The outputs x0 to x7 of the flip-flops 12a to 12h are output as a parallel 8-bit M series. When this M-sequence is used for randomization of the recorded / reproduced digital video signal, it is supplied to the adder of mod. 2 together with the 8-bit parallel digital video signal (not shown).

The above embodiment is an example of a polynomial for generating the M sequence, and other polynomials may be used. In addition to the randomization, the M series can be used.

[0016]

Since the present invention is parallel processing, there is an advantage that the adder and the flip-flop are not required to operate at high speed. Further, the circuit scale can be reduced as compared with the case of using the ROM.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of a conventional randomization configuration.

FIG. 3 is a schematic diagram for explaining an operation when a shift register is used.

FIG. 4 is a block diagram showing another example of a conventional randomization configuration.

[Explanation of symbols]

 11a to 11h mod.2 adder

Claims (1)

[Claims] 1. An adder for adding mod.2 to generate a number corresponding to a degree of a polynomial for generating an M sequence, each of which corresponds to a series of outputs in the case of a shift register configuration. And a path for outputting the outputs of the plurality of adders as parallel data and feeding back the parallel data to the input side of the adder.