JPH05167929A - Amplification type solid state image pickup device - Google Patents

Abstract

PURPOSE:To obtain an amplification type solid state image pickup device capable of reducing a fixed pattern noise on a picked-up image by suppressing a Hall dark current generated by blanking the substrate surface of a gate part in an amplification type cell. CONSTITUTION:A power supply (P.S) is suely set up to a low voltage (e.g. 0V) as an electron injection period once only for a fixed period at the end of each horizontal blanking (HBLK) period and a source and a drain voltages of a MOS transistor constituting the amplification type cell are set up so as to be lower than the surface potential of the gate part, so that the Hall dark current generated due to blanking of the substrate surface of the gate part can be suppressed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplification type solid-state image pickup device, and more particularly to driving an amplification type cell constituting a unit pixel.

[0002]

2. Description of the Related Art As an amplification type solid-state image pickup device, holes (signal charges) obtained by photoelectric conversion are accumulated in a P-type well of an N-channel MOS transistor (= pixel transistor), and a potential change (back) in the P-type well is stored. FWA configured to read change in channel current due to change in gate potential)
The present applicant has proposed a (Floating Well Amplifier) type solid-state imaging device. In this FWA-type amplification type solid-state imaging device, the substrate surface of the gate portion of the MOS transistor is filled with electrons once in one field by the channel current of the read operation, but the other periods are allocated to photoelectric conversion. Has been.

[0003]

However, during the photoelectric conversion period, the source-drain voltage of the MOS transistor is usually a high voltage such as the power supply voltage (for example, 5 V), and the surface potential of the gate portion is not that high. And the surface of the gate portion is depleted. That is, the cycle in which the surface level is filled with electrons is one of the normal read operations.
Once in the field (once every 16.7 msec.), It is longer than the generation recombination life of electrons and holes, and cannot suppress the generation of hole dark current. As a result, the fixed pattern noise on the image pickup screen due to the hole dark current becomes a serious problem.

Therefore, the present invention suppresses the hole dark current generated by the depletion of the substrate surface of the gate portion of the amplification type cell, thereby reducing the fixed pattern noise of the image pickup screen. An object is to provide an imaging device.

[0005]

In the amplification type solid-state image pickup device according to the present invention, at least one of the source voltage and the drain voltage of the MOS transistor constituting the amplification type cell is gated in a predetermined period within the horizontal blanking period. It is configured to be driven so as to be lower than the surface potential of.

[0006]

In the amplification type solid-state image pickup device according to the present invention, the drain and / or source voltage of the MOS transistor constituting the amplification type cell is made lower than the gate surface potential for a certain period in the horizontal blanking period. Electrons are injected from the drain and / or the source to the surface of the gate portion. When the electrons are captured by the surface level existing on the surface of the gate portion and the surface level is filled with the electron, the probability that the electron is excited to the surface level from the valence band is reduced.

If the drain and / or source voltage is lowered every horizontal blanking period, electrons are injected again before the surface level electrons are excited to the conduction band. as a result,
Even if the surface of the gate portion is depleted again after the electron injection period, the hole dark current due to the electrons being excited from the valence band to the surface level is suppressed, and thus fixed pattern noise on the imaging screen can be suppressed.

[0008]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 2 is a configuration diagram of an FWA type amplification type solid-state imaging device according to the present invention. In the figure, amplification type cells 1 composed of MOS transistors for photoelectrically converting incident light and storing the same are arranged in a matrix in a pixel unit. In these amplification type cells 1, the gates of the respective MOS transistors are connected for each horizontal scanning line. It is selected by the vertical scanning circuit 3 via the selected vertical selection line 2.

In the amplification type cell 1, the drain of the MOS transistor is connected to the power supply (PS), and the source is connected to the signal line 4 for each vertical column. A load MOS transistor 5 is connected to the end of the signal line 4 to form a source follower circuit with the MOS transistor of the amplification type cell 1. A transfer gate switch 6 composed of a MOS transistor is further connected to the end of the signal line 4.

A signal for one horizontal scanning line obtained from the source follower circuit is held by a sample hold circuit 7 arranged for each signal line 4, and the horizontal scanning circuit 8 causes a horizontal gate switch 9 consisting of a MOS transistor.
Are sequentially turned on to derive the signal of each pixel. By performing this operation for each horizontal scanning line while sequentially changing the vertical selection line 2 to be selected, the signal output of the solid-state imaging device can be obtained.

However, as shown in the operation timing of FIG. 1, the vertical selection line 2 to be selected during the horizontal blanking period.
Are switched between adjacent odd (O) lines and even (E) lines to perform signal reading twice, and the respective signals are combined in the sample hold circuit 7 to perform field reading.

FIG. 3 shows an amplification type cell 1 which constitutes a unit pixel.
The cross-sectional structure of is shown. An N type well 12 and a P type well 13 are sequentially stacked on a P type silicon substrate 11, and an N ⁺ type drain region 15 and an N ⁺ type source region 16 are formed on the surface side of the P type well 13, respectively. There is. Then, the gate electrode 14 is formed on the vertical selection line 2 and the drain region 1 is formed.
5 is connected to the power source (PS) and the source region 16 is connected to the signal line 4, respectively, to form the equivalent circuit of FIG.

In this amplification type cell 1, the photoelectrically converted holes (signal charges) 17 are accumulated in the P type well 13,
The storage state (A) of FIG. 5 is entered. This accumulated hole 1
7 modulates the channel current 18 in the read operation (B), the source potential of the source follower circuit composed of the amplification type cell 1 and the load MOS transistor 5 changes, and this potential change is derived as a signal output. .. Note that FIG. 5C shows the potential of the gate portion when the reset operation of the amplification type cell 1 and the electronic shutter operation are performed at the same timing.

MO is formed via the drain of the MOS transistor constituting the amplification type cell 1 and the transfer gate switch 6.
The power supply voltage (for example, 5 V) applied to the sources of the S transistors is generated from the power supply unit 21 as shown in FIG. The power supply unit 21 does not constantly output a constant power supply voltage, but as shown in the operation timing of FIG. 1, a constant period immediately before the end of the horizontal blanking (HBLK) period (hereinafter referred to as an electron injection period). ) Lower voltage (for example, 0V) is output. The operation control is performed by the timing generator 22.

By the way, in the conventional example, as shown in the operation timing of FIG. 7, the power supply (PS) is always at a high voltage, and in the equivalent circuit of FIG. 4, the drain of the amplification type cell 1 is fixed to the power supply voltage. Has been done. In addition, the transfer gate switch 6 is ON and the load M
Since the OS transistor 5 is off, it is fixed at the power supply voltage.

However, in the storage state (A) in FIG. 5, since the channel potential is lower than the drain and source voltages, electrons are not supplied from the drain and source, and the gate surface 19 in FIG. 3 is depleted. There is. Therefore, as described above, holes (hole dark current) are generated from the surface states existing on the surface 19 of the gate portion, and these appear as fixed pattern noise (FPN) on the imaging screen.

On the other hand, in the present invention, as shown in the operation timing of FIG. 1, the horizontal blanking (HBL
K), the power source (PS) is set to a low voltage (for example, 0
V). As a result, the amplification type cell 1
The voltage of the drain and the source becomes lower than the potential of the gate surface 19, and electrons are injected into the gate surface 19 from the drain and the source.

When the electrons are trapped by the surface level existing on the surface 19 of the gate portion and the surface level is filled with the electron, the probability that the electron is excited to the surface level from the valence band decreases. The cycle of the horizontal blanking period is 63.5 μsec. In the case of the current television system, and the time constant of occurrence recombination is 1
Since it is sufficiently shorter than msec., if the drain and source voltages are lowered every horizontal blanking period, electrons at the surface level are injected again before being excited to the conduction band.

As a result, even if the surface 19 of the gate portion is depleted again after the electron injection period, holes generated by the electrons being excited from the valence band to the surface level, that is, holes are generated (hole dark current). Will be suppressed. Therefore,
Fixed pattern noise (FPN) of the imaging screen is significantly suppressed by providing an electron injection period in which the source and drain voltages of the amplification type cell 1 are made lower than the potential of the gate surface 19 in each horizontal blanking period. You can do it.

In the above embodiment, the power supply (PS) is normally maintained at a high voltage, and the electron injection period is provided by lowering the voltage for a certain period at the end of the horizontal blanking period. As shown in the operation timing of FIG. 6, the power supply (PS) is set to a high voltage only during the horizontal blanking period during which the signal is read out, and the output of this high voltage is terminated before the horizontal blanking period ends. It is also possible to provide an injection period, and even in this case, the same effect as that of the above-mentioned embodiment can be obtained.

Further, in each of the above-mentioned embodiments, the voltage of both the drain and the source of the MOS transistor constituting the amplification type cell 1 is driven so as to be lower than the potential of the surface 19 of the gate portion. It is also possible to drive one of the sources to have a voltage lower than the potential of the gate surface 19 so that electrons are injected into the gate surface 19 from the drain or the source.

[0022]

As described above, according to the present invention,
This occurs when the surface of the gate substrate is depleted by providing an electron injection period in which at least one of the source voltage and the drain voltage of the MOS transistor forming the amplification cell is lower than the gate surface potential in the horizontal blanking period. By being configured to suppress the hole dark current, it is possible to suppress fixed pattern noise on the imaging screen, and thus it is possible to improve the image quality and contribute to improving the yield of the imaging device.

[Brief description of drawings]

FIG. 1 is a waveform diagram showing an operation timing of an embodiment of the present invention.

FIG. 2 is a configuration diagram of an FWA type amplification type solid-state imaging device.

FIG. 3 is a sectional structural view of a unit pixel.

FIG. 4 is an equivalent circuit diagram of a unit pixel.

FIG. 5 is a potential diagram of a gate portion of an amplification type cell.

FIG. 6 is a waveform chart showing the operation timing of another embodiment of the present invention.

FIG. 7 is a waveform diagram showing conventional operation timing.

[Explanation of symbols]

1 amplification type cell 2 vertical selection line 3 vertical scanning circuit 5 load MOS transistor 7 sample hold circuit 8 horizontal scanning circuit 9 horizontal gate switch 14 gate electrode 15 N ⁺ type drain region 16 N ⁺ type source region 21 power supply unit 22 timing generator

Claims (2)

[Claims] 1. An amplification type solid-state imaging device in which amplification type cells for photoelectrically converting incident light and storing the same are arranged in a matrix on a pixel-by-pixel basis. The amplification type cells are configured in a predetermined period within a horizontal blanking period. An amplification type solid-state imaging device, characterized in that the source and drain voltages of the MOS transistor are driven to be lower than the gate surface potential. 2. An amplification type solid-state imaging device in which amplification type cells for photoelectrically converting incident light and storing the same are arranged in a matrix on a pixel-by-pixel basis. The amplification type cells are configured in a predetermined period within a horizontal blanking period. The amplification type solid-state imaging device, characterized in that the source or drain voltage of the MOS transistor is driven so as to be lower than the gate surface potential.