JPH05167430A - Semiconductor logic circuit - Google Patents

Abstract

PURPOSE:To make an input threshold voltage of the logic circuit stable by providing the logic circuit whose input threshold voltage is adjustable and a circuit generating automatically an input threshold level adjustment voltage to the title circuit. CONSTITUTION:The circuit includes a pMOSP2 as a control MOS transistor(TR) whose drain connects to a source of a pMOSP1 and whose source connects respectively to a power supply VCC as a threshold voltage adjustment means adjusting an input threshold voltage for a CMOS inverter comprising the TRs pMOSMP1, NMOSMN1 and includes a VTC generating circuit 10 as a control voltage generating circuit whose output connects to a gate of the pMOSP2 and outputting a threshold level adjustment voltage VTC. The control voltage generating circuit is of the same configuration as the controlled logic circuit and has a same TR size ratio. Thus, the relation of an input threshold voltage with respect to a gain coefficient beta is kept same and the voltage is the same as a setting voltage given to an input of the control voltage generating circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a semiconductor logic circuit formed as a semiconductor integrated circuit, and more particularly in a CMOS.
The present invention relates to a semiconductor logic circuit composed of a (complementary MOS) gate and a Bi-CMOS (mixed bipolar / CMOS) gate.

[0002]

2. Description of the Related Art In a conventional CMOS inverter, as shown in FIG. 8, the source is a power supply V _CC , the gate is an input IN,
P-type MOS whose drain is connected to output OUT
Transistor (hereinafter referred to as pMOS) MP ₁ and source are grounded, gate is input IN, drain is output O
It has an n-type MOS transistor (hereinafter referred to as nMOS) MN ₁ connected to each UT.

Next, the operation will be described. When input IN is at high potential, pMOSMP ₁ is “off”, nMOSM
N ₁ is turned “on”, and the output OUT becomes low potential. When input IN is at low potential, pMOSMP ₁ is “on”, n
MOSMN ₁ is "off" and the output OUT is at high potential.

When the threshold voltage and the transistor gain coefficient of the pMOS are V _Tp and β _p , and the threshold voltage and the transistor gain coefficient of the nMOS are V _Tn and β _n , -V _Tp = V _Tn β _p = If β _n , the input / output characteristics of the inverter are as shown in FIG. 9, and the input threshold voltage is 1/2 V _CC .

In a normal CMOS IC, V _Tp = -0.7
V, V _Tn = 0.7V, and the threshold voltage is adjusted by changing the ratio of β _p and β _n .

When β _p > β _n , the input threshold voltage shifts to the high potential side as shown in FIG.

When β _p <β _n , the input threshold voltage shifts to the low potential side as shown in FIG. For example, in the case of a TTL interface, if β _p / β _n = 1/6, an input threshold voltage of 1.5V can be obtained when V _CC = 5V.

[0008]

In this conventional CMOS inverter, the input threshold voltages are pMOS and nMOS.
Of the threshold voltage V _Tp and V _Tn and the gain factors β _p and β _n.
However, there is a drawback that it is liable to fluctuate due to the process-related fluctuations, and the change of the power supply potential V _CC .

An object of the present invention is to provide a semiconductor logic circuit in which the input threshold voltage is stabilized by eliminating the above-mentioned drawbacks.

[0010]

According to the present invention, in a logic circuit based on a CMOS inverter, a control MOS transistor connected in series to the CMOS inverter and a gate voltage of the control MOS transistor are set to a predetermined value. And a threshold voltage adjusting means for adjusting an input threshold voltage of the logic circuit.

According to the present invention, the control voltage generating circuit has the same circuit configuration and transistor size ratio as the logic circuit to which the control MOS transistor is connected, and the output thereof is the gate of the control MOS transistor. Connected to a set power supply having an output voltage equal to the input threshold voltage to be set, and its control M
The gate of the OS transistor is preferably connected to the output.

According to the present invention, the semiconductor logic circuit is
An output circuit may be included that includes a bipolar transistor connected to the output of the logic circuit.

[0013]

The threshold voltage adjusting means is, for example, a control p-MOS connected between the pMOS of the CMOS inverter and the power supply V _CC.
It is composed of a MOS and a control voltage generating circuit for controlling the gate voltage of the controlling pMOS to a predetermined value. Since this control voltage generation circuit has the same configuration as the controlled logic circuit and has the same transistor size ratio, the relationship between the input threshold voltage and the gain coefficient β is the same,
It becomes the same as the set voltage applied to the input of the control voltage generation circuit. As a result, the input threshold voltage of the controlled logic circuit is adjusted to be equal to the set voltage by balancing the controlled logic circuit and the control voltage generating circuit via the control MOS transistor.

Further, the logic circuit is applicable including a CMOS inverter, a NAND gate and a NOR gate based on the CMOS inverter, and a Bi-CMOS circuit in which a bipolar transistor is added to the output.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, showing a basic configuration of a semiconductor logic circuit of the present invention.

In the first embodiment, pMOSMP ₁ and nMO are used.
In a CMOS inverter composed of SMN ₁ and SMN ₁ , the drain serves as the threshold voltage adjusting means for adjusting the input threshold voltage of the CMOS inverter, which is the feature of the present invention, and the drain is the source of pMOSMP ₁ Are connected to the power supply V _CC , respectively, and the output is pMOSMP ₂ as a control MOS transistor.
It also includes a V _TC generation circuit 10 as a control voltage generation circuit which is connected to the gate of P ₂ and outputs a threshold adjustment voltage V _TC .

The V _TC generation circuit 10 has a pMOS whose source is connected to the power supply V _CC and whose gate is connected to the output.
And MP _4, the drain of source PMOS MP _4, comprises a PMOS MP ₃ having a drain connected to the output, a drain connected to the drain of the PMOS MP _3, and NMOS NM ₂ whose source is grounded, PMOS MP ₃
And the gate of nMOSMN ₂ are commonly connected and grounded via a power supply V _TR which outputs a threshold voltage V _TR to be set as an output voltage.

Next, the operation of the first embodiment will be described.

First, the principle of adjusting the input threshold voltage V _T of the input threshold adjustment type CMOS inverter constituted by pMOSMP ₁ and MP ₂ and nMOSMN ₁ will be described. As described in the section of the prior art, when the inverter is composed only of pMOSMP ₁ and nMOSMN ₁ , the input threshold voltage V _T is pMOSM.
The gain coefficient β which is the current driving capability of P ₁ and nMOSMN ₁
It is adjusted by the magnitude of _p1 and β _n1 . The ratio of β _p1 and β _n1 is pMO
It is determined by the design values of the gate length and gate width of SMP ₁ and nMOSMN ₁ . In this threshold adjustment type CMOS inverter, β _n1 of the nMOS MN ₁ is determined by the gate length and the gate width at the time of design.
Side current drive capacity cannot be changed, but pM
Since pMOSMP ₁ and MP ₂ are connected in series on the OS side, the current driving capability can be changed by the gate potential of pMOSMP ₂ . Since the gate bias voltage V _GS applied to the pMOSMP ₂ is V _GS = V _TC −V _CC , when the threshold adjustment voltage V _TC becomes low potential, the bias of the pMOSMP ₂ becomes deep and “on”. The resistance is lowered and the current drive capability on the pMOS side is increased, and the input threshold voltage V _T moves to the high potential side. On the contrary, when the threshold adjustment voltage V _TC becomes high, pMOSMP ₂
Has a shallower bias and higher "on" resistance, resulting in pM
The current driving capability on the OS side becomes small, and the input threshold voltage V _T moves to the low potential side.

PMOSMP ₁ and MP ₂ and nM
The threshold voltages V _Tp1 , V _Tp2 and V _{Tn1 of} OSMN ₁ and the gain coefficients β _p1 , β _p2 and β _n1 are −V _Tp1 = −V _Tp2 = V _Tn1 = 0.7V β _p1 : β _p2 : β FIG. 2 shows the relationship between the threshold adjustment voltage V _TC and the input threshold voltage V _T , taking the case of _n1 = 1: 1: 2 as an example. Threshold voltage V _TC
Becomes large to some extent, the input threshold voltage V _T suddenly decreases.

Next, the operation of the _VTC generation circuit 10 will be described. pMOSMP ₃ and MP ₄ , and nMOSM
N _2, respectively to be the same size as PMOS MP ₁ and MP ₂ and NMOS NM _1. pMOSMP
The input threshold voltage of the CMOS inverter composed of ₃ and nMOSMN ₂ is V _T ′. pMOSMP ₁ and n
Similar to the case of MOSMN _1, the threshold voltage V _TC applied to the gate of pMOSMP ₄ changes the input threshold voltage V _T ′. pMOSMP ₃ and nMOS
Consider a case where a threshold voltage V _TR to be set is applied to the input of the CMOS inverter constituted by MN ₂ . It is assumed that the threshold adjustment voltage V _TC is a certain voltage and V _TR > V _T ′ at this time. In this case, since it is equivalent to inputting a high potential to the inverter, the threshold voltage V _TC corresponding to the output moves to the low voltage side. As previously described, 'as a result, V _TR> V _T because increases' approaches from the V _TR = V _T' threshold adjustment voltage V _TC is input threshold voltage V _T to be a low voltage .. On the other hand, when V _TR <V _T ′, it is equivalent to the input of a low voltage to the inverter, so the threshold voltage V _TC moves to the high voltage side and the input threshold voltage V _T ′. is lowered, it approaches 'from _{V TR = V T' V TR} <V T to.

As described above, the threshold voltage V _TR to be set on the gates of pMOSMP ₃ and nMOSMN ₂
It can be seen that the threshold adjustment voltage V _TC automatically settles to a potential V _TR = V _T ′ when V is applied. pMOS
MP ₃ and MP ₄ and nMOSMN ₂ and pMO
Since SMP ₁ and MP ₂ and nMOSMN ₁ have the same configuration, if the threshold adjusting voltage V _TC is applied to the gate of pMOSMP ₂ , pMOSMP ₁ and nMOSM ₁
The input threshold voltage V _T of the CMOS inverter constituted by N ₁ is also automatically adjusted to the set threshold voltage V _TR .

[0024] Figure 3 is an illustration comparing the change in the input threshold voltage V _T with respect to the conventional example of change in the threshold voltage V _Tn of NMOS NM ₁ of the first embodiment and FIG. 8 in Figure 1, It can be seen that the input threshold voltage V _T of the first embodiment is maintained at a substantially constant value.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention, which is an example in which the present invention is applied to a CMOS NAND gate. In FIG. 3, the input IN ₁ is a TTL interface and the input IN ₂ is a CMOS level.

In the second embodiment, pM which constitutes a logic circuit is used.
In addition to OSMP ₁ and MP ₅ and nMOS MN ₁ and MN ₂ , pMOSMP ₂ and V _TC as threshold voltage control means for controlling the input threshold voltage of the logic circuit, which is a feature of the present invention. The generating circuit 10a is included.

The V _TC generation circuit 10a is a pMOS.
And MP _3, MP ₄ and MP _6, the NMOS NM ₂ and MN _4, and a power source V _TR, are formed by transistors of the same dimensions constituting the logic circuit.

Next, the operation of the second embodiment will be described. Also in the second embodiment, as in the first embodiment, p
The drive capability of the MOSMP ₂ is set to the threshold adjustment voltage V based on the set threshold voltage V _TR in the V _TC generation circuit 10a.
By adjusting with _TC , the input threshold voltage V
_T is set to the set threshold voltage V _TR .

FIG. 5 is a characteristic diagram comparing the change of the input threshold voltage V _T with respect to the change of the power supply V _CC in the second embodiment and the conventional example corresponding to the second embodiment. ..
It can be seen from FIG. 5 that the input threshold voltage V _T changes greatly in the conventional example, while in the second embodiment, the set threshold voltage V _TR = 1.5 V is almost maintained.

FIG. 6 is a circuit diagram showing a third embodiment of the present invention, which is obtained by converting the circuit of the first embodiment of FIG. 1 into a Bi-CMOS.

That is, in FIG. 6, the NPN bipolar transistor Q ₁ and the nMOSMN ₅ are added to the circuit of FIG. 1, and the operation is the same as that of the first embodiment.

FIG. 7 is a circuit diagram showing a fourth embodiment of the present invention, in which the circuit of the second embodiment of FIG. 4 is formed into a Bi-CMOS.

That is, in FIG. 7, the NPN bipolar transistor Q ₁ and nMOSMN ₅ and MN ₆ are added to the circuit of FIG. 4, and the operation is the same as that of the second embodiment.

[0034]

As described above, according to the present invention, by the logic circuit capable of adjusting the input threshold voltage and the circuit for automatically generating the input threshold adjusting voltage, the fluctuation of the power supply voltage,
There is an excellent effect that the input threshold voltage of the logic circuit can be stabilized against the process variations such as the threshold voltages V _Tp and V _{Tn of} the transistors and the gain coefficients β _n and β _p .

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a characteristic diagram showing changes in the input threshold voltage V _T with respect to the threshold adjustment voltage V _TC .

FIG. 3 is a characteristic diagram showing changes in the input threshold voltage V _T with respect to variations in the threshold voltage V _Tn of the nMOS in comparison with the conventional example.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a characteristic diagram showing changes in the input threshold voltage V _T with respect to changes in the power supply V _CC , in comparison with the conventional example.

FIG. 6 is a circuit diagram showing a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 8 is a circuit diagram showing a conventional example.

FIG. 9 is an input-output characteristic diagram thereof.

FIG. 10 is an input-output characteristic diagram when the gain coefficient β _p > β _n of the transistor.

FIG. 11 is an input vs. output characteristic diagram when the gain coefficient β _p <β _n of the transistor.

[Explanation of symbols]

10, 10a V _TC generation circuit IN, IN ₁ , IN ₂ input MP _{1 to} MP ₆ p-type MOS transistor MN _{1 to} MN ₆ n-type MOS transistor OUT output Q ₁ NPN bipolar transistor V _CC power supply V _T input threshold voltage V _TC threshold adjustment voltage V _TR power supply (set threshold voltage) V _Tn n MOS transistor threshold voltage β _p , β _n gain factor of transistor

Claims (3)

[Claims] 1. A logic circuit based on a CMOS inverter, comprising a control MO connected in series to the CMOS inverter.
And a threshold voltage adjusting means for adjusting the input threshold voltage of the logic circuit, which is composed of an S transistor and a control voltage generating circuit for controlling the gate voltage of the controlling MOS transistor to a predetermined value. And a semiconductor logic circuit. 2. The control voltage generating circuit comprises the control M
An output voltage having the same circuit configuration and transistor size ratio as the logic circuit to which the OS transistor is connected, the output of which is connected to the gate of the control MOS transistor, and the input of which is the same as the input threshold voltage to be set. 2. The semiconductor logic circuit according to claim 1, wherein the semiconductor logic circuit is connected to a setting power source having a control gate, and the gate of the control MOS transistor is connected to the output. 3. The semiconductor logic circuit according to claim 1, wherein the semiconductor logic circuit has an output circuit including a bipolar transistor connected to an output of the logic circuit.