JPH05167423A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To provide the output buffer circuit stopping a through-current so as to reduce power consumption and to reduce switching noise. CONSTITUTION:A P-channel MOS transistor(TR) 16 and an N-channel MOS TR 17 connected in series are provided between a power supply and ground, its connecting point is used for an output terminal 19, a cathode of a diode 12 whose anode connects to an output terminal of a pre-buffer 11 is connected to a gate electrode of the P-channel MOS TR 16, an anode of a diode 13 whose cathode connects to an output terminal of the pre-buffer 11 is connected to a gate electrode of the N-channel MOS TR 17, a resistor 14 is connected between the output terminal of the pre-buffer 11 connecting to an input terminal 18 and a gate electrode of the P-channel MOS TR 16 and a resistor 15 is connected between the output terminal and the gate electrode of the N-channel MOS TR 17 to form the output buffer circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit which blocks a shoot-through current and reduces power consumption.

[0002]

2. Description of the Related Art Generally, in ICs for digital circuits,
Since the output signal is connected to another IC or transistor, an output buffer circuit is used as its interface. A conventional configuration example of such an output buffer circuit is shown in FIG. 6, and timing charts showing its operation are shown in FIGS. 7 and 8.

As shown in FIG. 6, the output buffer circuit is
Pre-buffer 101 and P-channel MOS transistor 10
2 and an N-channel MOS transistor 103, and P
Channel and N channel MOS transistors 102, 103
Is connected in series between the power supply and the ground, and the output of the pre-buffer 101 is connected to the P-channel and N-channel MOS transistors 102.
, 103 connected to the respective gates, and the connection point of the P-channel and N-channel MOS transistors 102, 103 is used as an output. In addition, 104 is an input terminal and 105 is an output terminal. Then, the input signal IN input from the input terminal 104 is inverted by the pre-buffer 101, and the inverted output is the P-channel and N-channel MOS transistor 102.
, 103, and the output signal OUT in phase with the input waveform is output from the output terminal 105.

[0004]

By the way, in the above conventional output buffer circuit, when the input signal IN having the waveform as shown in FIG. 7 is inputted to the input terminal 104, at the rising and falling edges of the input signal IN, P channel MO
S transistor 102 and N channel MOS transistor 10
3 becomes conductive at the same time, and a through current flows directly from the power supply to ground. When the input signal IN having a blunt waveform as shown in FIG. 8 is input, this through-current becomes long for the P-channel MOS transistor 102 and the N-channel MOS transistor 103 to conduct simultaneously, and a large amount of through-current occurs. Since current flows, there is a drawback in that power consumption increases. Further, this through current causes a problem that the impedance between the power supply and the ground is temporarily lowered to generate radiation noise, which adversely affects the device connected to the digital IC via the output buffer circuit and causes a malfunction. It was

The present invention has been made in order to solve the above problems in the conventional output buffer circuit, and provides an output buffer circuit in which the through current is completely blocked, the power consumption is reduced and the switching noise is reduced. The purpose is to provide.

[0006]

In order to solve the above problems, the present invention provides a pre-buffer 1 connected to an input terminal 6, a power supply and an output terminal 7 as shown in the conceptual diagram of FIG. P-channel MOS transistor 4 connected in between
And an N-channel MOS connected between the output terminal 7 and ground
A transistor 5, a first diode 2 having an anode connected to the output terminal of the pre-buffer 1 and a cathode connected to the gate electrode of the P-channel MOS transistor 4, and an N-channel MO transistor having a cathode connected to the output terminal of the pre-buffer 1
A second diode 3 having an anode connected to the gate electrode of the S-transistor 5, and the first diode 2
So that the charging time of the gate electrode of the P-channel MOS transistor 4 flowing through is faster than the discharging time, and the discharging time of the gate electrode of the N-channel MOS transistor 5 flowing through the second diode 3 is charging time. The output buffer circuit is configured so that it is set to be faster, and the rise time and fall time of the drive signals of the gate electrodes of the P-channel and N-channel MOS transistors 4 and 5 are made different.

In the output buffer circuit thus configured, the rising time t _r of the drive signal for the gate electrode of the P-channel MOS transistor 4 is changed to the falling time t _f.
Becomes shorter, whereas N-channel MOS transistors fall time of the drive signal of the gate electrode of 5 t _f rise time shorter than t _r, the OFF state both transistors are transmitted fast, the ON state is transmitted slowly It Therefore, the P-channel MOS transistor 4 and the N-channel MOS transistor 5 forming the output buffer of the final stage are prevented from becoming conductive at the same time. As a result, power consumption is reduced and switching noise can be reduced.

[0008]

EXAMPLES Next, examples will be described. FIG. 2 is a circuit configuration diagram showing an embodiment of the output buffer circuit according to the present invention. As shown in FIG. 2, the output buffer circuit of this embodiment includes a prebuffer 11, diodes 12, 13 and resistors.
14 and 15, a P-channel MOS transistor 16 and an N-channel MOS transistor 17, which are P-channel and N-channel.
The channel MOS transistors 16 and 17 are connected in series between the power supply and the ground, the drain terminals are commonly connected and led to the output terminal 19, and the source terminals are connected to the power supply and the ground, respectively. Further, the diode 12 is
The anode terminal is connected to the output terminal of the prebuffer 11, the cathode terminal is connected to the gate electrode of the P-channel MOS transistor 16, and the diode 13 has an anode terminal N
The cathode terminal of the channel MOS transistor 17 is connected to the output terminal of the prebuffer 11.

On the other hand, the resistor 14 is connected between the output terminal of the pre-buffer 11 and the gate electrode of the P-channel MOS transistor 16, and the resistor 15 is connected between the output terminal of the pre-buffer 11 and the gate electrode of the N-channel MOS transistor 17. Is connected in between. The input terminal 18 is connected to the input terminal of the prebuffer 11.

Next, the operation of the output buffer circuit configured as described above will be described with reference to the timing chart shown in FIG. First, the input signal IN input from the input terminal 18 is inverted by the pre-buffer 11, and its inverted output A is passed through the diodes 12 and 13 to form the P-channel MOS transistor 16 which constitutes the final output buffer of this output buffer circuit. And to each gate electrode of the N-channel MOS transistor 17. The drive signal B applied to the gate electrode of the P-channel MOS transistor 16 is quickly charged by the forward current of the diode 12 at the rising edge, but discharged at the falling edge through the resistor 14, as shown in FIG. The waveform is rounded. On the other hand, the drive signal C applied to the gate electrode of the N-channel MOS transistor 17 has a blunted waveform because its rising is charged through the resistor 15, and its falling is quickly discharged by the forward current of the diode 13.

Therefore, the rising time t _r of the drive signal B to the gate electrode of the P-channel MOS transistor 16
And the fall time t _f , t _r <t _f , and N
The rising time t _r and the falling time t _f of the drive signal C to the gate electrode of the channel MOS transistor 17 are
t _r > t _f . Therefore, the P-channel and N-channel MOS transistors 16 and 17 change to the OFF state quickly, and change to the ON state slowly. Therefore, both MOS transistors 16 and 17 do not become conductive at the same time, and the through current can be greatly reduced.

Further, since the output of the pre-buffer 11 is connected to the resistors 14 and 15, the forward voltage drop of the diodes 12 and 13 is compensated for. Therefore, the P channel and N channel M
The gate electrodes of the OS transistors 16 and 17 make a full swing to prevent a leak current. It is also possible to change the through current and the delay time by changing the resistance values of the resistors 14 and 15, and the effect is very large.

In the output buffer circuit shown in FIG. 2,
As the diodes 12 and 13, NPN transistors or PNP transistors whose collector and base are short-circuited as shown in FIGS. 4A and 4B can be used instead of ordinary diodes, and NPN transistors are used. In this case, the collector / base terminal is the anode and the emitter terminal is the cathode. When using a PNP transistor, the emitter terminal is the anode and the collector / base terminal is the cathode. The operation when the NPN or PNP transistor whose collector / base is short-circuited is used as a diode is the same as that of the embodiment shown in FIG. 2, but in the case of a BiCMOS gate array or the like, the NPN and PNP transistors are used. Is provided in the I / O area, it can be used.

In the output buffer circuit shown in FIG. 2, the resistors 14 and 15 are P-channel MOS transistors used as pull-up resistors as shown in FIGS. 5A and 5B instead of ordinary resistors. An N-channel MOS transistor used as a transistor or a pull-down resistor can be used. The operation in this case is also the same as that of the embodiment shown in FIG. 2, but the CMOS gate array is usually provided with pull-up resistors and pull-down resistors, and these can be used.

The diodes and resistors used in the above embodiment are
Although other elements can be used as described above, they can be formed by various methods other than the above.

[0016]

As described above on the basis of the embodiments,
According to the present invention, the P-channel MOS transistor and the N-channel MOS transistor forming the output buffer of the final stage do not become conductive at the same time and the through current is completely blocked, thereby reducing the power consumption and simultaneously. Noise due to switching can be reduced and malfunction can be prevented.

[Brief description of drawings]

FIG. 1 is a conceptual diagram for explaining an output buffer circuit according to the present invention.

FIG. 2 is a circuit configuration diagram showing an embodiment of the present invention.

FIG. 3 is a timing chart for explaining the operation of the embodiment shown in FIG.

FIG. 4 is a diagram showing another configuration example of the diode of the embodiment shown in FIG.

5 is a diagram showing another configuration example of the resistor of the embodiment shown in FIG.

FIG. 6 is a circuit configuration diagram showing a conventional output buffer circuit.

FIG. 7 is a timing chart for explaining the operation of the conventional example shown in FIG.

FIG. 8 is a timing chart for explaining the operation of the conventional example shown in FIG.

[Explanation of symbols]

 1,11 Pre-buffer 2,3,12,13 Diode 4,16 P-channel MOS transistor 5,17 N-channel MOS transistor 14,15 Resistance

Claims (5)

[Claims] 1. A prebuffer connected to an input terminal,
A P-channel MOS transistor connected between the power supply and the output terminal, and an N-channel M transistor connected between the output terminal and the ground
An OS transistor, a first diode whose anode is connected to the output terminal of the prebuffer and whose cathode is connected to the gate electrode of the P-channel MOS transistor, and a cathode which is connected to the output terminal of the prebuffer and whose gate electrode is connected to the N-channel MOS transistor. A second diode connected to the anode, so that the charging time of the gate electrode of the P-channel MOS transistor flowing through the first diode is faster than the discharging time, and also through the second diode. The discharge time of the gate electrode of the flowing N-channel MOS transistor is set to be faster than the charging time, and the rising time and the falling time of the drive signals of the gate electrodes of the P-channel and N-channel MOS transistors are made different from each other. Output buffer circuit characterized by. 2. A first resistor is connected between the output terminal of the pre-buffer and the gate electrode of the P-channel MOS transistor, and the output terminal of the pre-buffer and the N-channel MOS are connected.
The output buffer circuit according to claim 1, wherein a second resistor is connected between the gate electrodes of the transistors. 3. A P-channel M used as the pull-up resistor and the pull-down resistor for the first and second resistors.
3. The output buffer circuit according to claim 2, comprising an OS transistor and an N-channel MOS transistor. 4. At least one of the first and second diodes is composed of an NPN transistor having a collector-base short-circuited, and a collector-base terminal is an anode and an emitter terminal is a cathode. The output buffer circuit according to claim 1. 5. A PNP transistor having a collector and a base short-circuited, at least one of the first diode and the second diode, wherein the emitter terminal is an anode and the collector / base terminal is a cathode. The output buffer circuit according to claim 1.