JPH05167391A - Variable filter circuit for reproduced siginal - Google Patents

Abstract

PURPOSE:To improve the degree of freedom for waveform shaping processing of a reproduced signal. CONSTITUTION:The variable filter circuit 1 is provided with a differential sum/subtraction type equalizer 2 waveform-shaping a reproduced signal. The sum subtraction coefficient of the differential sum/subtraction type equalizer 2 is divided to almost independently control the amplitude characteristic and the delay characteristic to attain waveform shaping. A low pass filter 3 is connected to the equalizer 2 and when the amplitude characteristic is made flat, the variable filter circuit 1 is approximated entirely to the Butterworth type. In addition the slope of the delay characteristic is controlled variably almost in the middle of the flat part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a filter circuit used in a data reproducing circuit incorporated in a recording device such as an optical disk, a hard disk or a floppy disk. More specifically, the present invention relates to a variable filter circuit capable of adjusting a cutoff frequency according to a change in the frequency of a reproduction signal.

[0002]

2. Description of the Related Art FIG. 14 shows a typical data reproducing circuit configuration. This circuit includes a magnetic or optical head 101 for reading recorded data from an optical disk, a hard disk, or a floppy disk. The reproduction signal including the pulse train output from the head 101 is preliminarily amplified by the preamplifier 102, and then the AGC is performed.
Automatic gain control is performed by 103. Then filter /
The noise is removed by the amplifier 104, and the waveform is shaped and amplified. The waveform-shaped reproduced signal is converted into a rectangular pulse train by the comparator 105, and the demodulation circuit 106 reproduces the data.

Incidentally, storage devices such as optical disk devices and magnetic disk devices are required to have an increased recording capacity as the processing capability of computer systems advances. Therefore, the data bit density and the track density on the recording medium disk are increased to maximize the recording density per unit area. In order to further improve the recording density, in recent years, the recording density has been changed according to the radius of the disk to further increase the storage capacity. This is a so-called zone bit method, in which the disk surface is divided into a plurality of zones according to the radius to make the recording density of all zones uniform.

When reading data from a disk by a head, a constant linear velocity method and a constant angular velocity method are generally used. In the constant linear velocity method, control is performed so that the reproduction frequency becomes constant in accordance with the change in bit density, that is, the rotational speed is gradually changed following the transition of the disk radius. This method is suitable for serial reading of music information such as a compact disc.

On the other hand, a disk used as an external storage device of a computer is basically capable of random access. In such a case, if the constant linear velocity method is adopted, it is necessary to adjust the number of rotations at each access. However, since disk rotation uses, for example, a spindle motor, there is a problem that the response to the rotation control is low and the actual access time becomes long. Therefore, in the case of random access, the constant angular velocity method is generally adopted. In this system, the head is operated to read data while keeping the number of revolutions of the disk constant, so that the frequency of the reproduction signal inevitably changes.

[0006]

As described above, the frequency of the reproduction signal read from the external storage device of the computer or the like changes. Therefore, it is necessary to variably control the cutoff frequency, the amplitude characteristic, and the like of the reproduction circuit system filter in accordance with the transition of the disc radius. For example, in the case of the data recording format by the above-mentioned zone bit method, conventionally, filter circuits for the number of zones have been prepared and appropriately switched to cope with them. However, this method requires a plurality of individual filter circuits, which makes it difficult to reduce the cost and size of the device.

In recent years, with the progress of semiconductor technology, LSI
It has become possible to integrate a variable frequency filter in the. By using this integrated circuit variable filter,
The cutoff frequency and amplitude characteristics can be adjusted with a single circuit according to the frequency change of the reproduced signal. This adjustment is usually made electrically by firmware and is programmable.

However, the variable filter incorporated in the existing LSI is generally a Bessel type low-pass filter and has a so-called maximum delay flatness characteristic. For this reason, there is a problem or problem that the amplitude characteristic is not well cut off, and noise included in the reproduced signal cannot be sufficiently removed, resulting in a poor S / N ratio. Further, the cut-off frequency of the Bessel type filter needs to be set to twice or more the used band, which is disadvantageous or disadvantageous in terms of frequency characteristics. In addition, in the Bessel type filter, the delay characteristic is maintained flat and the slope cannot be changed. Therefore, there is a problem that the distortion of the reproduction signal pulse due to the asymmetry of bit interference cannot be improved.

Therefore, a first object of the present invention is to provide a variable filter circuit in which the amplitude characteristic is sharply cut and the delay characteristic can be arbitrarily selected.

The reproduced signal contains pulses corresponding to the bits recorded on the disc. The pulse width changes as the frequency of the reproduced signal changes. The higher the dot recording density, the shorter the pulse interval and mutual interference, which may cause a data reproduction error. Therefore, so-called slimming processing is performed as shown in FIG. The waveform indicated by the solid line on the left side of FIG. 15 is the pulse peak shape before processing. When the slimming process is performed, the pulse width becomes smaller as shown by the dotted line, and the data reproduction error due to bit interference can be prevented. This slimming processing may be performed by emphasizing the amplitude characteristic of the variable filter on the high frequency side, as shown on the right side of FIG. That is, by selectively amplifying the high frequency component corresponding to the pulse peak among the frequency components forming the pulse, the low frequency component forming the foot of the pulse is relatively suppressed and the slimming process is performed.

Further, as shown in FIG. 16, individual pulses included in the reproduced signal may be asymmetrically distorted. Since this also causes a data reproduction error, it is necessary to remove the distortion as shown by the dotted line. For this reason, so-called delay correction is performed to relatively adjust the phase relationship of each frequency component forming the pulse. Specifically, as shown on the right side of FIG. 16, the delay characteristic of the variable filter may be increased on the high frequency side, and the high frequency component forming the peak may be delayed relative to the low frequency component.

As described above, in order to remove the deformation and distortion of the pulse included in the reproduction signal, it is necessary to control the amplitude characteristic and the delay characteristic of the filter circuit. For this reason, an equalizer is generally incorporated in the variable filter circuit. However, the conventional equalizer has a problem or a problem that it is difficult to control the amplitude characteristic and the delay characteristic independently, and it is difficult to perform effective waveform shaping.

Therefore, a second object of the present invention is to provide a variable filter which can control the amplitude characteristic and the delay characteristic almost independently.

[0014]

Means for solving the above problems of the prior art and achieving the objects of the present invention will be briefly described with reference to FIG. The variable filter circuit 1 includes a differential-sum difference equalizer 2 that shapes the waveform of a reproduction signal and a low-pass filter 3 having a predetermined function. The addition / subtraction coefficient of the equalizer 2 is divided so that the amplitude characteristic and the delay characteristic can be controlled almost independently to perform waveform shaping. Further, by adding the low-pass filter 3, the input / output characteristic of the variable filter circuit 1 becomes close to that of the Butterworth type when the amplitude characteristic is set flat. Then, the inclination of the delay characteristic can be variably controlled around a substantially flat shape.

The equalizer 2 is a differential sum difference type, and in particular, it performs pulse shaping by performing amplitude correction and phase correction of the high frequency component of the reproduction signal. The equalizer 2 is divided into a front part and a rear part. The front stage section includes a loop including a high-pass filter 4 and a pair of multipliers 5 and 6. The high-frequency component that has passed through the high-pass filter 4 is added to the original input signal after the gain is adjusted by the predetermined coefficients C and D by the multipliers 5 and 6. In the present invention, the divided constants C and D are used. Further, the latter part has the same structure and is composed of the high-pass filter 7 and the pair of multipliers 8 and 9. The coefficient of one multiplier 8 is C, and the coefficient of the other multiplier 9 is D. The high frequency component that has passed through the high pass filter 7 is added to the original reproduction signal after gain adjustment. However, unlike the former stage, in the latter stage, the high frequency components applied via the multipliers 8 and 9 have opposite polarities. In such a configuration, the coefficient common to the front stage and the rear stage is set and controlled at the same time. Further, the high pass filters 4 and 7 are configured by using a transconductance amplifier as described later, and their cutoff frequencies can be variably controlled. The characteristics of the high-pass filters 4 and 7 represented by blocks are represented by transfer functions as shown in the figure.

The low-pass filter 3 is for combining the equalizer 2 to make the variable filter circuit 1 as a whole an amplitude maximum flat characteristic (Butterworth type). Since the Butterworth type has better breakage in amplitude characteristics than the Bessel type, noise included in the reproduced signal can be effectively removed.

[0017]

2 is a transfer function representation of the equalizer 2 shown in FIG. 1 and is summarized as shown. In order to arrange the transfer function display, instead of the coefficient D, the coefficient d =
1-D is used. Further, the coefficient c included in the transfer function is the same as the coefficient C shown in FIG. 1 and is simply replaced to adjust the form. As is clear from this transfer function,
The amplitude characteristic of the equalizer 2 is characterized by the first term of the numerator and the delay characteristic is also characterized by the second term. That is, the delay characteristic can be adjusted only by the value of the coefficient d, regardless of the value of the coefficient c. When the coefficient d is fixed, the amplitude characteristic can be adjusted by controlling the coefficient c.

For example, as shown in FIG. 3, d = 1 (D =
When set to 0), the transfer function display shown in FIG. 2 is simplified as shown on the left side of FIG. As is clear from this simplified transfer function display, the amplitude characteristic changes with the coefficient c. When c = 0 is set, the equalizer 2 has a mere squared first-order low-pass characteristic. Further, if c = 1 is set, the equalizer 2 becomes an all-pass filter.

For example, when c = 1 is set, the amplitude characteristic of the equalizer 2 becomes flat. Therefore, by connecting the low pass filter 3 having Butterworth characteristics to this equalizer, the variable filter circuit 1 becomes approximately Butterworth type as a whole approximately. Therefore, it is possible to obtain the variable filter circuit 1 having a good amplitude characteristic. Also, the delay characteristic is constant regardless of the value of c. Therefore, by correcting the delay characteristic obtained when the coefficient d of the equalizer 2 is set to a certain value in a combination with the low-pass filter 3, the variable filter circuit 1 having a delay characteristic substantially equivalent to that of the conventional Bessel type is obtained. can get. However, some ripple is actually included. If the coefficient d is changed with this state as a reference, the slope of the delay characteristic can be variably controlled with a substantially flat center.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the drawings. First, with reference to FIG. 4, an example of a basic circuit as a constituent element of the variable filter circuit according to the present invention will be described. This basic circuit is a 4-terminal input, 2-terminal output type frequency variable amplifier. The basic circuit comprises a transconductance amplifier or gm amplifier 11, a load capacitance 12 connected to its output terminal, and a pair of emitter follower type buffer transistors 13. gm
The amplifier 11 takes an output signal as a current while an input signal is a voltage. Its conductance is variable. If you connect a resistor to the output, it becomes a variable gain amplifier,
If a capacitor is connected, it becomes a filter. In the illustrated example, the load capacitance 12 is connected to the current output terminal of the gm amplifier 11.
Is connected, a variable RC integrator is obtained. g
The output current amount of the m-amplifier 11 is the difference between the input voltages applied to the bases of a pair of transistors, for example, Q1 and Q2, and the transconductance (gm of a circuit configured by two long tail pairs Q1-Q2 and Q3-Q4 ) And the product. On the other hand, this transconductance gm is the tail current I2 of one long tail pair Q3-Q4.
Is the tail current I of the other long tail pair Q1-Q2.
It is a function of the ratio divided by 1 and the emitter resistance R.
When the capacitor 12 is connected to the output terminal of the gm amplifier 11, the band of this basic circuit becomes a function of the transconductance gm and the load capacitance. Therefore, one tail current I2
, The frequency response characteristic of the output voltage Vout with respect to the input voltage Vin of the basic circuit can be adjusted. The output current Iout of the gm amplifier 11 is obtained as the difference between the currents flowing through the pair of transistors Q3 and Q4.
When the above-described operation is expressed by a mathematical expression, Iout = gm
× Vin = (1 / R) × (I2 / I1) × Vin.

The output current Iout charges and discharges the load capacitance 12 according to its polarity. As a result, the AC output voltage Vout is obtained via the buffer 13. Expressing this AC output voltage by a mathematical expression, Vout = (gm / sC) × Vi
n = (1 / s × _REQ × C) × Vin. Where R
_EQ is the reciprocal of the transconductance gm. In this way, a variable RC integrator or a first-order variable low-pass filter can be obtained by changing gm. By controlling gm, the cutoff frequency of the filter can be adjusted. In the basic circuit shown in FIG. 4, if an input signal is applied via the load capacitance 12, a first-order high pass filter can be easily obtained.

FIG. 5 shows a block representation of the basic circuit described above. As shown in the figure, it comprises a 4-terminal input stage, a variable transconductance stage or gm stage, and a pair of buffer stages. This basic block is easily LSI
It is possible to realize a high-order complicated variable filter circuit having various functions.

Next, FIG. 6 shows an example in which the variable filter circuit 1 shown in FIG. 1 is configured by using the basic block shown in FIG.
As shown in the figure, this variable filter circuit has a structure in which a primary low-pass filter 31, an equalizer 2, and two secondary low-pass filters 32 and 33 are connected in series. The front stage 21 of the equalizer 2 corresponds to the front stage of the equalizer shown in FIG. 1, and the rear stage 22 corresponds to the rear stage of the equalizer shown in FIG. Further, one primary low-pass filter 31 and two secondary low-pass filters 32 and 33 constitute a fifth-order low-pass filter as a whole and correspond to the low-pass filter 3 shown in FIG. Note that in this example, the first-order low-pass filter 31 may also serve as differentiation, so
It is separated from the next low-pass filter and placed at the beginning.
A control voltage having a cutoff frequency is applied to the gm stage of each block, and a control voltage for setting the coefficients C and D is applied to the multipliers of the equalizer. These control voltages are programmable and programmable by the provided firmware.

FIG. 7 shows a transfer function of the variable filter circuit shown in FIG. That is, the first block 31
Is a first-order low-pass filter, and the next two blocks 2
Reference numerals 1 and 22 are differential sum / difference circuits, and the latter two blocks 3
Reference numerals 2 and 33 indicate second-order low-pass filters, respectively.

Subsequently, referring to FIG. 8, FIG.
A method of setting various parameters of the variable filter circuit shown in will be described. The purpose of this filter design is to approximate the Butterworth type when the amplitude characteristic is set to be flat, and to allow the slope of the delay characteristic to be variably controlled around a substantially flat shape. First, one coefficient C of the equalizer 2 is initialized to 1. At this time, as described above, the equalizer 2 becomes a first-order all-pass filter, so that its amplitude characteristic is flat. Therefore, the filters 31 to 3 other than the equalizer 2 are
It suffices to construct the 5th-order Butterworth characteristic with 3. Note that, in FIG. 8, the primary low-pass filter 31 arranged at the head for facilitating understanding is arranged behind the equalizer 2. The Butterworth type low-pass filter has a maximum amplitude flatness characteristic, the amplitude characteristic is well cut, and has an excellent noise elimination effect. When the coefficient C is set to be smaller than 1, an attenuation type equalizer can be obtained.

Next, when the remaining coefficient D is set to 1, that is, when d is set to 0, ω ₀ of the equalizer 2 is adjusted so that the delay characteristic of the entire variable filter circuit becomes substantially flat.

The operation of the variable filter circuit obtained by combining the coefficient division control type differential sum difference equalizer and the fifth-order Butterworth type low-pass filter will be described with reference to the graphs shown in FIGS. The upper graph shown in FIG. 9 represents the amplitude characteristic. The horizontal axis represents the frequency of the logarithmic memory, and the vertical axis represents the amplitude value in dB. The lower graph represents the delay characteristic, the horizontal axis represents the frequency of the logarithmic memory, and the vertical axis represents the delay time.
The delay time is standardized based on the value when the frequency is 0.01 in the logarithmic memory. In the graph of FIG. 9, one coefficient C is set to 0 and the other coefficient D is set to 0.
It shows the case where it is changed between ~ 2. In the amplitude characteristic graph, the coefficient D is changed in steps of 1, and in the delay characteristic graph, it is changed in steps of 0.5. Similarly, the graph shown in FIG. 10 shows the case where the coefficient C is set to 1. Moreover, FIG.
1 is the case where the coefficient C is set to 2, and the graph of FIG. 12 is the case where the coefficient C is set to 3.

The variable filter circuit shown in FIG. 8 has a coefficient C = 1.
When the coefficient D is 1, perfect Butterworth characteristics are obtained, and when the coefficient D = 1, substantially flat delay characteristics are obtained. Therefore, first, this point will be confirmed with reference to FIG. As is clear from the upper amplitude characteristic graph, the amplitude is substantially flat and sharply falls near the cutoff frequency. It can be seen that it has an ideal maximum amplitude flatness characteristic. Also, the other coefficient D
Even if is changed, the amplitude characteristic is hardly affected. On the other hand, as is clear from the graph on the lower side, it can be seen that when D is set to 1, this delay characteristic is substantially flat. When the coefficient D is changed to 1.5 or 2, it rises, and when it is changed to 0.5 or 0, it falls. In this way, since the inclination of the delay characteristic can be variably controlled with a substantially flat center, a very effective delay operation of the reproduced signal can be performed.

In the amplitude characteristic graph of FIG. 9, the coefficient C is changed to 0. Therefore, the amplitude tends to be attenuated on the high frequency side. On the contrary, in the case of FIG. 11, since the coefficient C is set to 2, the amplitude characteristic is emphasized on the high frequency side. In the case of FIG. 12, since the coefficient C is set to a higher value of 3, the emphasis on the high frequency side of the amplitude becomes more remarkable. The amplitude enhancement on the high frequency side enables effective slimming processing of the pulse included in the reproduced signal.

Next, focusing on the delay characteristics, FIG. 9 and FIG.
1, in any case of FIG. 12, when the coefficient D = 1,
It can be seen that the delay characteristics are almost flat. Like this
In the variable filter circuit according to the present invention, the amplitude characteristic and the delay characteristic can be controlled substantially independently of each other by individually adjusting the divided addition / subtraction coefficients C and D of the equalizer.

Finally, another example of the variable filter circuit according to the present invention will be described with reference to FIG. Also in this example, the equalizer 2 has the same structure as that of the above-described embodiment and is represented by the same transfer function. In this example, when one coefficient C of the equalizer is set to 0, the low-pass filter 30 in the subsequent stage is provided so that an ideal Butterworth characteristic is obtained.
1 to 304 are designed. As mentioned above, the coefficient C
When = 0, the equalizer 2 has the square characteristic of a first-order low-pass filter. That is, it is equivalent to a second-order low-pass filter when Q = 0.5 is set. Therefore, it is necessary to configure the Butterworth characteristic including this. In this example, since C = 0 is used as a reference, only an emphasis type variable filter circuit can be obtained with respect to the amplitude characteristic. 2 to equalizer 2
By combining the following low-pass filters 301 to 303, it is possible to obtain a variable filter circuit having an 8th-order Butterworth characteristic as a whole.

Since the order of the filter is higher than that of the above-described embodiment, the delay characteristic of the equalizer alone cannot be used for correction. Therefore, one more all-pass filter 30
4 is added. With this configuration, D = 1 (d = 0)
When set to, the delay characteristics of the entire filter circuit are made substantially flat.

[0033]

As described above, according to the present invention, the amplitude characteristic and the delay characteristic can be controlled substantially independently by dividing and adjusting the addition / subtraction coefficient of the differential sum difference equalizer. Therefore, there is an effect that the flexibility of the waveform shaping process of the reproduction signal is improved. In particular, since the delay operation can be effectively performed, it is possible to effectively remove the distortion of the reproduction signal pulse due to the asymmetry of bit interference. or,
Since the amplitude characteristic of the variable filter circuit is set so as to be close to the ideal Butterworth characteristic, the amplitude is cut off better than the conventional Bessel type, and noise can be effectively removed, and the S / N ratio is improved. .. Furthermore, since the slope of the delay characteristic can be variably controlled around a substantially flat shape, there is an effect that it is possible to cope with various types of reproduced signal pulse distortion.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a basic configuration of a reproduction signal variable filter circuit according to the present invention.

FIG. 2 is a transfer function display block diagram of an equalizer incorporated in a variable filter.

FIG. 3 is a transfer function display block diagram of the equalizer.

FIG. 4 is a circuit diagram showing a configuration example of a gm amplifier which is a basic constituent element of a variable filter circuit.

5 is a block representation of the basic components shown in FIG.

FIG. 6 is a block diagram showing an embodiment of a variable filter circuit.

7 is a transfer function display block diagram of the variable filter circuit shown in FIG. 6;

8 is a block diagram showing a parameter design of the variable filter circuit shown in FIG.

FIG. 9 is a graph showing amplitude characteristics and delay characteristics of the variable filter circuit.

FIG. 10 is a graph showing amplitude characteristics and delay characteristics of the variable filter circuit.

FIG. 11 is a graph showing amplitude characteristics and delay characteristics of the variable filter circuit.

FIG. 12 is a graph showing amplitude characteristics and delay characteristics of the variable filter circuit.

FIG. 13 is a transfer function display block diagram showing another embodiment of the variable filter circuit according to the present invention.

FIG. 14 is a block diagram showing a general configuration of a data reproducing circuit incorporating a variable filter circuit.

FIG. 15 is an explanatory diagram of a slimming process of a reproduction signal pulse.

FIG. 16 is a schematic diagram for explaining a delay operation of a reproduction signal pulse.

[Explanation of symbols]

 1 Variable Filter Circuit 2 Equalizer 3 Low Pass Filter 4 High Pass Filter 5 Multiplier 6 Multiplier 7 High Pass Filter 8 Multiplier 9 Multiplier

Claims (2)

[Claims] 1. A variable filter circuit having a differential-sum difference equalizer for shaping the waveform of a reproduced signal, wherein the addition / subtraction coefficient of the differential-sum difference equalizer is divided so that the amplitude characteristic and the delay characteristic can be controlled substantially independently. Variable filter circuit characterized by waveform shaping. 2. The variable filter circuit according to claim 1, wherein when the amplitude characteristic is set to be flat, the variable filter circuit approximates a Butterworth type and the slope of the delay characteristic can be variably controlled around a substantially flat center.