JPH05167030A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent malfunction of a dynamic RAM or the like from occurring, which has a write per bit mode and is formed into a multi-bit constitution, and to improve the reliability of the RAM or the like. CONSTITUTION:Other complementary common data lines IO01*, IO11* and the like, which are not assumed to be in a state that they are connected to each other, or other signal conductors are respectively arranged between complementary common data lines IO00*, IO10* and the like, which are assumed to be in a state that they are simultaneously connected to each other, or the complementary common data lines, which are assumed to be in a state that they are simultaneously connected to each other, are arranged at a distance to such an extent as to be able to ignore mutually a coupling noise or non-inverted and inverted signal conductors of the complementary common data lines, which are assumed to be in a state that they are simultaneously connected to each other, intersect each other and are arranged so that the coupling noise is offset. Thereby, the coupling noise, which is induced from complementary common data lines, in which a write operation is performed, to complementary common data lines, in which a readout operation is performed, in a write per bit mode, is inhibited and the erroneous inversion of a readout signal is prevented from being generated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique which is particularly effective when used for a dynamic RAM (random access memory) having a multi-bit structure having a write per bit mode.

[0002]

2. Description of the Related Art A dynamic RA having a so-called multi-bit structure for simultaneously inputting or outputting a plurality of bits of stored data.
There is M. Further, in such a dynamic RAM, there is a so-called write per bit mode in which a write operation of stored data is performed in a maskable manner with respect to a plurality of memory cells which are simultaneously selected.

A dynamic RAM having a write per bit mode is described, for example, in "Hitachi IC Memory Data Book", pages 391 to 415, published by Hitachi, Ltd. in 1991.

[0004]

FIG. 5 shows a dynamic RAM developed by the present inventors prior to the present invention.
A partial circuit block diagram of is shown. This dynamic RAM has a write per bit mode and a 4
It has a so-called x4 bit structure for simultaneously inputting or outputting bit storage data. The dynamic RAM has a total of eight sets of complementary common data lines IO to which four sets of designated complementary bit lines of the memory array ARY0 or ARY1 and the memory array ARY2 or ARY3 are selectively connected.
00 * to IO31 * (here, for example, the non-inverted common data line IO00 and the inverted common data line IO00B are collectively denoted by an asterisk such as the complementary common data line IO00 *. A so-called inverted signal or an inverted signal line which is selectively set to a low level is represented by adding B to the end of its name. These complementary common data lines are connected to the corresponding main amplifier MA0.
0 to MA31 are coupled to the input terminals of the data input buffers DIB0 to DIB3 through the write switch MOSFETs receiving the write control signals DIC00 to DIC31 at their gates.

When the dynamic RAM is set to the normal read mode, the main amplifiers MA00 to MA31
Is the main amplifier selection signal M as illustrated in FIG.
Four of them are selectively activated according to S0 to MS1.
Further, when the dynamic RAM is set to the normal write mode, the write switch MOSFETs are selectively turned on in groups of four in accordance with the write control signals DIC00 to DIC31. As a result, the adjacent four sets of complementary common data lines IO00 * and IO10 * and IO20 * and IO30 * or IO01 * and IO11 * and IO21 * and IO31 * serve as input circuits for the data input buffers DIB0 and DIB1.
Alternatively, the data output buffers DOB0 to DOB that serve as output circuits
The DOB3 is selectively connected to realize the input or output operation of 4-bit storage data for the selected four memory cells.

Next, when the dynamic RAM is set to the write per bit mode, the write control signal DIC0
The 0 to DIC 31 are selectively formed in accordance with predetermined max data, whereby the corresponding write switch MOSFET is selectively turned on. As a result, the write operation of the storage data to the selected four memory cells is selectively executed for each bit. At this time, a normal read operation is performed on the memory cell in which the write operation is not performed, and the read data is output via the corresponding data input / output terminals DQ0 to DQ3.

However, the inventors of the present application have found that the dynamic RAM of FIG. 5 has the following problems. That is, when the selective write operation in the write per bit mode is performed, one of the non-inversion and the inversion signal line of the corresponding complementary common data line is at a high level like the power supply voltage of the circuit and the other is at the circuit level. It is fully swung to a low level like the ground potential of each. At this time, in the other complementary common data line where the write operation is not executed, the normal read operation is performed as described above, and the levels of the non-inverted and inverted signal lines thereof are the same as the parasitic capacitance of the selected complementary bit line. It becomes a predetermined intermediate level set by charge sharing with the parasitic capacitance of the complementary common data line. Moreover, the complementary common data line on which the read operation is performed is the complementary common data line arranged adjacent to the complementary common data line on which the write operation is performed, as described above. As a result, a relatively large coupling noise is induced from the complementary common data line on which the write operation is performed to the complementary common data line on which the read operation is performed, and the wrong read data is output due to this coupling noise. Is.

An object of the present invention is to suppress coupling noise between complementary common data lines in the write per bit mode and prevent erroneous inversion of a read signal.
Another object of the present invention is to prevent malfunction of a dynamic RAM having a write-per-bit mode and a multi-bit configuration, and to improve its reliability.

[0009]

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM having a write-per-bit mode and a multi-bit configuration, other complementary common data lines or other signal lines that are not connected between complementary common data lines that are simultaneously connected. , Or the complementary common data lines that are connected simultaneously are placed with a distance such that coupling noise between them can be ignored, or the non-inverted and inverted signals of the complementary common data lines that are connected simultaneously. The lines are arranged crossing each other so that their coupling noise is canceled out.

[0010]

According to the above means, in the write-per-bit mode, the coupling noise induced from the complementary common data line on which the write operation is performed to the complementary common data line on which the read operation is performed can be suppressed. Inversion can be prevented. As a result, a dynamic type R having a write per bit mode and having a multi-bit configuration
It is possible to prevent malfunctioning of AM or the like and improve its reliability.

[0011]

FIG. 1 is a partial circuit block diagram of a first embodiment of a dynamic RAM to which the present invention is applied. Based on the figure, an outline of the structure and operation of the dynamic RAM of this embodiment and its features will be described. The circuit elements of FIG. 1 and the circuit elements constituting each block are formed on one semiconductor substrate such as P-type single crystal silicon together with other circuit elements (not shown) of the dynamic RAM. In the following circuit block diagram, the MOSFET (metal oxide semiconductor type field effect transistor shown in FIG.
SFET is a generic term for an insulated gate field effect transistor), but it is not particularly limited, but all are N channel MOSFETs.

In FIG. 1, the dynamic RAM is
A total of four memory arrays ARY0 and A arranged symmetrically across the corresponding sense amplifier SA0 or SA1.
It comprises RY1 and ARY2 and ARY3. Each memory array includes a plurality of word lines (not shown) arranged in parallel in the vertical direction in the figure, and n + 1 sets of complementary bit lines B0 * to Bn * arranged in parallel in the horizontal direction. At the intersections of these word lines and complementary bit lines, a plurality of dynamic memory cells (not shown) are arranged in a grid pattern. In this embodiment, complementary bit lines B0 * to B forming the memory arrays ARY0 to ARY3.
Each group of n * is divided into four groups, and a total of p + 1, that is, (n + 1) / 4 groups of complementary bit line groups are formed.

The n + 1 sets of complementary bit lines B0 * to Bn * forming the memory arrays ARY0 and ARY1 are connected to the sense amplifier S via a shared MOSFET (not shown).
It is coupled to one of the corresponding switch MOSFETs of A0. The other of the switch MOSFETs is sequentially commonly connected to the non-inverted and inverted signal lines of the complementary common data lines IO00 * to IO11 *. In addition, these switch MOSFE
Eight gates are commonly connected to each complementary bit line group, and corresponding bit line selection signals YS0 to YSp are supplied from a Y address decoder (not shown). As a result, the switch MOSF configuring the sense amplifier SA0
ETs are selectively turned on by eight by corresponding high-level bit line selection signals YS0 to YSp being selectively turned on, and are complementary to the corresponding four sets of complementary bit lines of the memory array ARY0 or ARY1. Common data line IO00 *
To IO11 * are selectively connected.

Similarly, memory arrays ARY2 and ARY
3 of n + 1 complementary bit lines B0 * to Bn *
Are coupled to one of the corresponding switch MOSFETs of the sense amplifier SA1 via a shared MOSFET (not shown). The other of the switch MOSFETs is sequentially commonly coupled to the non-inverted and inverted signal lines of the complementary common data lines IO20 * to IO31 *. Further, the gates of these switch MOSFETs are commonly coupled for each complementary bit line group, and the corresponding bit line selection signals YS0 to YSp are supplied from the Y address decoder. As a result, the switch MOSFE forming the sense amplifier SA1
Ts are selectively turned on by eight by corresponding high levels of the bit line selection signals YS0 to YSp being selectively turned on, and are complementary to the corresponding four sets of complementary bit lines of the memory array ARY2 or ARY3. Common data line IO20 * ~
IO31 * is selectively connected.

Complementary common data lines IO00 * to IO31 *
Is coupled to the input terminals of the corresponding main amplifiers MA00 to MA31, and at the same time, an N-channel write M
Corresponding data input buffer DIB via OSFET
Two sets of output terminals 0 to DIB3 (input circuit) are commonly coupled to each other. The two gates of the write MOSFET are commonly coupled to each other, and a corresponding write control signal DI is output from a timing generation circuit TG (not shown).
C00 to DIC31 are supplied. On the other hand, the output terminals of the main amplifiers MA00 and MA10 to MA30 and MA31 correspond to the corresponding data output buffers DOB0 to DOB.
Two of them are commonly connected to the input terminals of B3 (output circuit). In addition, four main amplifiers MA00 to MA3
0 is commonly supplied with the main amplifier selection signal MS0 from the timing generation circuit TG, and the remaining four main amplifiers MA01 to MA31 are supplied with the main amplifier selection signal MS1.
Are commonly supplied. Data input buffer DIB0-D
Input terminal of IB3 and data output buffer DOB0
~ DOB3 output terminals are corresponding data input / output terminals D
Commonly coupled to Q0 to DQ3, respectively.

Here, the write control signals DIC00 to DIC
When the dynamic RAM is set to the normal write mode, the IC 31 has four corresponding write control signals DIC00 to DIC30 or DIC01 to DI.
C31 is selectively and simultaneously brought to the high level. As a result, the write operation is simultaneously performed on four of the selected eight memory cells of the memory arrays ARY0 to ARY3. On the other hand, when the dynamic RAM is set to the write per bit mode, the write control signals DIC00 to DIC31 correspond to the corresponding write control signals DIC00 to DIC30 or DIC01 to DIC3.
1 is selectively set to a high level according to predetermined mask data. As a result, the write operation to four of the selected eight memory cells in total is selectively performed in bit units. Next, the main amplifier selection signal MS
0 and MS1 are alternatively formed when the dynamic RAM is in the normal read mode or the write per bit mode. As a result, four main amplifiers MA
00 to MA30 or MA01 to MA31 are selectively and simultaneously operated, and the read signals output from four of the selected eight memory cells in total are simultaneously amplified.

That is, the dynamic RA of this embodiment
In M, four sets of complementary common data lines IO00 * to IO11 * and IO are provided corresponding to each sense amplifier.
20 * to IO31 * are substantially connected every other set, and two adjacent sets of complementary common data lines are not connected at the same time. In other words, another complementary common data line that is not connected is arranged between the two sets of complementary common data lines that are simultaneously connected, whereby two sets of complementary common data that are simultaneously connected are provided. This results in the wire being substantially shielded.

As is well known, the data input buffer DIB
The write operation of the stored data by 0 to DIB3 selectively selects the levels of the non-inverted and inverted signal lines of the complementary common data lines IO00 * to IO31 * such as the high level such as the power supply voltage of the circuit or the ground potential of the circuit. It is realized by full swing to low level. In addition, corresponding complementary bit lines B0 * to Bn * from the selected memory cell
The read signal that is output to is once fully swung to a high level or a low level by the corresponding unit amplifier circuit of the sense amplifier SA0 or SA1, but the complementary bit line and the complementary common data lines IO00 * to IO31 * are connected. At that time, the charge is shared according to the ratio of the respective parasitic capacitances, and it becomes a predetermined intermediate level and is transmitted to the main amplifiers MA00 to MA31. Therefore,
The read signal transmitted through the complementary common data line is
It becomes susceptible to the write signal that is fully swung on the complementary common data line. However, in this embodiment, the complementary common data lines that are simultaneously connected are arranged across the other complementary common data lines that are not connected. Therefore, even if the write and read operations of the stored data are selectively and simultaneously performed bit by bit in the write per bit mode, the complementary common data line on which the write operation is performed to the complementary common data line on which the read operation is performed is performed. As a result, the coupling noise that is induced is suppressed, so that the read signal on the complementary common data line on which the read operation is performed can be prevented from being erroneously inverted. As a result, it is possible to prevent malfunction of the dynamic RAM having the write-per-bit mode and the multi-bit configuration, and to improve its reliability.

FIG. 2 is a partial circuit block diagram of a second embodiment of a dynamic RAM to which the present invention is applied. Since the following embodiments basically follow the dynamic RAM of the embodiment of FIG. 1, description will be added only to the parts different from this. In the circuit block diagram below, the memory array A
Only the portions corresponding to RY0 and ARY1 are partially shown.

In FIG. 2, main amplifiers MA00 to M
A31 is, as illustrated, two adjacent main amplifiers MA00 and MA10 and MA01 and MA1.
1 etc. are activated at the same time, and 2 adjacent to this
The pair of complementary common data lines IO00 * and IO10 * and IO01 * and IO11 * are brought into the connected state at the same time. Therefore, in the dynamic RAM of this embodiment, the non-inverted and inverted signal lines of each complementary common data line and the adjacent complementary common data lines that are not simultaneously connected are arranged at a relatively short distance d1. Of two complementary common data lines IO00 * and I
O10 * and IO01 * and IO11 * are arranged at a predetermined distance d2 so that mutual coupling noise becomes negligible. Therefore, like the embodiment of FIG. 1, even when the write and read operations of the stored data are selectively and simultaneously performed bit by bit in the write per bit mode, the read operation is performed from the complementary common data line on which the write operation is performed. Coupling noise induced on the complementary common data line on which the operation is performed is suppressed, and thus erroneous inversion of the read signal can be prevented. As a result, it is possible to prevent the malfunction of the dynamic RAM having the write per bit mode and the multi-bit configuration, and to improve the reliability thereof.

FIG. 3 is a partial circuit block diagram of a third embodiment of a dynamic RAM to which the present invention is applied. In the figure, the main amplifier MA00
2 to MA31 are adjacent to each other, as in the embodiment of FIG.
Main amplifiers MA00 and MA10 and MA0
1 and MA11 etc. are activated at the same time, and accordingly, two sets of adjacent complementary common data lines IO00 * and IO
10 * and IO01 *, IO11 *, etc. are simultaneously set in the connected state. Therefore, in the dynamic RAM of this embodiment, one of the adjacent complementary common data lines IO is
Non-inverting and inverting signal lines such as 00 * and IO01 * are arranged to intersect each other in the middle of the corresponding sense amplifier SA0. Therefore, even if the write and read operations of the stored data are selectively and simultaneously performed bit by bit in the write per bit mode, the complementary common data line on which the write operation is performed to the complementary common data line on which the read operation is performed is performed. The coupling noises that are induced by the two signals cancel each other out, and thereby erroneous inversion of the read signal can be prevented. As a result, it is possible to prevent malfunction of the dynamic RAM having the write-per-bit mode and the multi-bit configuration, and to improve its reliability.

FIG. 4 shows a partial circuit block diagram of a fourth embodiment of a dynamic RAM to which the present invention is applied. This embodiment is a modification of the embodiment shown in FIG. 3, and complementary common data lines IO10 * and IO11 * with which the non-inverted and inverted signal lines intersect are other complementary common data lines IO00 * and IO10. Are arranged in the middle of the non-inverted and inverted signal lines of the. In other words, the non-inverted and inverted signal lines of the two sets of complementary common data lines that are connected at the same time are arranged at substantially the same distance. Therefore, in the write per bit mode, the coupling noise induced from the complementary common data line on which the write operation is performed to the complementary common data line on which the read operation is performed causes the coupling noise of the complementary common data line on which the read operation is performed. The same amount is obtained in the inverted and inverted signal lines, and the canceling effect is further increased. As a result, the reliability of the dynamic RAM having the write per bit mode and having a multi-bit structure is further improved.

As shown in the above embodiment, the present invention is applied to a semiconductor memory device such as a dynamic RAM having a write-per-bit mode and having a multi-bit configuration, to obtain the following operation. The effect is obtained. That is, (1) in a dynamic RAM having a write-per-bit mode and configured in multiple bits, another complementary common data line that is not connected is placed between complementary common data lines that are simultaneously connected. By doing so, it is possible to suppress the coupling noise induced from the complementary common data line in which the write operation is performed in the write per bit mode to the complementary common data line in which the read operation is performed. (2) In a dynamic RAM having a write-per-bit mode and a multi-bit configuration, the complementary common data lines that are simultaneously connected are arranged at a distance such that mutual coupling noise can be ignored. By that,
In the write per bit mode, it is possible to suppress the coupling noise induced from the complementary common data line on which the write operation is performed to the complementary common data line on which the read operation is performed.

(3) In a dynamic RAM having a write-per-bit mode and a multi-bit configuration, the coupling noise cancels the non-inverted and inverted signal lines of the complementary common data line which are simultaneously connected. By arranging as much as possible to cross each other, the coupling noise induced in the complementary common data line in which the read operation is performed from the complementary common data line in which the write operation is performed in the write per bit mode is canceled and suppressed. The effect that can be obtained is obtained. (4) According to the above items (1) to (3), it is possible to prevent erroneous inversion of the read signal on the complementary common data line in which the read operation is performed in the write per bit mode. (5) According to the above items (1) to (4), it is possible to prevent a malfunction of a dynamic RAM having a write-per-bit mode and a multi-bit configuration and to improve its reliability. can get.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, adjacent complementary common data lines are prohibited from being simultaneously connected, and other complementary common data lines that are not equivalently connected between complementary common data lines that are equivalently simultaneously connected. However, the same effect can be obtained by arranging, for example, a power supply voltage supply line or a ground potential supply line between complementary common data lines that are simultaneously connected.
3 and 4, the non-inverted and inverted signal lines of the complementary common data line may be crossed a plurality of times, and the crossing position is not restricted by this embodiment. Further, in FIG. 1 to FIG. 4, the number of memory arrays forming the dynamic RAM, the number of complementary common data lines provided corresponding to each sense amplifier, and the specific configuration of the dynamic RAM are different from those in the various embodiments. Can be taken. The dynamic RAM can also have the same write per bit function in, for example, the nibble mode and other operation modes.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic type RAM which is the field of application which is the background of the invention has been described.
The present invention is not limited to this, and can be applied to, for example, a static RAM similarly having a plurality of complementary common data lines, a gate array integrated circuit incorporating these memories, and the like. The present invention can be widely applied to a semiconductor memory device having at least a write per bit mode and a multi-bit configuration, and a digital integrated circuit device incorporating such a semiconductor memory device.

[0027]

In a dynamic RAM having a write-per-bit mode and a multi-bit configuration, another complementary common data line which is not connected between complementary common data lines which are simultaneously connected or other Signal lines are arranged, or complementary common data lines that are connected at the same time are arranged at a distance such that coupling noise between them can be ignored, or non-inversion of complementary common data lines that are connected at the same time By arranging the inverted signal lines and the inverted signal lines so as to cross each other so as to cancel the coupling noise, a complementary common data line in which a read operation is performed from a complementary common data line in which a selective write operation is performed in the write per bit mode. It is possible to suppress the coupling noise induced in the read signal and prevent erroneous inversion of the read signal. As a result, it is possible to prevent a malfunction of a dynamic RAM having a write per bit mode and a multi-bit configuration, and to improve its reliability.

[Brief description of drawings]

FIG. 1 is a partial circuit block diagram showing a first embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a partial circuit block diagram showing a second embodiment of a dynamic RAM to which the present invention is applied.

FIG. 3 is a partial circuit block diagram showing a third embodiment of a dynamic RAM to which the present invention is applied.

FIG. 4 is a partial circuit block diagram showing a fourth embodiment of a dynamic RAM to which the present invention is applied.

FIG. 5 is a partial circuit block diagram showing an example of a dynamic RAM developed by the inventors of the present application prior to the present invention.

[Explanation of symbols]

B0 * to Bn * ... Complementary bit lines, ARY0 to ARY
3 ... Memory array, SA0-SA1 ... Sense amplifier, IO00 * -IO31 * ... Complementary common data line, DIB0-DIB3 ... Data input buffer, M
A00-MA31 ... Main amplifier, DOB0-DO
B3 ... Data output buffer.

Claims (3)

[Claims] 1. A complementary common data line which comprises at least four sets of complementary common data lines for simultaneously selecting at least two sets of complementary bit lines from one memory array and connecting them to an input circuit and an output circuit, and which are connected at the same time. Between complementary common data lines that are simultaneously connected and have a function of performing a storage data write operation through any one of the data lines and a storage data read operation through any of the other data lines. A semiconductor memory device characterized in that another complementary common data line or another signal line which is not connected to is arranged. 2. A complementary common data line having at least four sets of complementary common data lines for simultaneously selecting at least two sets of complementary bit lines from one memory array and connecting them to an input circuit and an output circuit, and being connected simultaneously. It has a function of performing a storage data write operation via any one of the data lines and a storage data read operation via any of the other data lines, and the complementary common data lines which are simultaneously connected are connected to each other. A semiconductor memory device, wherein the semiconductor memory device is arranged at a distance such that the coupling noise of the above can be ignored. 3. A complementary common circuit having at least four sets of complementary common data lines for simultaneously selecting at least two sets of complementary bit lines from one memory array and connecting to the input circuit and the output circuit, and being connected simultaneously. It has a function of performing a storage data write operation via any one of the data lines and at the same time performing a storage data read operation via any of the other data lines. A semiconductor memory device, wherein non-inverted and inverted signal lines are arranged so as to cross each other so as to cancel the coupling noise.