JPH05166867A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPH05166867A
JPH05166867A JP3328972A JP32897291A JPH05166867A JP H05166867 A JPH05166867 A JP H05166867A JP 3328972 A JP3328972 A JP 3328972A JP 32897291 A JP32897291 A JP 32897291A JP H05166867 A JPH05166867 A JP H05166867A
Authority
JP
Japan
Prior art keywords
wiring
integrated circuit
circuit device
semiconductor integrated
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3328972A
Other languages
Japanese (ja)
Inventor
Takashi Miwa
孝志 三輪
Kanji Otsuka
寛治 大塚
Masayuki Shirai
優之 白井
Toshihiro Tsuboi
敏宏 坪井
Toshihiro Matsunaga
俊博 松永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi ULSI Engineering Corp
Hitachi Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP3328972A priority Critical patent/JPH05166867A/en
Publication of JPH05166867A publication Critical patent/JPH05166867A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32153—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
    • H01L2224/32175—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic
    • H01L2224/32188—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being metallic the layer connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To reduce the effective inductance of an interconnection formed in a package for a semiconductor integrated circuit device. CONSTITUTION:Lead pins 4, 4 whose current direction is opposite to each other are arranged so as to be close to each other. In addition, interconnection patterns whose current direction is opposite to each other are arranged inside a package substrate 3 so as to be close to each other. In addition, bonding wires 9, 9 whose current direction is opposite to each other are arranged so as to be close to each other. Thereby, the self-inductance of close interconnections is offset by the mutual inductance of the close interconnections.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【産業上の利用分野】本発明は、半導体集積回路装置技
術に関し、特に、多ピン、高速動作の半導体集積回路装
置に適用して有効な技術に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device technology, and more particularly to a technology effective when applied to a multi-pin, high speed operation semiconductor integrated circuit device.

【０００２】[0002]

【従来の技術】多ピン、高速動作の半導体集積回路装置
においては、パッケージ本体に形成された配線のインダ
クタンスに起因するノイズを如何にして抑制するかが課
題となっている。2. Description of the Related Art In a multi-pin, high-speed operation semiconductor integrated circuit device, how to suppress noise caused by the inductance of wiring formed in a package body has been a problem.

【０００３】特に問題となるノイズとして同時切り換え
ノイズがある。同時切り換えノイズは、複数の信号配線
の電位が同時に切り換わる際に、配線のインダクタンス
により、電源用配線またはグランド（以下、ＧＮＤと記
す）用配線の電位が変動するノイズである。Simultaneous switching noise is a particularly problematic noise. Simultaneous switching noise is noise in which the potential of a power supply wiring or a ground (hereinafter referred to as GND) wiring fluctuates due to the wiring inductance when the potentials of a plurality of signal wirings are switched at the same time.

【０００４】同時切り換えノイズによる電源用配線また
はＧＮＤ用配線の電位変動は、半導体集積回路装置の誤
動作の原因となる。本来動作すべきでない信号配線をも
動作させてしまうからである。The potential fluctuation of the power supply wiring or the GND wiring due to the simultaneous switching noise causes the malfunction of the semiconductor integrated circuit device. This is because the signal wiring, which should not be operated, is also operated.

【０００５】現状では、同時切り換えノイズによるＧＮ
Ｄ用配線の電位変動が問題となっている。ＧＮＤの方が
ノイズマージンが狭いからである。しかし、電源電圧が
低電圧化されれば、電源側でも問題となる。At present, GN due to simultaneous switching noise
The potential fluctuation of the D wiring is a problem. This is because GND has a narrower noise margin. However, if the power supply voltage is lowered, there will be a problem on the power supply side.

【０００６】ところで、このようなノイズ対策として従
来は、例えば配線長を短くしたり、配線幅を広くしたり
する等、専ら対象となる配線の自己インダクタンスを低
減する方法を採用している。By the way, as a countermeasure against such noise, conventionally, for example, a method of reducing the self-inductance of the target wiring, such as shortening the wiring length or widening the wiring width, has been adopted.

【０００７】したがって、例えば上記した同時切り換え
ノイズの対策としても、ＧＮＤピンをパッケージ本体の
内周部に集めることでＧＮＤ用配線の長さを短くした
り、ＧＮＤ用配線をベタパターンとしたりする等の方法
を採用している。Therefore, for example, as a measure against the above-mentioned simultaneous switching noise, by collecting the GND pins in the inner peripheral portion of the package body, the length of the GND wiring is shortened, or the GND wiring is formed into a solid pattern. Method is adopted.

【０００８】なお、半導体集積回路装置の多ピン化およ
び高速化については、例えば日経マグロウヒル社、１９
８４年６月１１日発行、「マイクロデバイス、日経エレ
クトロニクス別冊 ｎｏ．２」Ｐ１３０〜Ｐ１４７に記
載がある。Regarding the increase in the number of pins and the speedup of semiconductor integrated circuit devices, see, for example, Nikkei McGraw-Hill, 19
Published on June 11, 1984, "Microdevice, Nikkei Electronics Separate Volume No. 2", P130 to P147.

【０００９】[0009]

【発明が解決しようとする課題】ところが、近年、半導
体集積回路装置においては、益々、多ピン化および高速
化する傾向にあるため、対象となる配線の自己インダク
タンスのみを低減する上記従来技術では、ノイズを抑制
する上で充分な効果が得られないという問題があった。However, in recent years, semiconductor integrated circuit devices tend to have more and more pins and higher speeds. Therefore, in the above-mentioned conventional technique for reducing only the self-inductance of the target wiring, There is a problem that a sufficient effect cannot be obtained in suppressing noise.

【００１０】本発明は上記課題に着目してなされたもの
であり、その目的は、半導体集積回路装置を構成するパ
ッケージ本体に形成された配線の実効的なインダクタン
スを低減することのできる技術を提供することにある。The present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of reducing an effective inductance of wiring formed in a package body constituting a semiconductor integrated circuit device. To do.

【００１１】本発明の前記ならびにその他の目的と新規
な特徴は、明細書の記述および添付図面から明らかにな
るであろう。The above and other objects and novel features of the present invention will be apparent from the description of the specification and the accompanying drawings.

【００１２】[0012]

【課題を解決するための手段】本願において開示される
発明のうち、代表的なものの概要を簡単に説明すれば、
以下のとおりである。Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

【００１３】すなわち、請求項１記載の発明は、パッケ
ージ本体に封止された半導体チップから引き出された配
線のうち、電流方向が互いに対向する配線同士を互いに
近接させて配置した半導体集積回路装置構造とするもの
である。That is, the invention according to claim 1 is a semiconductor integrated circuit device structure in which, of the wirings drawn from the semiconductor chip sealed in the package body, the wirings in which the current directions are opposite to each other are arranged close to each other. It is what

【００１４】請求項５記載の発明は、前記半導体チップ
から引き出された配線の一部を構成するボンディングワ
イヤのうち、電流方向が互いに対向するボンディングワ
イヤ同士を互いに近接させて配置するとともに、前記ボ
ンディングワイヤを多段とした半導体集積回路装置構造
とするものである。According to a fifth aspect of the present invention, among the bonding wires forming a part of the wiring drawn from the semiconductor chip, the bonding wires whose current directions are opposite to each other are arranged close to each other, and the bonding is performed. This is a semiconductor integrated circuit device structure in which the wires are multi-staged.

【００１５】請求項６記載の発明は、前記半導体チップ
から引き出された配線の一部を構成するボンディングワ
イヤのうち、電流方向が互いに対向するボンディングワ
イヤ同士を互いに近接させて配置するとともに、前記ボ
ンディングワイヤの接合部部をウェッジボンディングと
した半導体集積回路装置構造とするものである。According to a sixth aspect of the present invention, among the bonding wires forming a part of the wiring drawn out from the semiconductor chip, the bonding wires whose current directions are opposite to each other are arranged close to each other, and the bonding is performed. A semiconductor integrated circuit device structure in which a wire bonding portion is wedge-bonded is provided.

【００１６】[0016]

【作用】上記請求項１記載の発明によれば、近接させた
配線の各々に流れる電流の向きが互いに逆方向であるた
め、それらの配線間の相互インダクタンスが各々の配線
の自己インダクタンスを打ち消すように働く。According to the first aspect of the present invention, since the directions of the currents flowing in the wirings that are brought close to each other are opposite to each other, the mutual inductance between the wirings cancels the self-inductance of each wiring. To work.

【００１７】すなわち、配線の実効的なインダクタンス
を、配線の自己インダクタンスと配線間の相互インダク
タンスとの差で表すことができる。したがって、配線の
実効的なインダクタンスを従来よりも低減することが可
能となる。That is, the effective inductance of the wiring can be represented by the difference between the self-inductance of the wiring and the mutual inductance between the wirings. Therefore, it is possible to reduce the effective inductance of the wiring as compared with the conventional case.

【００１８】上記した請求項５記載の発明によれば、所
定のボンディングワイヤの左右のみならず上方または下
方側にも、電流方向が逆となるボンディングワイヤを配
置させることができるので、ボンディングワイヤ間の相
互インダクタンスを増大させることが可能となる。According to the invention described in claim 5, the bonding wires whose current directions are opposite can be arranged not only on the right and left sides of the predetermined bonding wire but also on the upper side or the lower side. It is possible to increase the mutual inductance of.

【００１９】上記した請求項６記載の発明によれば、ボ
ンディングワイヤの接合部をウェッジボンディングとし
たことにより、ボンディング部をネイルボンディングと
した場合に比べて隣接するボンディングワイヤの間隔を
狭めることができる。According to the sixth aspect of the invention, since the bonding portion of the bonding wire is wedge-bonded, the interval between the adjacent bonding wires can be narrowed as compared with the case where the bonding portion is nail-bonded. ..

【００２０】このため、ボンディングワイヤ間の電磁結
合力を強化させることができるので、相互インダクタン
スを増大させることが可能となる。Therefore, since the electromagnetic coupling force between the bonding wires can be strengthened, the mutual inductance can be increased.

【００２１】[0021]

【実施例】図１は本発明の一実施例である半導体集積回
路装置の断面図、図２は図１の半導体集積回路装置の所
定部分のリードピンの斜視図、図３は図１の半導体集積
回路装置のパッケージ本体の要部斜視図である。1 is a sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a perspective view of a lead pin of a predetermined portion of the semiconductor integrated circuit device of FIG. 1, and FIG. 3 is a semiconductor integrated circuit of FIG. It is a principal part perspective view of the package main body of a circuit device.

【００２２】図１に示す本実施例の半導体集積回路装置
は、例えばＰＧＡ（Pin Grid Array）形のパッケージ本
体１を有する。パッケージ本体１は、熱拡散板２と、パ
ッケージ基板３と、複数のリードピン４と、キャップ５
とを有している。The semiconductor integrated circuit device of this embodiment shown in FIG. 1 has a PGA (Pin Grid Array) type package body 1, for example. The package body 1 includes a heat diffusion plate 2, a package substrate 3, a plurality of lead pins 4, and a cap 5.
And have.

【００２３】熱拡散板２は、例えば銅（Ｃｕ）からな
り、その表面には酸化処理が施されている。熱拡散板２
の上面には、放熱フィン６が、例えばシリコーンゴム等
からなる接着剤層７ａによって接合されている。放熱フ
ィン６は、例えばアルミニウム（Ａｌ）からなる。The heat diffusion plate 2 is made of, for example, copper (Cu), and its surface is subjected to an oxidation treatment. Heat diffusion plate 2
The heat radiation fins 6 are joined to the upper surface of the with an adhesive layer 7a made of, for example, silicone rubber. The radiation fin 6 is made of, for example, aluminum (Al).

【００２４】熱拡散板２の下面中央には、半導体チップ
８がその主面を図の下方に向けた状態で接合されてい
る。すなわち、本実施例の半導体集積回路装置は、半導
体チップ８で発生した熱を熱拡散板２を通じて放熱フィ
ン６から放散する構造になっている。The semiconductor chip 8 is bonded to the center of the lower surface of the heat diffusion plate 2 with its main surface facing downward in the figure. That is, the semiconductor integrated circuit device of this embodiment has a structure in which the heat generated in the semiconductor chip 8 is dissipated from the heat radiation fins 6 through the heat diffusion plate 2.

【００２５】半導体チップ８は、例えば単結晶シリコン
（Ｓｉ）からなり、その主面側には、例えば動作周波数
が１００ＭＨｚ以上の高速動作を行うＣＭＯＳゲートア
レイ等のような半導体集積回路が形成されている。The semiconductor chip 8 is made of, for example, single crystal silicon (Si), and a semiconductor integrated circuit such as a CMOS gate array which operates at high speed with an operating frequency of 100 MHz or more is formed on the main surface side thereof. There is.

【００２６】この半導体集積回路は、ボンディングワイ
ヤ（以下、単にワイヤという）９およびパッケージ基板
３に形成された後述する配線パターンを通じて、パッケ
ージ基板３の外周に配置されたリードピン４に電気的に
接続されている。This semiconductor integrated circuit is electrically connected to lead pins 4 arranged on the outer periphery of the package substrate 3 through bonding wires (hereinafter simply referred to as wires) 9 and wiring patterns formed on the package substrate 3 which will be described later. ing.

【００２７】リードピン４は、パッケージ基板３に形成
されたスルーホール１０内に挿入された状態で固定され
ている。リードピン４は、例えばコバールからなり、そ
の表面には半田（Ｐｂ／Ｓｎ）コート処理が施されてい
る。リードピン４の直径は、例えば0.３０ｍｍまたは0.
４６ｍｍ程度である。リードピン４の総ピン数は、例え
ば４００ピン程度である。図２にリードピン４の斜視図
を示す。The lead pin 4 is fixed while being inserted into the through hole 10 formed in the package substrate 3. The lead pin 4 is made of, for example, Kovar, and its surface is subjected to a solder (Pb / Sn) coating treatment. The diameter of the lead pin 4 is, for example, 0.30 mm or 0.3.
It is about 46 mm. The total number of lead pins 4 is, for example, about 400 pins. FIG. 2 shows a perspective view of the lead pin 4.

【００２８】本実施例においては、上記半導体チップ８
（図１参照）の図示しない出力バッファ回路部（出力回
路部）の出力に電気的に接続された信号用のリードピン
４ｓの周囲に、出力バッファ回路部にＧＮＤ電位を供給
するＧＮＤ用のリードピン４ｇが２本配置されている。In this embodiment, the semiconductor chip 8 is used.
A GND lead pin 4g for supplying a GND potential to the output buffer circuit unit around a signal lead pin 4s electrically connected to the output of an output buffer circuit unit (output circuit unit) (not shown) (see FIG. 1). Two are arranged.

【００２９】ただし、信号用のリードピン４ｓの周囲に
配置するＧＮＤ用のリードピン４ｇの数は２本に限定さ
れるものではなく種々変更可能であり、少なくとも１本
あれば良い。However, the number of the GND lead pins 4g arranged around the signal lead pins 4s is not limited to two and can be variously changed, and at least one is sufficient.

【００３０】また、同様に、信号用のリードピン４ｓの
周囲には、出力バッファ回路部に電源電位を供給する電
源用のリードピン４ｖが１本配置されている。ただし、
信号用のリードピン４ｓの周囲に配置する電源用のリー
ドピン４ｖも少なくとも１本あれば良い。Similarly, one power supply lead pin 4v for supplying a power supply potential to the output buffer circuit portion is arranged around the signal lead pin 4s. However,
At least one power supply lead pin 4v may be arranged around the signal lead pin 4s.

【００３１】このようにすると、次のような作用を得
る。まず、上記出力バッファ回路部の出力（すなわち、
信号用のリードピン４ｓの電位）がＨｉｇｈレベル（以
下、”Ｈ”レベルと記す）からＬｏｗレベル（以下、”
Ｌ”レベルと記す）に切り換わると、出力バッファ回路
部のＧＮＤに電荷が流れ込むため、信号用のリードピン
４ｓとＧＮＤ用のリードピン４ｇとには、互いに逆方向
の電流が流れる。By doing so, the following effects are obtained. First, the output of the output buffer circuit section (that is,
The potential of the signal lead pin 4s changes from High level (hereinafter referred to as "H" level) to Low level (hereinafter referred to as "H" level).
When it is switched to L level), electric charges flow into GND of the output buffer circuit portion, so that currents in opposite directions flow to the signal lead pin 4s and the GND lead pin 4g.

【００３２】このため、信号用のリードピン４ｓとＧＮ
Ｄ用のリードピン４ｇとの間の相互インダクタンスが、
自己インダクタンスを打ち消す方向に働くので、リード
ピン４ｓ，４ｇの実効的なインダクタンスを低減するこ
とが可能となっている。Therefore, the signal lead pin 4s and the GN
Mutual inductance between the D lead pin 4g and
Since it works in the direction of canceling the self-inductance, it is possible to reduce the effective inductance of the lead pins 4s and 4g.

【００３３】また、出力バッファ回路部の出力が”Ｌ”
レベルから”Ｈ”レベルに切り換わる場合は、信号用の
リードピン４ｓと、電源用のリードピン４ｖとの間に、
リードピン４ｓ，４ｇ間で生じた作用と同様の作用が働
くため、リードピン４ｓ，４ｖの実効的なインダクタン
スを低減することが可能となっている。The output of the output buffer circuit section is "L".
When the level is switched to the “H” level, between the signal lead pin 4s and the power source lead pin 4v,
Since the same action as that produced between the lead pins 4s and 4g works, it is possible to reduce the effective inductance of the lead pins 4s and 4v.

【００３４】ところで、リードピン４の自己インダクタ
ンスＬselfは、次式で表せる。The self-inductance L self of the lead pin 4 can be expressed by the following equation.

【００３５】[0035]

【数１】 [Equation 1]

【００３６】ここで、μ0 は真空の透磁率、Ｘはリード
ピン４の長さ、ａはリードピン４の半径である。Here, μ 0 is the magnetic permeability of vacuum, X is the length of the lead pin 4, and a is the radius of the lead pin 4.

【００３７】また、相互インダクタンスＭは、次式のよ
うになる。The mutual inductance M is given by the following equation.

【００３８】[0038]

【数２】 [Equation 2]

【００３９】ここで、ｄはリードピン４，４間のピッチ
である。Here, d is the pitch between the lead pins 4 and 4.

【００４０】さらに、実効的なインダクタンスＬ
eff は、Ｌeff ＝Ｌself−Ｍで表すことができる。Further, the effective inductance L
eff can be expressed by L eff = L self -M.

【００４１】したがって、リードピン４，４間のピッチ
を縮小する程、相互インダクタンスが増大するので、実
効的なインダクタンスを低減するのに効果的である。Therefore, as the pitch between the lead pins 4 and 4 is reduced, the mutual inductance increases, which is effective in reducing the effective inductance.

【００４２】なお、図示はしないが、リードピン４は、
プリント配線基板のスルーホール内に挿入され、プリン
ト配線基板の配線パターンと電気的に接続されるように
なっている。Although not shown, the lead pin 4 is
It is inserted into the through hole of the printed wiring board and electrically connected to the wiring pattern of the printed wiring board.

【００４３】一方、図１の半導体集積回路装置の熱拡散
板２の下面において、半導体チップ８の周囲には、パッ
ケージ基板３が、例えばシリコーンゴムからなる接着剤
層７ｂによって接合されている。On the other hand, on the lower surface of the heat diffusion plate 2 of the semiconductor integrated circuit device of FIG. 1, the package substrate 3 is bonded around the semiconductor chip 8 by an adhesive layer 7b made of, for example, silicone rubber.

【００４４】パッケージ基板３は、第３図に示すよう
に、複数の絶縁層３ａ〜３ｅが積層されて構成されてい
る。絶縁層３ａ〜３ｅは、例えばビスマレイミドトリア
ジン（ＢＴ）樹脂等のようなプラスチック材料からな
る。As shown in FIG. 3, the package substrate 3 is formed by laminating a plurality of insulating layers 3a to 3e. The insulating layers 3a to 3e are made of a plastic material such as bismaleimide triazine (BT) resin.

【００４５】絶縁層３ａ，３ｂの間には、ＧＮＤ用の配
線パターン１１ｇがベタパターンで形成されている。Ｇ
ＮＤ用の配線パターン１１ｇは、絶縁層３ｂの側壁で折
曲し、絶縁層３ｂ上のボンディングパッド（以下、単に
パッドという）部１１ｇ1 と電気的に接続されている。A wiring pattern 11g for GND is formed in a solid pattern between the insulating layers 3a and 3b. G
The wiring pattern 11g for ND is bent at the side wall of the insulating layer 3b and is electrically connected to a bonding pad (hereinafter simply referred to as a pad) portion 11g 1 on the insulating layer 3b.

【００４６】パッド部１１ｇ1 は、半導体チップ８の主
面外周に形成された共通パッド１２にワイヤ９を通じて
電気的に接続されている。The pad portion 11g 1 is electrically connected to the common pad 12 formed on the outer periphery of the main surface of the semiconductor chip 8 through the wire 9.

【００４７】共通パッド１２は、例えばＡｌまたはＡｌ
合金からなり、半導体チップ８内の出力バッファ回路部
と電気的に接続されている。本実施例においては、共通
パッド１２を設けたことにより、ＧＮＤ用のワイヤ９の
配置の自由度を向上させることが可能となっている。The common pad 12 is, for example, Al or Al.
It is made of an alloy and is electrically connected to the output buffer circuit section in the semiconductor chip 8. In this embodiment, by providing the common pad 12, it is possible to improve the degree of freedom in the arrangement of the GND wire 9.

【００４８】絶縁層３ｂ，３ｃ間は、信号用の配線層と
なっており、その間には、主として信号用の配線パター
ン１１ｓが形成されている。A wiring layer for signals is provided between the insulating layers 3b and 3c, and a wiring pattern 11s mainly for signals is formed between them.

【００４９】信号用の配線パターン１１ｓのパッド部１
１ｓ1 は、ワイヤ９を通じて半導体チップ８のパッド１
３に電気的に接続され、さらにそのパッド１３を通じて
半導体チップ８内の出力バッファ回路部に電気的に接続
されている。Pad portion 1 of signal wiring pattern 11s
1s 1 is the pad 1 of the semiconductor chip 8 through the wire 9.
3 and is electrically connected to the output buffer circuit section in the semiconductor chip 8 through the pad 13.

【００５０】信号用の配線パターン１１ｓのパッド部１
１ｓ1 の片側には、上記したＧＮＤ用の配線パターン１
１ｇのパッド部１１ｇ1 が配置されている。Pad portion 1 of signal wiring pattern 11s
On one side of 1s 1 , the wiring pattern 1 for GND described above
A 1 g pad portion 11g 1 is arranged.

【００５１】また、信号用の配線パターン１１ｓのパッ
ド部１１ｓ1 のもう一方の片側には、電源用の配線パタ
ーン１１ｖのパッド部１１ｖ1 が配置されている。電源
用の配線パターン１１ｖのパッド１１ｖ1 は、ワイヤ９
を通じて、半導体チップ８のパッド１３に電気的に接続
され、さらにそのパッド１３を通じて半導体チップ８の
出力バッファ回路に電気的に接続されている。The pad portion 11v 1 of the power supply wiring pattern 11v is arranged on the other side of the pad portion 11s 1 of the signal wiring pattern 11s. The pad 11v 1 of the wiring pattern 11v for power supply is the wire 9
Through, and is electrically connected to the pad 13 of the semiconductor chip 8 and further electrically connected to the output buffer circuit of the semiconductor chip 8 through the pad 13.

【００５２】これにより、出力バッファ回路部の出力
（すなわち、信号用の配線パターン１１ｓの電位）が”
Ｈ”レベルから”Ｌ”レベルまたは”Ｌ”レベルから”
Ｈ”レベルに切り換わる際に、信号用の配線パターン１
１ｓとＧＮＤ用の配線パターン１１ｇまたは電源用の配
線パターン１１ｖとで互いに逆方向の電流が流れる。As a result, the output of the output buffer circuit section (that is, the potential of the signal wiring pattern 11s) is "
From "H" level to "L" level or "L" level
Wiring pattern 1 for signal when switching to H "level
Currents in opposite directions flow between 1s and the wiring pattern 11g for GND or the wiring pattern 11v for power supply.

【００５３】したがって、上記したリードピン４の場合
と同様に、配線パターンの実効的なインダクタンスを低
減することが可能となっている。Therefore, as in the case of the lead pin 4 described above, it is possible to reduce the effective inductance of the wiring pattern.

【００５４】絶縁層３ｃと絶縁層３ｄとの間には、電源
用の配線パターン１１ｖがベタパターンで形成されてい
る。電源用の配線パターン１１ｖは、絶縁層３ｄの側壁
で折曲し、絶縁層３ｄ上のパッド部１１ｖ2 と電気的に
接続されている。Between the insulating layer 3c and the insulating layer 3d, a power supply wiring pattern 11v is formed in a solid pattern. Wiring patterns 11v for power, and bent by the side walls of the insulating layer 3d, which is electrically connected to the pad portion 11v 2 on the insulating layer 3d.

【００５５】電源用の配線パターン１１ｖのパッド部１
１ｖ2 は、ワイヤ９ａを通じて半導体チップ８のパッド
１３に電気的に接続され、さらにそのパッド１３を通じ
て半導体チップ８内の出力バッファ回路部と電気的に接
続されている。Pad portion 1 of wiring pattern 11v for power supply
1 v 2 is electrically connected to the pad 13 of the semiconductor chip 8 through the wire 9 a and further electrically connected to the output buffer circuit section in the semiconductor chip 8 through the pad 13.

【００５６】このように本実施例においては、信号用の
配線パターン１１ｓの左右のみならず、上下にそれぞれ
電源用の配線パターン１１ｖ、ＧＮＤ用の配線パターン
１１ｇを配置したことにより、信号とＧＮＤまたは電源
との電磁結合がより強化されるので、配線パターン間の
相互インダクタンスを増大させることができ、実効的な
インダクタンスをより低減することが可能となってい
る。As described above, in this embodiment, the wiring pattern 11v for power supply and the wiring pattern 11g for GND are arranged not only on the left and right sides of the wiring pattern 11s for signal, but also on the upper and lower sides, respectively. Since the electromagnetic coupling with the power supply is further strengthened, the mutual inductance between the wiring patterns can be increased, and the effective inductance can be further reduced.

【００５７】絶縁層３ｄ，３ｅ間には、ＧＮＤ用の配線
パターン１１ｇがベタパターンで形成されている。ＧＮ
Ｄ用の配線パターン１１ｇのパッド部１１ｇ2 は、ワイ
ヤ９ｂを通じて上記したＧＮＤ用の配線パターン１１ｇ
のパッド部１１ｇ1 に電気的に接続されている。A wiring pattern 11g for GND is formed in a solid pattern between the insulating layers 3d and 3e. GN
The pad portion 11g 2 of the wiring pattern 11g for D is the wiring pattern 11g for GND described above through the wire 9b.
Is electrically connected to the pad portion 11g 1 .

【００５８】ワイヤ９は、例えば金（Ａｕ）からなり、
ワイヤ９についても信号用とＧＮＤ用または電源用とが
近接した状態で配置されている。このため、ワイヤ９に
おいても相互インダクタンスによって実効的なインダク
タンスが低減されている。The wire 9 is made of, for example, gold (Au),
The wires 9 are also arranged in a state in which the signal and the GND or the power supply are close to each other. Therefore, in the wire 9 as well, the effective inductance is reduced by the mutual inductance.

【００５９】また、本実施例においては、ワイヤ９の接
続構造を多段としたことにより、信号用のワイヤ９の左
右のみならず、斜め上側等にもＧＮＤ用のワイヤ９を配
置できるので、ワイヤ９，９間の相互インダクタンスを
さらに増大させることが可能となっている。Further, in this embodiment, since the connection structure of the wires 9 is multi-staged, the GND wires 9 can be arranged not only on the left and right of the signal wires 9 but also on the diagonally upper side. It is possible to further increase the mutual inductance between 9 and 9.

【００６０】さらに、本実施例においては、ワイヤ９の
接合部がウェッジボンディングとされている。このた
め、その接合部をネイルボンディングとした場合に比べ
て半導体チップ８のパッド１３のピッチを狭めることが
できる。ウェッジボンディングの場合、ネイルボンディ
ングの場合のように接合部がボール状とならないからで
ある。Further, in this embodiment, the bonding portion of the wire 9 is wedge bonded. Therefore, the pitch of the pads 13 of the semiconductor chip 8 can be narrowed as compared with the case where the bonding portion is nail-bonded. This is because, in the case of wedge bonding, the bonding portion does not have a ball shape unlike in the case of nail bonding.

【００６１】この結果、ワイヤ９，９のピッチを狭める
ことができるので、ワイヤ９，９間の電磁結合力がより
強化され、ワイヤ９，９間の相互インダクタンスをさら
に増大させることが可能となっている。As a result, the pitch of the wires 9, 9 can be narrowed, so that the electromagnetic coupling force between the wires 9, 9 is further strengthened and the mutual inductance between the wires 9, 9 can be further increased. ing.

【００６２】このように本実施例によれば以下の効果を
得ることが可能となる。As described above, according to this embodiment, the following effects can be obtained.

【００６３】(1).互いに電流方向が逆となるリードピン
４ｓ，４ｇおよびリードピン４ｓ，４ｖを近接させて配
置したことにより、信号用のリードピン４ｓの電位が切
り換わる際にリードピン４ｓ，４ｇおよびリードピン４
ｓ，４ｖ間の相互インダクタンスが自己インダクタンス
を打ち消すように作用する。この結果、リードピン４の
実効的なインダクタンスを従来よりも低減することが可
能となる。(1). Since the lead pins 4s, 4g and the lead pins 4s, 4v whose current directions are opposite to each other are arranged close to each other, the lead pins 4s, 4g and the lead pin 4s and 4g when the potential of the signal lead pin 4s is switched. Four
Mutual inductance between s and 4v acts to cancel self-inductance. As a result, the effective inductance of the lead pin 4 can be reduced as compared with the conventional case.

【００６４】(2).互いに電流方向が逆となる配線パター
ン１１ｓ，１１ｇおよび配線パターン１１ｓ，１１ｖを
近接させて配置したことにより、リードピン４と同様の
作用によって、パッケージ基板３に形成された配線パタ
ーン１１ｓ，１１ｇ，１１ｖの実効的なインダクタンス
を従来よりも低減することが可能となる。(2). By arranging the wiring patterns 11s and 11g and the wiring patterns 11s and 11v in which the current directions are opposite to each other in close proximity to each other, the wiring formed on the package substrate 3 by the same action as the lead pin 4. It is possible to reduce the effective inductance of the patterns 11s, 11g, and 11v more than before.

【００６５】(3).互いに電流方向が逆となるワイヤ９，
９を近接させて配置したことにより、リードピン４と同
様の作用によって、ワイヤ９の実効的なインダクタンス
を従来よりも低減することが可能となる。(3). Wires 9 whose current directions are opposite to each other,
By arranging 9 close to each other, it is possible to reduce the effective inductance of the wire 9 as compared with the conventional case by the same action as the lead pin 4.

【００６６】(4).ワイヤ９の接続構造を多段としたこと
により、信号用のワイヤ９の左右のみならず、斜め上方
側等にもＧＮＤ用または電源用のワイヤ９を配置でき、
ワイヤ９，９間の相互インダクタンスを増大させること
ができるので、ワイヤ９の実効インダクタンスをさらに
低減することが可能となる。(4). The multi-stage connection structure of the wires 9 allows the GND or power supply wires 9 to be arranged not only on the left and right sides of the signal wire 9 but also on the diagonally upper side.
Since the mutual inductance between the wires 9 and 9 can be increased, the effective inductance of the wire 9 can be further reduced.

【００６７】(5).ワイヤ９の接合部をウェッジボンディ
ングとしたことにより、その接合部をネイルボンディン
グとした場合よりもワイヤ９，９の間隔を狭めることが
できるので、ワイヤ９，９間の電磁結合力をより強化さ
せることができ、ワイヤ９，９間の相互インダクタンス
を増大できる。この結果、ワイヤ９の実効インダクタン
スをさらに低減することが可能となる。(5) Since the bonding portion of the wire 9 is wedge-bonded, the distance between the wires 9 and 9 can be made narrower than when the bonding portion is nail-bonded. The electromagnetic coupling force can be further strengthened, and the mutual inductance between the wires 9 and 9 can be increased. As a result, the effective inductance of the wire 9 can be further reduced.

【００６８】(6).上記(1) 〜(5) により、パッケージ本
体１に形成された配線（リードピン４、配線パターン１
１ｓ，１１ｖ，１１ｇおよびワイヤ９）の実効的なイン
ダクタンスを全体的に従来よりも低減することができる
ので、配線のインダクタンスに起因するノイズを抑制す
ることができ、半導体集積回路装置の動作信頼性を向上
させることが可能となる。(6). The wiring (lead pin 4, wiring pattern 1) formed on the package body 1 by the above (1) to (5).
Since the effective inductance of 1s, 11v, 11g and the wire 9) can be reduced as a whole as compared with the conventional one, noise due to the inductance of the wiring can be suppressed and the operation reliability of the semiconductor integrated circuit device can be reduced. It is possible to improve.

【００６９】以上、本発明者によってなされた発明を実
施例に基づき具体的に説明したが、本発明は前記実施例
に限定されるものではなく、その要旨を逸脱しない範囲
で種々変更可能であることはいうまでもない。Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

【００７０】例えば前記実施例においては、半導体チッ
プ内に形成された出力バッファ回路部に電気的に接続さ
れた配線について説明したが、例えば入力バッファ回路
部（内部回路部）に電気的に接続された配線についても
前記実施例と同様の構造とできる。その場合は、例えば
入力バッファ回路に電源電位を供給する電源用の配線
と、入力バッファ回路部にＧＮＤ電位を供給するＧＮＤ
用の配線とを近接させて配置すれば良い。For example, in the above-described embodiment, the wiring electrically connected to the output buffer circuit section formed in the semiconductor chip has been described, but it is electrically connected to the input buffer circuit section (internal circuit section), for example. The wiring can also have the same structure as in the above embodiment. In that case, for example, a power wiring for supplying a power supply potential to the input buffer circuit and a GND for supplying a GND potential to the input buffer circuit section
It may be arranged close to the wiring for use.

【００７１】また、前記実施例においては、半導体チッ
プにＣＭＯＳ回路が形成されている半導体集積回路装置
に本発明を適用した場合について説明したが、これに限
定されるものではなく種々適用可能であり、例えばＢｉ
Ｃ−ＭＯＳ（Bipolar C-MOS）回路が形成されている半
導体集積回路装置に適用することも可能である。Further, in the above-described embodiment, the case where the present invention is applied to the semiconductor integrated circuit device in which the CMOS circuit is formed on the semiconductor chip has been described, but the present invention is not limited to this and various applications are possible. , For example Bi
It can also be applied to a semiconductor integrated circuit device in which a C-MOS (Bipolar C-MOS) circuit is formed.

【００７２】また、前記実施例においては、ＰＧＡ形の
パッケージ本体を有する半導体集積回路装置に本発明を
適用した場合について説明したが、これに限定されるも
のではなく種々適用可能であり、例えばＱＦＰ（Quad F
lat Package)、ＳＯＰ（Small Outline Package)または
マルチチップモジュール形のパッケージ本体にも適用す
ることが可能である。Further, in the above-mentioned embodiment, the case where the present invention is applied to the semiconductor integrated circuit device having the PGA type package main body has been described, but the present invention is not limited to this and various applications are possible, for example, QFP. (Quad F
(lat package), SOP (Small Outline Package) or multi-chip module type package body.

【００７３】[0073]

【発明の効果】本願において開示される発明のうち、代
表的なものによって得られる効果を簡単に説明すれば、
下記のとおりである。The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

【００７４】(1).すなわち、請求項１記載の発明によれ
ば、近接させた配線の各々に流れる電流の向きが互いに
逆方向であるため、それらの配線間の相互インダクタン
スが各々の配線の自己インダクタンスを打ち消すように
働く。(1) In other words, according to the invention described in claim 1, since the directions of the currents flowing in the wirings which are brought close to each other are opposite to each other, the mutual inductance between these wirings is different from each other. Works to cancel self-inductance.

【００７５】この結果、配線の実効的なインダクタンス
を従来よりも低減することができるので、そのインダク
タンスに起因するノイズを抑制することができ、半導体
集積回路装置の動作信頼性を向上させることが可能とな
る。As a result, the effective inductance of the wiring can be reduced as compared with the conventional case, so that noise due to the inductance can be suppressed and the operation reliability of the semiconductor integrated circuit device can be improved. Becomes

【００７６】(2).請求項５記載の発明によれば、所定の
ボンディングワイヤの左右のみならず上または下側にも
電流方向が逆となるボンディングワイヤを配置させるこ
とができるので、ボンディングワイヤ間の相互インダク
タンスを増大させることが可能となる。(2) According to the invention of claim 5, it is possible to dispose the bonding wires whose current directions are opposite not only on the left and right sides of the predetermined bonding wire but also on the upper side and the lower side. It is possible to increase the mutual inductance between them.

【００７７】この結果、配線の実効的なインダクタンス
をさらに低減することができるので、そのインダクタン
スに起因するノイズを抑制することができ、半導体集積
回路装置の動作信頼性を向上させることが可能となる。As a result, the effective inductance of the wiring can be further reduced, so that the noise due to the inductance can be suppressed and the operational reliability of the semiconductor integrated circuit device can be improved. ..

【００７８】(3).請求項６記載の発明によれば、ボンデ
ィングワイヤの接合部をウェッジボンディングとしたこ
とにより、ボンディング部をネイルボンディングとした
場合に比べて隣接するボンディングワイヤの間隔を狭め
ることができる。(3) According to the invention as defined in claim 6, since the bonding portion of the bonding wire is wedge-bonded, the interval between adjacent bonding wires is narrower than that in the case where the bonding portion is nail-bonded. You can

【００７９】このため、ボンディングワイヤ間の電磁結
合力を強化させることができるので、相互インダクタン
スを増大させることが可能となる。Therefore, the electromagnetic coupling force between the bonding wires can be strengthened, and the mutual inductance can be increased.

【００８０】この結果、配線の実効的なインダクタンス
をさらに低減することができるので、そのインダクタン
スに起因するノイズを抑制することができ、半導体集積
回路装置の動作信頼性を向上させることが可能となる。As a result, the effective inductance of the wiring can be further reduced, so that noise due to the inductance can be suppressed and the operation reliability of the semiconductor integrated circuit device can be improved. ..

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施例である半導体集積回路装置の
断面図である。FIG. 1 is a cross-sectional view of a semiconductor integrated circuit device that is an embodiment of the present invention.

【図２】図１の半導体集積回路装置の所定部分のリード
ピンの斜視図である。FIG. 2 is a perspective view of a lead pin of a predetermined portion of the semiconductor integrated circuit device of FIG.

【図３】図１の半導体集積回路装置のパッケージ本体の
要部斜視図である。3 is a perspective view of a main part of a package body of the semiconductor integrated circuit device of FIG.

【符号の説明】[Explanation of symbols]

１ パッケージ本体 ２ 熱拡散板 ３ パッケージ基板 ３ａ〜３ｅ 絶縁層 ４ リードピン ５ キャップ ６ 放熱フィン ７ａ 接着剤層 ７ｂ 接着剤層 ８ 半導体チップ ９ ワイヤ ９ａ ワイヤ ９ｂ ワイヤ １０ スルーホール １１ｇ 配線パターン １１ｇ1 パッド部 １１ｇ2 パッド部 １１ｓ 配線パターン １１ｓ1 パッド部 １１ｖ 配線パターン １１ｖ1 パッド部 １１ｖ2 パッド部 １２ 共通パッド １３ パッド1 Package Main Body 2 Thermal Diffusion Plate 3 Package Substrate 3a-3e Insulating Layer 4 Lead Pin 5 Cap 6 Radiating Fin 7a Adhesive Layer 7b Adhesive Layer 8 Semiconductor Chip 9 Wire 9a Wire 9b Wire 10 Through Hole 11g Wiring Pattern 11g 1 Pad Part 11g 2 pad part 11s wiring pattern 11s 1 pad part 11v Wiring pattern 11v 1 pad part 11v 2 pad part 12 common pad 13 pad

───────────────────────────────────────────────────── フロントページの続き (72)発明者 大塚 寛治 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 (72)発明者 白井 優之 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 (72)発明者 坪井 敏宏 東京都小平市上水本町５丁目20番１号 日 立超エル・エス・アイ・エンジニアリング 株式会社内 (72)発明者 松永 俊博 東京都青梅市今井2326番地 株式会社日立 製作所デバイス開発センタ内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kanji Otsuka 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device Development Center (72) Inventor Yoshiyuki Shirai 2326 Imai, Ome-shi, Tokyo Hitachi, Ltd. Device development In the Center (72) Inventor Toshihiro Tsuboi 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hitsuritsu Cho-LS Engineering Co., Ltd. (72) Inventor Toshihiro Matsunaga 2326 Imai, Ome-shi, Tokyo Stocks Hitachi Device Development Center

Claims (8)

【特許請求の範囲】[Claims] 【請求項１】 パッケージ本体に封止された半導体チッ
プから引き出された配線のうち、電流方向が互いに対向
する配線同士を互いに近接させて配置したことを特徴と
する半導体集積回路装置。1. A semiconductor integrated circuit device, characterized in that, among wirings drawn from a semiconductor chip sealed in a package body, wirings whose current directions are opposite to each other are arranged close to each other. 【請求項２】 前記半導体チップから引き出された配線
のうち、前記半導体チップの入力回路部に電気的に接続
された電源用配線に、前記半導体チップの入力回路部に
電気的に接続されたグランド用配線を近接させて配置し
たことを特徴とする請求項１記載の半導体集積回路装
置。2. The wiring electrically connected to the input circuit section of the semiconductor chip among the wirings drawn from the semiconductor chip, and the ground electrically connected to the input circuit section of the semiconductor chip. 2. The semiconductor integrated circuit device according to claim 1, wherein the wiring for use is arranged close to each other. 【請求項３】 前記半導体チップから引き出された配線
のうち、前記半導体チップの出力回路部に電気的に接続
された信号用配線に、前記半導体チップの出力回路部に
電気的に接続された電源用配線およびグランド用配線の
少なくとも一方を近接させて配置したことを特徴とする
請求項１記載の半導体集積回路装置。3. A power supply electrically connected to an output circuit unit of the semiconductor chip, to a signal wiring electrically connected to the output circuit unit of the semiconductor chip, of the wirings drawn from the semiconductor chip. 2. The semiconductor integrated circuit device according to claim 1, wherein at least one of the wiring for ground and the wiring for ground is arranged close to each other. 【請求項４】 前記半導体チップから引き出された配線
の一部を構成するボンディングワイヤのうち、電流方向
が互いに対向するボンディングワイヤ同士を互いに近接
させて配置したことを特徴とする請求項１，２または３
記載の半導体集積回路装置。4. The bonding wires forming a part of the wiring drawn out from the semiconductor chip, the bonding wires having current directions opposite to each other are arranged close to each other. Or 3
The semiconductor integrated circuit device described. 【請求項５】 前記ボンディングワイヤを多段としたこ
とを特徴とする請求項４記載の半導体集積回路装置。5. The semiconductor integrated circuit device according to claim 4, wherein the bonding wire has multiple stages. 【請求項６】 前記ボンディングワイヤの接合部をウェ
ッジボンディングとしたことを特徴とする請求項４また
は５記載の半導体集積回路装置。6. The semiconductor integrated circuit device according to claim 4, wherein the bonding portion of the bonding wire is wedge-bonded. 【請求項７】 前記半導体チップから引き出された配線
の一部を構成する配線パターンのうち、電流方向が互い
に対向する配線パターン同士を近接させてパッケージ基
板に配置したことを特徴とする請求項１，２または３記
載の半導体集積回路装置。7. The wiring pattern constituting a part of the wiring drawn from the semiconductor chip, the wiring patterns having current directions opposite to each other are arranged close to each other and arranged on the package substrate. 2. The semiconductor integrated circuit device according to 2 or 3. 【請求項８】 前記半導体チップから引き出された配線
の一部を構成するリードピンのうち、電流方向が互いに
対向するリードピン同士を近接させて配置したことを特
徴とする請求項１，２または３記載の半導体集積回路装
置。8. The lead pin forming a part of the wiring drawn out from the semiconductor chip, the lead pins having current directions opposite to each other are arranged close to each other. Semiconductor integrated circuit device.
JP3328972A 1991-12-12 1991-12-12 Semiconductor integrated circuit device Withdrawn JPH05166867A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3328972A JPH05166867A (en) 1991-12-12 1991-12-12 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3328972A JPH05166867A (en) 1991-12-12 1991-12-12 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPH05166867A true JPH05166867A (en) 1993-07-02

Family

ID=18216177

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3328972A Withdrawn JPH05166867A (en) 1991-12-12 1991-12-12 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH05166867A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014090170A (en) * 2012-10-29 2014-05-15 Lsi Corp Low inductance flex bond with low thermal resistance

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014090170A (en) * 2012-10-29 2014-05-15 Lsi Corp Low inductance flex bond with low thermal resistance

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