JPH10135406A - Semiconductor device mounting structure - Google Patents
Semiconductor device mounting structureInfo
- Publication number
- JPH10135406A JPH10135406A JP8291614A JP29161496A JPH10135406A JP H10135406 A JPH10135406 A JP H10135406A JP 8291614 A JP8291614 A JP 8291614A JP 29161496 A JP29161496 A JP 29161496A JP H10135406 A JPH10135406 A JP H10135406A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- package
- mounting structure
- recess
- lsi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
- H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置の実装
構造に関し、特に複数の半導体装置を高密度に実装する
半導体装置の実装構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting structure, and more particularly to a semiconductor device mounting structure in which a plurality of semiconductor devices are mounted at high density.
【０００２】[0002]
【従来の技術】従来のこの種の半導体装置の実装構造が
実開昭６３−６１１５０号（実願昭６１−１５６５２９
号）公報に開示されている。2. Description of the Related Art A conventional mounting structure of a semiconductor device of this kind is disclosed in Japanese Utility Model Application Laid-Open No. 63-61150 (Japanese Utility Model Application No. 61-156529).
No.) gazette.
【０００３】図５を参照すると、この従来の半導体装置
の実装構造では、多層配線基板に段付きの凹所を形成す
るとともに該凹所に設けられたデバイスピットに１つの
半導体装置１０２を収容搭載してなる１つのパッケージ
ユニット１０１が複数積み重ねられ、積層方向に隣接す
る該パッケージユニット間が導電性材料１０３を介して
電気的に接続されて構成されている。Referring to FIG. 5, in this conventional semiconductor device mounting structure, a stepped recess is formed in a multilayer wiring board, and one semiconductor device 102 is accommodated in a device pit provided in the recess. A plurality of package units 101 are stacked, and the adjacent package units in the stacking direction are electrically connected via a conductive material 103.
【０００４】[0004]
【発明が解決しようとする課題】上述の従来の半導体装
置の実装構造では、上記導電性材料および上記多層配線
基板の内部配線により形成される配線径路が上記パッケ
ージユニットの積層方向に長くなってしまうため、搭載
される半導体装置の電気的特性が悪化してしまうという
問題がある。これは、誘導成分、容量成分および配線抵
抗の各々が増加してしまうためである。In the above-described conventional mounting structure of a semiconductor device, the wiring path formed by the conductive material and the internal wiring of the multilayer wiring board becomes longer in the stacking direction of the package units. Therefore, there is a problem that the electrical characteristics of the semiconductor device to be mounted are deteriorated. This is because each of the inductive component, the capacitive component, and the wiring resistance increases.
【０００５】また、従来の半導体装置の実装構造では、
実装される半導体装置の個数を増加させるに従って実装
された複数のパッケージユニット全体の積層方向の高さ
が増大してしまうため、高密度実装ができないという問
題がある。In the conventional semiconductor device mounting structure,
As the number of semiconductor devices to be mounted increases, the height in the stacking direction of the plurality of mounted package units as a whole increases, so that there is a problem that high-density mounting cannot be performed.
【０００６】本発明の目的は、高密度実装が可能な半導
体装置の実装構造を提供することにある。An object of the present invention is to provide a semiconductor device mounting structure capable of high-density mounting.
【０００７】また、本発明の他の目的は、半導体装置の
電気的特性を良好にする半導体装置の実装構造を提供す
ることにある。It is another object of the present invention to provide a semiconductor device mounting structure that improves the electrical characteristics of the semiconductor device.
【０００８】[0008]
【課題を解決するための手段】上記課題を解決するため
に本発明の半導体装置の実装構造は、パッケージに設け
られた凹部と、この凹部に収容された第１の半導体装置
と、前記凹部の前記第１の半導体装置の上方に収容され
た第２の半導体装置とを含む。In order to solve the above-mentioned problems, a semiconductor device mounting structure according to the present invention comprises a recess provided in a package, a first semiconductor device housed in the recess, and A second semiconductor device housed above the first semiconductor device.
【０００９】また、本発明の他の半導体装置の実装構造
は、パッケージに設けられた第１の凹部と、この第１の
凹部の底面に設けられた第２の凹部と、この第２の凹部
に収容された第１の半導体装置と、前記第１の凹部に収
容され前記第２の凹部を被覆する基板と、この基板に搭
載された第２の半導体装置とを含む。Further, another mounting structure of a semiconductor device according to the present invention includes a first concave portion provided in a package, a second concave portion provided on a bottom surface of the first concave portion, and a second concave portion provided in a bottom surface of the first concave portion. A first semiconductor device housed in the first recess, a substrate housed in the first recess to cover the second recess, and a second semiconductor device mounted on the substrate.
【００１０】また、本発明の他の半導体装置の実装構造
は、パッケージに形成され周辺部に複数の段部からなる
階段状部を有する凹部と、前記複数の段部を用いて上下
方向に並べて搭載された複数の半導体装置とを含む。According to another aspect of the present invention, there is provided a semiconductor device mounting structure in which a recess formed in a package and having a plurality of steps in a peripheral portion and a plurality of steps is arranged vertically using the plurality of steps. And a plurality of mounted semiconductor devices.
【００１１】また、本発明の他の半導体装置の実装構造
は、パッケージに形成され周辺部に第１の段部とこの第
１の段部の上部に設けられた第２の段部とを有する凹部
と、前記第１の段部に設けられた第１の接続用パッド
と、前記凹部に収容され前記第１の接続用パッドに電気
的に接続された第１の半導体装置と、前記第２の段部に
設けられた第２の接続用パッドと、前記凹部の前記第１
の半導体装置の上部に収容され前記第２の接続用パッド
に電気的に接続された第２の半導体装置とを含む。According to another aspect of the present invention, there is provided a semiconductor device mounting structure having a first step formed in a package and a second step provided above the first step in a peripheral portion. A recess, a first connection pad provided in the first step, a first semiconductor device housed in the recess and electrically connected to the first connection pad, A second connection pad provided on the step of
And a second semiconductor device housed above the semiconductor device and electrically connected to the second connection pad.
【００１２】また、本発明の他の半導体装置の実装構造
は、前記パッケージは外部接続用ピンと内部配線とを含
み、前記第１および第２のパッドは前記内部配線を介し
て前記外部接続用ピンに電気的に接続されていることを
特徴とする。In another aspect of the present invention, the package includes an external connection pin and an internal wiring, and the first and second pads are connected to the external connection pin via the internal wiring. Is electrically connected to the power supply.
【００１３】また、本発明の他の半導体装置の実装構造
は、前記第２の半導体装置が搭載される基板と、この基
板に設けられた配線とを含み、前記第２の半導体装置は
前記配線が前記パッケージの内部配線と接続されるよう
に前記第２の接続用パッドに搭載されることを特徴とす
る。According to another aspect of the present invention, there is provided a semiconductor device mounting structure including a substrate on which the second semiconductor device is mounted and wiring provided on the substrate. Is mounted on the second connection pad so as to be connected to the internal wiring of the package.
【００１４】また、本発明の他の半導体装置の実装構造
は、前記パッケージが複数の配線層からなる多層配線構
造を有し、前記凹部は該パッケージの表面に対して段階
的に前記配線基板の積層数を減少させることにより形成
されることを特徴とする。According to another aspect of the present invention, there is provided a semiconductor device mounting structure, wherein the package has a multilayer wiring structure including a plurality of wiring layers, and the concave portion is formed on the surface of the package step by step. It is characterized by being formed by reducing the number of layers.
【００１５】また、本発明の他の半導体装置の実装構造
は、最上部の前記半導体装置の上部に設けられ前記凹部
を被覆するキャップを含む。Further, another mounting structure of the semiconductor device according to the present invention includes a cap provided on the uppermost semiconductor device and covering the concave portion.
【００１６】また、本発明の他の半導体装置の実装構造
は、前記第２の半導体装置と前記キャップとの間に設け
られた熱伝導部材を含む。According to another aspect of the present invention, there is provided a semiconductor device mounting structure including a heat conductive member provided between the second semiconductor device and the cap.
【００１７】また、本発明の他の半導体装置の実装構造
は、前記第１の半導体装置がロジック系の半導体装置で
あり、前記第２の半導体装置がメモリであることを特徴
とする。Further, another mounting structure of the semiconductor device according to the present invention is characterized in that the first semiconductor device is a logic semiconductor device and the second semiconductor device is a memory.
【００１８】[0018]
【発明の実施の形態】次に本発明について図面を参照し
て詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail with reference to the drawings.
【００１９】図１を参照すると、本発明の半導体装置の
実装構造の第一の実施の形態は、パッケージ１に設けら
れた凹部５と、この凹部５に収容されたＬＳＩ２と、凹
部５のＬＳＩ２の上方に収容されたＬＳＩ１２とを含
む。Referring to FIG. 1, a first embodiment of a mounting structure of a semiconductor device according to the present invention includes a recess 5 provided in a package 1, an LSI 2 accommodated in the recess 5, and an LSI 2 in the recess 5. And an LSI 12 housed above the device.
【００２０】パッケージ１はセラミックＰＧＡ（ピング
リッドアレイ）であり、厚さは従来のパッケージと同様
４〜５ミリメートルである。The package 1 is a ceramic PGA (pin grid array), and has a thickness of 4 to 5 mm like the conventional package.
【００２１】パッケージ１には凹部５が設けられてい
る。凹部５にはＬＳＩ２およびＬＳＩ１２が上下方向に
積み重なって収容されるように実装される。凹部５は内
部の周辺部が階段状を呈しており、底部５１、段部５２
および段部５３からなる。段部５２および段部５３はＬ
ＳＩ２およびＬＳＩ１２の実装、接続に用いられる。The package 1 is provided with a recess 5. The recesses 5 are mounted so that the LSIs 2 and 12 are stacked and accommodated in the vertical direction. The concave portion 5 has a stepped inner peripheral portion, and has a bottom portion 51 and a step portion 52.
And a step 53. The steps 52 and 53 are L
Used for mounting and connecting SI2 and LSI12.
【００２２】パッケージ１は多層配線基板からなってお
り、凹部５は配線基板の積層数をパッケージ１の表面に
比べ段階的に減少させることにより形成される。The package 1 is composed of a multilayer wiring board, and the recess 5 is formed by reducing the number of stacked wiring boards in a stepwise manner as compared with the surface of the package 1.
【００２３】段部５２は底部５１からＬＳＩ２の高さと
略同一の高さであり、ＬＳＩ２とパッケージ１の内部配
線とを電気的に接続するためのステッチ３が設けられて
いる。底部５１にＬＳＩ２が搭載され、ＬＳＩ２の外部
接続端子とステッチ３とがリード４を介して接続され
る。The step 52 has a height substantially equal to the height of the LSI 2 from the bottom 51, and is provided with a stitch 3 for electrically connecting the LSI 2 to the internal wiring of the package 1. The LSI 2 is mounted on the bottom 51, and an external connection terminal of the LSI 2 is connected to the stitch 3 via the lead 4.
【００２４】段部５３は、底部５１からの高さがＬＳＩ
２およびリード４を充分に収容できる高さとなってお
り、ＬＳＩ１２とパッケージ１の内部配線とを電気的に
接続するためのステッチ１３が設けられている。The height of the step 53 from the bottom 51 is an LSI.
2 and the lead 4 are sufficiently high, and a stitch 13 for electrically connecting the LSI 12 to the internal wiring of the package 1 is provided.
【００２５】ＬＳＩ１２は基板１１に搭載されている。
基板１１は可撓性を有する基板であり、より具体的には
キャリアフィルムやプラスチック基板である。基板１１
には配線１５が施されており、この配線１５がＬＳＩ１
２とパッケージ１の内部配線とを電気的に接続する。Ｌ
ＳＩ１２の外部接続端子はリード１４を介して配線１５
と接続される。The LSI 12 is mounted on the substrate 11.
The substrate 11 is a flexible substrate, more specifically, a carrier film or a plastic substrate. Substrate 11
The wiring 15 is provided to the LSI 1
2 and the internal wiring of the package 1 are electrically connected. L
An external connection terminal of the SI 12 is connected to a wiring 15 through a lead 14.
Connected to
【００２６】ＬＳＩ１２が搭載された基板１１は、凹部
５に収容され段部５３を用いて搭載される。より具体的
には、半田ボール１６を介してＬＳＩ１２が段部５３に
設けられたステッチ１３に接続され搭載される。ステッ
チ１３はパッケージ１の内部配線と接続されており、パ
ッケージ１の内部配線とＬＳＩ１２の外部接続端子とが
ステッチ１３、半田ボール１６、配線１５およびリード
１４を介して接続される。The substrate 11 on which the LSI 12 is mounted is housed in the recess 5 and mounted using the step 53. More specifically, the LSI 12 is connected to the stitch 13 provided on the step portion 53 via the solder ball 16 and mounted. The stitch 13 is connected to the internal wiring of the package 1, and the internal wiring of the package 1 is connected to the external connection terminal of the LSI 12 via the stitch 13, the solder ball 16, the wiring 15, and the lead 14.
【００２７】段部５３からパッケージ１の表面までは、
ＬＳＩ１２が搭載された基板１１を充分収容できる高さ
を有している。パッケージ１の表面にはシールリング２
３を介してキャップ２２が設けられる。キャップ２２は
凹部５に収容されたＬＳＩ２およびＬＳＩ１２を被覆す
る。キャップ２２の材質はアルミ系の金属であり、その
厚さは０．５ミリメートル程度である。From the step 53 to the surface of the package 1,
It has a height that can sufficiently accommodate the substrate 11 on which the LSI 12 is mounted. Seal ring 2 on the surface of package 1
The cap 22 is provided through the intermediary 3. The cap 22 covers the LSI 2 and the LSI 12 housed in the recess 5. The material of the cap 22 is an aluminum-based metal, and its thickness is about 0.5 mm.
【００２８】ＬＳＩ２とＬＳＩ１２とはパッケージ１の
内部配線を介して互いに電気的に接続されている。外部
接続用ピン２１はＬＳＩ２およびＬＳＩ１２のそれぞれ
とパッケージ１の内部配線を介して電気的に接続されて
いる。The LSI 2 and the LSI 12 are electrically connected to each other via the internal wiring of the package 1. The external connection pin 21 is electrically connected to each of the LSI 2 and the LSI 12 via the internal wiring of the package 1.
【００２９】次に、本実施の形態の製造方法について図
面を参照して詳細に説明する。Next, the manufacturing method of the present embodiment will be described in detail with reference to the drawings.
【００３０】図２（ａ）を参照すると、ＬＳＩ２がパッ
ケージ１の凹部５に収容され、４００度程度の温度が与
えられてＡｕＳｉ（金シリコン）により凹部５の底部５
１に搭載される。ＬＳＩ２の外部接続端子と段部５２に
設けられたステッチ３とはボンディングにより直径３０
μφのアルミ線を介して接続される。Referring to FIG. 2A, the LSI 2 is housed in the recess 5 of the package 1 and is given a temperature of about 400 ° C. and is made of AuSi (gold silicon).
1 The external connection terminal of the LSI 2 and the stitch 3 provided on the step portion 52 are bonded to each other with a diameter of 30 by bonding.
Connected via μφ aluminum wire.
【００３１】図２（ｂ）を参照すると、基板１１にＬＳ
Ｉ１２が３００度程度の温度が与えられエポキシ系の樹
脂により搭載される。基板１１のＬＳＩ１２と対向しな
い主面には半田ボール１６が設けられる。Referring to FIG. 2B, LS is applied to the substrate 11.
I12 is given a temperature of about 300 degrees and is mounted with an epoxy resin. A solder ball 16 is provided on a main surface of the substrate 11 not facing the LSI 12.
【００３２】図２（ｃ）を参照すると、ＬＳＩ１２の外
部接続端子と基板１１に設けられた配線１５とがボンデ
ィングにより直径３０μφのリード１４を介して接続さ
れる。Referring to FIG. 2C, the external connection terminal of the LSI 12 and the wiring 15 provided on the substrate 11 are connected by bonding through the lead 14 having a diameter of 30 μφ.
【００３３】図２（ｄ）を参照すると、ＬＳＩ１２が搭
載された基板１１が凹部５に収容される。３００〜３５
０度の温度で基板１１に設けられた半田ボール１６と段
部５３に設けられたステッチ１３とが接続される。Referring to FIG. 2D, the substrate 11 on which the LSI 12 is mounted is accommodated in the recess 5. 300-35
At a temperature of 0 degrees, the solder ball 16 provided on the substrate 11 and the stitch 13 provided on the step 53 are connected.
【００３４】パッケージ１の表面に設けられたシールリ
ング２３にキャップ２２が搭載され、電気溶接法によっ
て接続される。A cap 22 is mounted on a seal ring 23 provided on the surface of the package 1 and connected by an electric welding method.
【００３５】次に、パッケージに２つのＬＳＩが搭載さ
れた場合の従来技術（実開昭６３−６１１５０号（実願
昭６１−１５６５２９号）公報記載の構成）および本発
明の比較を図面を参照して説明する。Next, a comparison between the prior art in the case where two LSIs are mounted in a package (the configuration described in Japanese Utility Model Application Laid-Open No. 63-61150 (Japanese Utility Model Application No. 61-156529)) and the present invention will be described with reference to the drawings. I will explain.
【００３６】図３（ａ）を参照すると、従来技術および
本発明のそれぞれのパッケージの厚さが比較される。１
つのパッケージの厚さを約５〜６ミリメートルとする
と、従来技術では１つのパッケージが２段重ねられるた
め厚さが約１０〜１２ミリメートルとなってしまうのに
対し、本発明ではパッケージ１つ分の約５〜６ミリメー
トルですむため、従来技術に比べ約５０〜４０パーセン
トの削減が図れる。Referring to FIG. 3A, the thicknesses of the respective packages of the prior art and the present invention are compared. 1
If the thickness of one package is about 5 to 6 mm, the thickness of the package is about 10 to 12 mm in the prior art because one package is stacked in two stages, whereas in the present invention, the thickness of one package is Since only about 5 to 6 mm is required, a reduction of about 50 to 40% can be achieved as compared with the prior art.
【００３７】図３（ｂ）を参照すると、従来技術および
本発明のそれぞれのパッケージ内部の平均配線長が比較
される。パッケージのピン数はともに５２８本とする。
この平均配線長の値は、パッケージの厚さおよび搭載さ
れたＬＳＩからパッケージの外部接続端子までの距離を
考慮して概算したものである。従来技術では平均配線長
が約２６ミリメートルであるの対し、本発明では約１６
ミリメートル程度となるため、約４０パーセントの短縮
ができる。Referring to FIG. 3B, the average wiring lengths inside the respective packages of the prior art and the present invention are compared. The number of pins of each package is 528.
The value of the average wiring length is roughly calculated in consideration of the thickness of the package and the distance from the mounted LSI to the external connection terminal of the package. In the prior art, the average wiring length is about 26 millimeters, whereas in the present invention, the average wiring length is about 16 millimeters.
Since it is on the order of millimeters, it can be reduced by about 40%.
【００３８】このように、本実施の形態によると、パッ
ケージ１に底部５１、段部５２および段部５３からなる
凹部５が設けられ、底部５１および段部５２を用いてＬ
ＳＩ２が、段部５３を用いてＬＳＩ１２がそれぞれ搭載
される。このため、パッケージ１の実装密度を上下方向
の高さを増大させること無く向上させることができる。
また、外部接続用ピン２１とＬＳＩ２またはＬＳＩ１２
との距離、ＬＳＩ２とＬＳＩ１２との距離をそれぞれ短
くすることができるため、パッケージ１内の電気的特性
が向上し高速動作が可能となる。As described above, according to the present embodiment, the package 1 is provided with the concave portion 5 including the bottom portion 51, the step portion 52, and the step portion 53.
The LSI 12 is mounted on the SI 2 using the step portion 53. For this reason, the mounting density of the package 1 can be improved without increasing the vertical height.
The external connection pins 21 and the LSI 2 or the LSI 12
, And the distance between the LSI 2 and the LSI 12 can be shortened, so that the electrical characteristics in the package 1 are improved and high-speed operation is possible.
【００３９】本実施の形態ではパッケージ１をセラミッ
クＰＧＡとしたが、本発明はこれに限定されず種々のパ
ッケージに適用できる。パッケージの厚さは従来のパッ
ケージ同様４〜５ミリメートルとしたが、複数のＬＳＩ
を搭載するためにより厚いパッケージを用いてもよい。In this embodiment, the package 1 is made of ceramic PGA. However, the present invention is not limited to this and can be applied to various packages. Although the thickness of the package was set to 4 to 5 mm like the conventional package, a plurality of LSIs were used.
May be used to mount a thicker package.
【００４０】また、本実施の形態ではＬＳＩの個数は２
つとしたがこれに限定されず３つ以上の個数が適用でき
る。パッケージ１の厚さおよび凹部５の形状は搭載され
るＬＳＩの個数にあわせて適宜選択される。In this embodiment, the number of LSIs is two.
The number is not limited to three, but three or more can be applied. The thickness of the package 1 and the shape of the concave portion 5 are appropriately selected according to the number of LSIs to be mounted.
【００４１】さらに、本実施の形態ではＬＳＩ１２がＬ
ＳＩ２と対向しない向きに搭載されたが、ＬＳＩ２と対
抗する向きに搭載してもよい。すなわち、ＬＳＩ１２と
半田ボール１６とを基板１１の同一の主面に設け、この
基板１１が半田ボール１６を介して凹部５の段部５３に
搭載されるようにしてもよい。Further, in this embodiment, the LSI 12
Although mounted in a direction not facing the SI2, it may be mounted in a direction facing the LSI2. That is, the LSI 12 and the solder balls 16 may be provided on the same main surface of the substrate 11, and the substrate 11 may be mounted on the step 53 of the recess 5 via the solder balls 16.
【００４２】さらに、本実施の形態ではＬＳＩ２および
ＬＳＩ１２を基板１１にボンディングにより実装させた
が、ともにフリップチップ実装であってもよい。Furthermore, in this embodiment, the LSI 2 and the LSI 12 are mounted on the substrate 11 by bonding, but both may be flip-chip mounted.
【００４３】また、本実施の態様において、ＬＳＩ２を
ＣＰＵ等のようなロジック系のＬＳＩ、ＬＳＩ１２をメ
モリとすることができる。これは、ＬＳＩ１２はＬＳＩ
２に比べより面積の広いＬＳＩを搭載できるため、大容
量のメモリに適しているためである。このような構成を
採用することにより、ＣＰＵ等のようなロジック系ＬＳ
Ｉからメモリまでの距離が非常に短くなるため、より高
速な動作が可能となるとともにＣＰＵ等のようなロジッ
ク系ＬＳＩとメモリとを１パッケージで扱えるため保守
性も向上する。In the present embodiment, the LSI 2 can be a logic LSI such as a CPU or the like, and the LSI 12 can be a memory. This is because LSI12 is LSI
This is because an LSI having a larger area can be mounted as compared with the second embodiment, which is suitable for a large-capacity memory. By adopting such a configuration, a logic system LS such as a CPU can be used.
Since the distance from I to the memory is very short, higher-speed operation is possible, and maintainability is improved because a logic LSI such as a CPU and a memory can be handled in one package.
【００４４】さらに、上記実施の形態では平面形状のキ
ャップが設けられたが、凹状を呈するものであってもよ
い。Further, in the above embodiment, the cap having a planar shape is provided, but the cap may have a concave shape.
【００４５】次に、本発明の第二の実施の形態につい
て、図面を参照して詳細に説明する。この第二の実施の
形態の特徴はＬＳＩ１２とキャップ２２との間に設けら
れたヒートスプレッダを含む点にある。Next, a second embodiment of the present invention will be described in detail with reference to the drawings. The feature of the second embodiment is that a heat spreader provided between the LSI 12 and the cap 22 is included.
【００４６】図４を参照すると、ＬＳＩ１２が搭載され
た基板１１は、ＬＳＩ１２がＬＳＩ２と対抗する向きに
凹部５に収容され、半田ボール１６により段部５３に搭
載される。Referring to FIG. 4, the substrate 11 on which the LSI 12 is mounted is accommodated in the recess 5 in a direction in which the LSI 12 faces the LSI 2, and is mounted on the step 53 by the solder balls 16.
【００４７】ヒートスプレッダ３０は基板１１のＬＳＩ
２と対向しない主面にエポキシ系樹脂によって接続され
ている。パッケージ１の表面にはシールリング２３を介
してキャップ２２がヒートスプレッダ３０と当接するよ
うに搭載される。ヒートスプレッダ３０によりＬＳＩ１
２→基板１１→ヒートスプレッダ３０→キャップ２２の
放熱径路が形成され、ＬＳＩ２の熱がキャップを介して
放熱される。The heat spreader 30 is an LSI of the substrate 11
2 is connected to the main surface that does not face 2 by an epoxy resin. A cap 22 is mounted on the surface of the package 1 via a seal ring 23 so as to be in contact with the heat spreader 30. LSI 1 by heat spreader 30
A heat radiation path of 2 → substrate 11 → heat spreader 30 → cap 22 is formed, and heat of the LSI 2 is radiated through the cap.
【００４８】このように、本実施の形態によると、ＬＳ
Ｉ１２が設けられた基板１１およびキャップ２２の両方
に当接されたヒートスプレッダ３０が設けられるため、
ＬＳＩ１２から発生する熱をキャップ２２を介してより
効果的に外部に放熱させることができる。As described above, according to the present embodiment, LS
Since the heat spreader 30 is provided in contact with both the substrate 11 provided with I12 and the cap 22,
The heat generated from the LSI 12 can be more effectively radiated to the outside via the cap 22.
【００４９】本実施の形態ではＬＳＩ１２をＬＳＩ２と
対向する向きに実装し、ヒートスプレッダ３０を基板１
１上のＬＳＩ２と対抗しない主面に設けたが、ＬＳＩ１
２をＬＳＩ２と対抗しない向きに実装し、ヒートスプレ
ッダ３０を該ＬＳＩ１２の上部に当接させるように設け
るとともにキャップを該ヒートスプレッダ３０と当接す
るように設けてもよい。In this embodiment, the LSI 12 is mounted so as to face the LSI 2 and the heat spreader 30 is mounted on the substrate 1.
1 on the main surface that does not compete with LSI 2
2 may be mounted so as not to oppose the LSI 2, and the heat spreader 30 may be provided so as to contact the upper part of the LSI 12 and a cap may be provided so as to contact the heat spreader 30.
【００５０】[0050]
【発明の効果】以上の説明から明らかなように、本発明
は、パッケージ１に凹部５を設け、この凹部５に複数の
ＬＳＩを上下方向に積み重ねて収容し搭載しているた
め、ＬＳＩの実装密度をより向上させることができると
いう効果がある。また、パッケージ１の外部接続用ピン
と複数のＬＳＩとの距離および複数のＬＳＩ同士の距離
をより短くすることができるため、パッケージ１の内部
の電気的特性を向上させることができるという効果も本
発明にはある。As is apparent from the above description, according to the present invention, the concave portion 5 is provided in the package 1 and a plurality of LSIs are stacked and accommodated in the concave portion 5 in the vertical direction. There is an effect that the density can be further improved. Further, since the distance between the external connection pins of the package 1 and the plurality of LSIs and the distance between the plurality of LSIs can be further reduced, the effect that the electrical characteristics inside the package 1 can be improved can be achieved. There is.
【図１】本発明の第一の実施の形態の断面図である。FIG. 1 is a cross-sectional view of a first embodiment of the present invention.
【図２】本発明の製造方法を示す断面図である。FIG. 2 is a cross-sectional view illustrating the manufacturing method of the present invention.
【図３】本発明の第一の実施の形態の効果を説明するた
めの図である。FIG. 3 is a diagram for explaining effects of the first embodiment of the present invention.
【図４】本発明の第二の実施の形態の断面図である。FIG. 4 is a sectional view of a second embodiment of the present invention.
【図５】従来の半導体装置の実装構造の断面図である。FIG. 5 is a cross-sectional view of a conventional semiconductor device mounting structure.
１ パッケージ ２ ＬＳＩ２ ３ ステッチ３ ４ リード４ ５ 凹部 １１ 基板１１ １２ ＬＳＩ１２ １３ ステッチ１３ １４ リード１４ １５ 配線 １６ 半田ボール１５ ２１ 外部接続用ピン２１ ２２ キャップ２２ ２３ シールリング２３ ３０ ヒートスプレッダ３０ ５１ 底部 ５２、５３ 段部 DESCRIPTION OF SYMBOLS 1 Package 2 LSI2 3 Stitch 3 4 Lead 4 5 Depression 11 Substrate 11 12 LSI 12 13 Stitch 13 14 Lead 14 15 Wiring 16 Solder ball 15 21 External connection pin 21 22 Cap 22 23 Seal ring 23 30 Heat spreader 30 51 Bottom 52, 53 Step
Claims (10)
２の半導体装置とを含むことを特徴とする半導体装置の
実装構造。1. A semiconductor device comprising: a recess provided in a package; a first semiconductor device housed in the recess; and a second semiconductor device housed in the recess above the first semiconductor device. A semiconductor device mounting structure characterized by the above-mentioned.
板と、 この基板に搭載された第２の半導体装置とを含むことを
特徴とする半導体装置の実装構造。A first concave portion provided in the package; a second concave portion provided on a bottom surface of the first concave portion; a first semiconductor device housed in the second concave portion; A mounting structure for a semiconductor device, comprising: a substrate accommodated in a first concave portion and covering the second concave portion; and a second semiconductor device mounted on the substrate.
部からなる階段状部を有する凹部と、 前記複数の段部を用いて上下方向に並べて搭載された複
数の半導体装置とを含むことを特徴とする半導体装置の
実装構造。3. A semiconductor device comprising: a recess formed in a package and having a stepped portion including a plurality of steps in a peripheral portion; and a plurality of semiconductor devices mounted in a vertical direction using the plurality of steps. Characteristic semiconductor device mounting structure.
部とこの第１の段部の上部に設けられた第２の段部とを
有する凹部と、 前記第１の段部に設けられた第１の接続用パッドと、 前記凹部に収容され前記第１の接続用パッドに電気的に
接続された第１の半導体装置と、 前記第２の段部に設けられた第２の接続用パッドと、 前記凹部の前記第１の半導体装置の上部に収容され前記
第２の接続用パッドに電気的に接続された第２の半導体
装置とを含むことを特徴とする半導体装置の実装構造。4. A recess formed in the package and having a first step in a peripheral portion and a second step provided above the first step, and a recess provided in the first step. A first connection pad accommodated in the recess, a first semiconductor device electrically connected to the first connection pad, and a second connection pad provided on the second step portion. A mounting structure for a semiconductor device, comprising: a pad; and a second semiconductor device housed in the recess above the first semiconductor device and electrically connected to the second connection pad.
配線とを含み、 前記第１および第２のパッドは前記内部配線を介して前
記外部接続用ピンに電気的に接続されていることを特徴
とする請求項４記載の半導体装置の実装構造。5. The package includes an external connection pin and an internal wiring, wherein the first and second pads are electrically connected to the external connection pin via the internal wiring. The mounting structure of the semiconductor device according to claim 4.
と、この基板に設けられた配線とを含み、 前記第２の半導体装置は前記配線が前記パッケージの内
部配線と接続されるように前記第２の接続用パッドに搭
載されることを特徴とする請求項４記載の半導体装置の
実装構造。6. A semiconductor device comprising: a substrate on which the second semiconductor device is mounted; and a wiring provided on the substrate, wherein the second semiconductor device is configured such that the wiring is connected to an internal wiring of the package. The mounting structure of a semiconductor device according to claim 4, wherein the mounting structure is mounted on the second connection pad.
多層配線構造を有し、前記凹部は該パッケージの表面に
対して段階的に前記配線基板の積層数を減少させること
により形成されることを特徴とする請求項１、２、３ま
たは４記載の半導体装置の実装構造。7. The package according to claim 1, wherein the package has a multilayer wiring structure including a plurality of wiring layers, and the concave portion is formed by gradually reducing the number of the wiring boards stacked on the surface of the package. The mounting structure of the semiconductor device according to claim 1, 2, 3, or 4.
れ前記凹部を被覆するキャップを含むことを特徴とする
請求項１または３記載の半導体装置の実装構造。8. The semiconductor device mounting structure according to claim 1, further comprising a cap provided on an uppermost portion of said semiconductor device and covering said recess.
の間に設けられた熱伝導部材を含むことを特徴とする請
求項８記載の半導体装置の実装構造。9. The mounting structure for a semiconductor device according to claim 8, further comprising a heat conductive member provided between said second semiconductor device and said cap.
半導体装置であり、前記第２の半導体装置がメモリであ
ることを特徴とする請求項１、２、３または４記載の半
導体装置の実装構造。10. The mounting of the semiconductor device according to claim 1, wherein the first semiconductor device is a logic semiconductor device, and the second semiconductor device is a memory. Construction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8291614A JPH10135406A (en) | 1996-11-01 | 1996-11-01 | Semiconductor device mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8291614A JPH10135406A (en) | 1996-11-01 | 1996-11-01 | Semiconductor device mounting structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10135406A true JPH10135406A (en) | 1998-05-22 |
Family
ID=17771239
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8291614A Pending JPH10135406A (en) | 1996-11-01 | 1996-11-01 | Semiconductor device mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10135406A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000035015A1 (en) * | 1998-12-09 | 2000-06-15 | Mitsubishi Denki Kabushiki Kaisha | Rf circuit module |
| JP2003502852A (en) * | 1999-06-17 | 2003-01-21 | テレフオンアクチーボラゲツト エル エム エリクソン（パブル） | Configuration for mounting chips on multilayer printed circuit boards |
| CN102938398A (en) * | 2011-08-16 | 2013-02-20 | 北京天中磊智能科技有限公司 | Packaging structure for kernel module of intelligent electricity meter |
| JP2014183126A (en) * | 2013-03-18 | 2014-09-29 | Fujitsu Ltd | High frequency module |
-
1996
- 1996-11-01 JP JP8291614A patent/JPH10135406A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2000035015A1 (en) * | 1998-12-09 | 2000-06-15 | Mitsubishi Denki Kabushiki Kaisha | Rf circuit module |
| JP2003502852A (en) * | 1999-06-17 | 2003-01-21 | テレフオンアクチーボラゲツト エル エム エリクソン（パブル） | Configuration for mounting chips on multilayer printed circuit boards |
| CN102938398A (en) * | 2011-08-16 | 2013-02-20 | 北京天中磊智能科技有限公司 | Packaging structure for kernel module of intelligent electricity meter |
| JP2014183126A (en) * | 2013-03-18 | 2014-09-29 | Fujitsu Ltd | High frequency module |
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