JPH05165428A - Display device - Google Patents

Abstract

PURPOSE:To provide a display device capable of suppressing a loss current when a capacitor is charged/discharged and generating a stable write voltage without depending on the frequency of a write voltage as a display device to display a character and a graphic, etc., by using a plasma display panel. CONSTITUTION:The emitter voltage of a transistor Tr2 is taken out as an auxiliary voltage Valpha, and is accumulated in a first capacitor C10. The auxiliary voltage Valpha, after being changed to a second detection voltage betaVs by resistors R13, R14, is added on a first detection voltage alphaVs proportional to a source voltage Vs. The addition voltage of the first detection voltage alphaVs and the second detection voltage betaVs is compared with a reference voltage Vr by an error amplifier 41, and the voltage, after being changed to a differential voltage gammaVs, is supplied to the base of a transistor Tr1, which keeps the voltage Valpha constant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly to a display device for displaying characters and figures using a plasma display panel.

With the recent demand for smaller and lighter OA equipment, as a display device such as a personal computer or an engineering workstation (EWS) terminal,
Instead of the conventional cathode ray tube (CRT), plasma display panel (PDP), liquid crystal display (LCD),
Flat display devices such as electroluminescence (EL) have come into use.

In such a flat panel display device, a display operation is performed by an X electrode for performing data scanning and a Y electrode for performing writing scanning. The writing voltage for performing the writing operation and the sustain voltage for maintaining the display operation are stable. Need to supply.

[0004]

2. Description of the Related Art FIG.
The circuit diagram of an example of the principal part of the display apparatus proposed by the 291 publication is shown. The drawing shows a drive voltage generating circuit in the display device. The drive voltage generating circuit is the write pulse generating circuit 10.
0 and write pulse control circuit 101.

The write pulse generation circuit 100 receives a power supply voltage Vs which is a sustain pulse for continuing a discharge state as an input signal by utilizing wall charges formed in the light emitting display cell, and receives the Vs as resistors R ₁₀ and R. _The voltage is divided by the resistance division ratio α by ₁₁ to generate the first detection voltage of αVs, while the resistances R ₁₂ , R ₁₃ and R ₁₄ are divided by the resistance division ratio β to be β.
A second detection voltage such as Vs is generated and supplied to the write pulse control circuit 101.

The resistor R ₁₂ is connected through the current source A ₁ to the resistors R ₁₃ ,
It is connected to the source of R ₁₅ , the capacitor C ₁₀ , and the transistor Q ₁₁ . The other end of the resistor R ₁₅ is connected to the drain of the transistor Q _{10, and} the drain of the transistor Q ₁₁ is connected to the drain of the transistor Q ₁₂ via the resistor R ₁₆ . These transistors Q ₁₁ and Q ₁₂ are turned off when one is turned on by the switching signal Wp. The drain of the transistor Q ₁₂ is connected to the cathode of the diode D ₁ via the capacitor C ₁₁ .

During the sustain operation, Q ₁₁ is off and Q ₁₂ is on, and the diode D ₁ is provided across the capacitor C _11.
The voltage Vx is charged from the Vs power supply via the. At this time,
Vα generated by the voltage division of the resistors R ₁₂ , R ₁₃ and R ₁₄ is charged in the capacitor C ₁₀ , but V due to the resistors R ₁₀ and R ₁₁ is charged.
The gate input of Q ₁₀ is controlled so that the sum of the detected value αVs of s and the detected value βVs of Vα by the resistors R ₁₃ and R ₁₄ becomes the same as the reference voltage Vref.

The reference voltage Vref is Vw (V
Input the voltage of αVs + βVs for the value of (s + Vα)
It Here, when αVs + βVs is smaller than Vref,
The comparator 104 outputs the H level and Q_TenIs off
Vα≈Vs. Then αVs + βVs is Vref
Therefore, the comparator 104 outputs an L level, and Q
_TenTurns on and the resistance R₁₂~ R₁₅And Q_TenON resistance of
(R_DS) By R ₁₂When

[0009]

[Equation 1]

The value divided into the ratio of is charged to Vα.

As a result, αVs + βVs becomes smaller than Vref again, and Q ₁₀ is turned off. This operation is repeated, and as a result, αVs + βVs operates as if the value becomes equal to Vref.

When performing the write operation, the transistor Q
₁₁ is on, Q ₁₂ is off, and VY has a terminal voltage Vα of C _10.
And the terminal voltage Vx of C ₁₁ are added, Vw (Vs + Vα)
Is output.

[0013]

However, in the device proposed by the present applicant, when the transistor Q ₁₀ is turned on, the voltage Vs is passed through the resistors R ₁₂ and R ₁₅ together with the discharge current from the capacitor C _10. current to power also flows to the drain of the transistor Q _10, becomes the loss current in the transistor Q _10, the power loss is large (for example, several W
About 10W).

Further, although the auxiliary voltage Vα for generating the write voltage is generated from the voltage Vs by resistance division by the resistors R _{12 to} R ₁₄ , the current flowing into the transistor Q ₁₀ when the transistor Q ₁₀ is turned on is generated. If the voltage dividing resistance ratio is increased in order to suppress it, the time for charging the capacitor C ₁₀ becomes longer, so that there is a problem that the size of the writing voltage Vw changes depending on the frequency of the writing scan.

The present invention has been made in view of the above points, and a display device that solves the above problems by adjusting the auxiliary voltage for generating the write voltage by a feedback system without using a voltage dividing resistor. The purpose is to provide.

[0016]

FIG. 1 is a block diagram showing the principle of the present invention. As shown in the figure, the display device of the present invention has a plurality of display cells 16 arranged in a matrix.
Commonly arranged Y for each display cell arranged in the horizontal direction
Between the side electrode group and the X-side electrode group commonly arranged for each display cell arranged in the vertical direction, the display unit 11 having the dielectric layer and the discharge space interposed, and the X-side electrode group are provided. The X-side driver 12 for driving, the Y-side driver 13 for driving the Y-side electrode group, and the power supply voltage Vs applied as the X-side driving voltage to the X-side driver 12 generate the write voltage Vw at a predetermined timing to generate the write voltage Vw. A write voltage generator 14 applied as a Y side drive voltage to the Y driver 13, a first detection voltage αVs obtained from the power supply voltage Vs, and a first voltage proportional to the write voltage extracted from the write voltage generator 14. And a write voltage control device 15 for generating a difference voltage γVs between the reference voltage Vr and the sum voltage of the detected voltage βVs of 2 and supplying it to the write voltage generator 14 and controlling the write voltage Vw to be constant. In Display device, writing voltage generator 14, the auxiliary voltage V is inversely proportional to the difference voltage γVs
The auxiliary voltage generating circuit for generating α, the first capacitor charged with the auxiliary voltage, the second capacitor C ₁₁ charged with the power supply voltage Vs, and the sum voltage of the first and second capacitors are The write voltage output circuit generates and outputs the write voltage Vw.

[0017]

In the present invention, the difference voltage γVs is set to the reference voltage V
Since the auxiliary voltage Vα is generated so as to match r,
Sum voltage (αVs + βV) of the first and second detection voltages
s) can be controlled to be constant, and from this, the write voltage Vw corresponding to the sum of the power supply voltage Vs proportional to Vs of the first detection voltage and the auxiliary voltage Vα proportional to the second detection voltage βVs. Can be kept constant.

Further, in the present invention, the first capacitor is charged by the emitter voltage of the second transistor connected to the collector side of the first transistor to which the differential voltage γVs is applied to the base, and the first capacitor is charged. Since the terminal voltage of is generated as the auxiliary voltage Vα, the current loss for charging and discharging the first capacitor can be suppressed. Further, the second transistor can be switched at a frequency sufficiently higher than the frequency of the write voltage.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In one embodiment of the display device according to the present invention, the display section 11 is a memory type plasma display panel having a structure as shown in FIG. In the figure, a plurality of X-side electrodes 22 are formed in parallel on the surface of a front glass substrate 21, and a dielectric layer 23 is laminated thereon. A plurality of Y-side electrodes 25 are formed in parallel on the surface of the back glass substrate 24, and a dielectric layer 26 is formed thereon.
The protective layer 2 is formed on each surface of the dielectric layers 23 and 26.
7, 28 are formed.

The front glass substrate 21 and the back glass substrate 24 are closely spaced by a spacer 29 so that the X-side electrode 22 and the Y-side electrode 25 are orthogonal to each other in the longitudinal direction, and a discharge space 30 is formed. However, the periphery thereof is sealed by a seal glass 31, and a predetermined structure is filled in the discharge space 30 with a known gas. X above
The intersection of the side electrode 22 and the Y-side electrode 25 is the display cell 16
Therefore, a plurality of display cells 16 are formed in a matrix.

As shown in FIG. 3A, the sustain voltage (sustain voltage) Vs, the write voltage Vw, and the erase voltage V _E are applied in time series to the selected Y-side electrode of the Y-side electrodes 25. Only the sustain voltage Vs is applied to the unselected Y-side electrode. On the other hand, the sustain voltage Vs is applied to the selected X-side electrode of the X-side electrodes 22 immediately after the write voltage Vw is applied to the selected Y-side electrode, as shown in FIG. At the timing when the erase voltage V _E is applied to the formed Y-side electrode, a cancel voltage Vc for canceling the erase voltage V _E is applied. Only the sustain voltage Vs of FIG. 3B is applied to the non-selected X-side electrode.

As a result, the voltage between the Y and X electrodes of the non-lighted display cells on the selected line becomes the erase voltage V as shown in FIG. 3C.
_E is applied, and the voltage between the Y and X electrodes of the illuminated display cell on the selected line is such that the erase voltage V _E has been canceled, as shown in FIG. In addition, the X electrode of the non-selected line,
Since only the sustain voltage Vs is applied to the Y electrode as described above, the voltage between the Y and X electrodes is as shown in FIG. However, even on a non-selected line, the cancel voltage Vc is applied to the X-side electrode of the column to which the cancel voltage Vc is applied, as shown in FIG.

As a result, in the lighted display cell, the write voltage Vw causes a discharge current to flow between the Y and X electrodes to emit light, and the discharge current causes wall charges to be formed on the back surfaces of the dielectric layers 23 and 26, and then the sustain voltage is applied. Each time Vs is applied, discharge using wall charges is performed and light is emitted. on the other hand,
Unlit display cell select lines for writing voltage Vw is applied between the Y-X electrode, although the wall charges are formed on the back surface of the dielectric layer 23 and 26, the wall charges by the application of the erase voltage V _E Is erased, so that even if the sustain voltage Vs is applied thereafter, the discharge is not performed and the LED does not light.

In this embodiment, the write voltage generator 14 and the write voltage controller 15 of a display device having such a plasma display panel in the display section 11 have a circuit configuration as shown in FIG. That is, FIG. 4 shows a circuit diagram of an embodiment of the main part of the device of the present invention, and the same components as those in FIGS. 1 and 5 are designated by the same reference numerals.

In FIG. 4, the power supply voltage Vs has the same value as the sustain voltage, erase voltage and cancel voltage Vc.
The write voltage generator 14 includes a first NPN transistor Tr ₁ that controls a collector current according to a base voltage,
A collector load resistor R ₁ for supplying a current to the collector of the transistor Tr ₁ to change its own voltage drop, and a resistor R
_A second NPN transistor T in which the base voltage changes due to the voltage drop of _{1 and} the emitter voltage changes accordingly.
r ₂ and the first capacitor C ₁₀ whose emitter of the transistor Tr ₂ is connected to the non-grounded terminal, and to supply a current to the collector of the transistor Tr ₂ when writing scan is performed and also to limit the current. a resistor R _2, and an emitter resistor R ₃ of the transistor Tr _1.

Further, similar to the conventional write pulse generating circuit 100 shown in FIG. 5, the write voltage generating device 14 has a capacitor C _{10 connected} in parallel with a series circuit of voltage dividing resistors R ₁₃ and R _14. , A P-channel field effect transistor Q ₁₁ and an N-channel field effect transistor Q ₁₂ have their drains connected to each other via a resistor R _16, and the drain of the transistor Q ₁₂ uses a second capacitor C ₁₁ to prevent backflow. It is connected to the cathode of the diode D ₁ .

A diode D ₂ and a transistor Q ₁₁ connected from the emitter to the collector of the transistor Tr _2.
The diode D ₃ connected between the gate and the source of the transistor Q _{4 and the} diode D ₄ connected between the gate and the source of the transistor Q ₁₂ are for transistor protection. A capacitor C ₁₂ is connected between the gates of the transistors Q ₁₁ and Q ₁₂ , and a resistor R ₁₈ is connected between the gate and source of the transistor Q ₁₁ .

[0028] In this in the writing voltage generating device 14 from the base voltage of the transistor Tr ₂ voltage Vα minus the base-emitter voltage V _BE of the transistor Tr ₂ (for example, about 0.7 V) of the transistor Tr ₂ as an auxiliary voltage Emitter It is taken out and applied to the capacitor C ₁₀ . Therefore, the above voltage Vα is approximately equal to the power supply voltage Vs from the resistance R ₁
It is equal to the base voltage of the transistor Tr ₂ after subtracting the voltage drop due to.

On the other hand, the write voltage controller 15 includes resistors R ₁₀ and R for stepping down the power supply voltage Vs to the first detection voltage αVs.
₁₁ , the resistors R ₂₁ and R ₂₂ , the error amplifier 41, the sum of the second detection voltage βVs obtained by dividing the voltage Vα by the resistors R ₁₃ and R ₁₄ and the first detection voltage αV _S. Of the DC voltage source 42 that generates a constant reference voltage Vr equal to the value when the write voltage Vw is correct, and the output voltage of the error amplifier 41 does not respond immediately when the input voltage suddenly changes, and slow AC feedback is performed. It is composed of a resistor R ₂₄ for application and a capacitor C ₂₁ .

Next, the operation of this embodiment will be described. The switching signal Wp is at a high level (for example, 8V) during the generation of the sustain voltage Vs, and is at a low level (for example, 0V) during the write voltage generation. When the switching signal Wp is at high level, the capacitor C ₁₁ is charged with the voltage Vs as described with reference to FIG. 5, while the capacitor C ₁₀ is charged with the emitter voltage Vα of the transistor Tr _2.
Are charged, and the terminal voltage of the capacitor C ₁₀ is set to Vα.

The switching signal Wp is a period of low level transistor Q ₁₂ is one that is turned off, the transistor Q ₁₁ is turned on the gate voltage of the transistor Q ₁₁ via the coupling capacitor C ₁₂ is set to the low level. Therefore, the source of charges the transistor Q ₁₁ of the capacitor C _10, is discharged into the capacitor C ₁₁ through the drain and the resistor R _16, from the connection point between the cathode of the capacitor C ₁₁ and the diode D _1, the capacitor C ₁₀ (Vα + Vs), which is the sum of the terminal voltages of C ₁₁ and C ₁₁ , is output to the Y-side driver as the write voltage Vw.

On the other hand, the terminal voltage Vα of the capacitor C ₁₀ is stepped down by the resistors R ₁₃ and R ₁₄ to obtain the second detection voltage βVs.
After that, it is added and combined with the first detection voltage αVs input via the resistor R ₂₁ via the resistor R ₂₂ . Therefore, this added synthetic voltage (αVs + βVs) is
The voltage is proportional to α + Vs) and is applied to the non-inverting input terminal of the error amplifier 41.

The error amplifier 41 uses the above voltage (αVs + β
Vs) and the reference voltage Vr are compared in level, and the difference voltage between them is compared.
Generates and outputs γVs. The difference voltage γVs is the write voltage Vw
The voltage (αVs + βVs) corresponding to indicates the normal voltage value.
Square when larger than the reference voltage Vr which is equal to
Toward the transistor Tr. ₁
Increase the base voltage of.

Then, the emitter voltage of the transistor Tr ₁ also increases according to the base-emitter voltage V _BE (about 0.7 V), the conduction state of the transistor Tr ₁ increases, the collector current increases, and the voltage of the resistor R ₁ increases. Greater descent. Therefore, the base voltage of the transistor Tr ₂ drops, and the emitter voltage Vα of Tr ₂ also drops. For this reason, the terminal voltage of the capacitor C ₁₀ drops, and the second detection voltage βVs obtained by being divided by the resistors R ₁₃ and R ₁₄ is obtained.
Is lower, the voltage (αVs + βVs) is the reference voltage V
r or slightly lower.

As a result, the output differential voltage γ of the error amplifier 41
When Vs decreases, turn reduces the collector current of the transistor Tr ₁ is due to a decrease in the base voltage of the transistor Tr _1, so also decreases the voltage drop due to the resistance R _1, the base voltage of the transistor Tr ₂ is increased, the transistor Tr ₂ The emitter voltage (auxiliary voltage) Vα of the device rises. As a result, the second detection voltage βVs rises, so that the voltage (αVs + βVs) rises this time, reaching the reference voltage Vr or slightly higher. After that, by repeating the above operation alternately, the value (Vs + Vα) of the write voltage Vw is controlled to be constant even if the power supply voltage Vs changes.

In this embodiment, since the emitter voltage Vα of the transistor Tr ₂ is controlled to be constant as described above, the transistor Q ₁₁ is turned on and the capacitor C ₁₁ is turned on.
Unnecessary current loss when ₁₀ is discharged can be suppressed. Moreover, in the present embodiment, the variation of the write voltage Vw depending on the frequency depends only on the switching frequency of the transistor Tr ₂ , which is sufficiently faster than the frequency of the write voltage, and therefore does not depend on the frequency of the write voltage Vw. A stable write voltage Vw can be supplied to the Y side driver.

The present invention is not limited to the above embodiment, and field effect transistors may be used instead of the transistors Tr ₁ and Tr ₂ , for example.

[0038]

As described above, according to the present invention, since the write voltage Vw can be kept constant regardless of the fluctuation of the power supply voltage Vs, the emission brightness of the display cell can be kept constant. The write voltage Vs is added to the power supply voltage Vs.
Since the current loss at the time of charging / discharging the first capacitor for generating the auxiliary voltage Vα used for w can be suppressed, the power loss can be suppressed as compared with the conventional one, and further, it does not depend on the frequency of the write voltage. It has a feature that a stable write voltage can be generated and that it contributes to the improvement of display performance.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a structural diagram of an example of a display unit of the device of the present invention.

FIG. 3 is an explanatory diagram of drive waveforms in the device of the present invention.

FIG. 4 is a circuit diagram of an embodiment of a main part of the present invention.

FIG. 5 is a circuit diagram of an example of a main part of a display device previously proposed by the applicant.

[Explanation of symbols]

11 Display Unit 12 X-Side Driver 13 Y-Side Driver 14 Write Voltage Generator 15 Write Voltage Controller 16 Display Cell 22 X-Side Electrode 23, 26 Dielectric Layer 25 Y-Side Electrode 30 Discharge Space 41 Error Amplifier 42 Reference Voltage Source R ₁₁ , R ₁₂ First detection voltage generating voltage dividing resistor R ₁₃ , R ₁₄ Second detection voltage generating voltage dividing resistor R ₁ , R ₂ Collector load resistance Tr ₁ First NPN transistor Tr ₂ Second NPN transistor Q ₁₁ P-channel field effect transistor Q ₁₂ N-channel field effect transistor C ₁₀ 1st capacitor C ₁₁ 2nd capacitor

Claims (3)

[Claims] 1. A Y-side electrode group commonly arranged for each display cell arranged in a horizontal direction among a plurality of display cells (16) arranged in a matrix and a display arranged in a vertical direction. Between the X-side electrode group commonly arranged for each cell,
A display unit (11) having a dielectric layer and a discharge space interposed therebetween; an X-side driver (12) for driving the X-side electrode group; a Y-side driver (13) for driving the Y-side electrode group; A write voltage generated from a power supply voltage (Vs) applied to the X side driver (12) as an X side drive voltage at a predetermined timing and applied to the Y side driver (13) as a Y side drive voltage. The generator (14) and a first detection voltage (αV) obtained from the power supply voltage (Vs).
s) and a second detection voltage (βV) proportional to the write voltage taken out from the write voltage generator (14).
s) and the reference voltage (Vr) are compared with each other to generate a voltage (γVs) so that the two coincide with each other, and the voltage (γVs) is supplied to the write voltage generator (14) to write the write voltage (Vw). A display device comprising a write voltage control device (15) for controlling the write voltage to be constant, wherein the write voltage generation device (14) generates an auxiliary voltage (Vα) inversely proportional to the voltage (γVs). ₁ , Tr ₂ , R ₁ ,
R ₂ ), a first capacitor (C ₁₀ ) charged with the auxiliary voltage, a second capacitor (C ₁₁ ) charged with the power supply voltage (Vs), and the first and second capacitors A display device comprising: a write voltage output circuit (Q ₁₁ , Q ₁₂ , D ₁ , R ₁₆ ) for generating and outputting a sum voltage of (C ₁₀ , C ₁₁ ) as the write voltage (Vw). 2. The auxiliary voltage generating circuit (Tr₁, T
r₂, R₁, R₂) Means that the difference voltage is applied to the base.
First transistor (Tr₁) And the first transition
Star (Tr₁) Collector load resistance (R₁) And the base
Is the first transistor (Tr₁) Connected to the collector
And the emitter is the first capacitor (C _Ten) Ungrounded
The second transistor (Tr₂)When,
The second transistor (Tr₂) Collector load resistance
(R₂) And the second transistor (Tr₂)
To extract the auxiliary voltage (Vα) from the emitter of
The display device according to claim 1, wherein the display device is a display device. 3. The second detection voltage (βVs) is the
Second transistor (Tr₂) Taken from the emitter
The auxiliary voltage (Vα)₁₃, R ₁₄)
3. The resistance is divided and generated.
Display device.