JPH05164819A - Pass fall deciding device for integrated circuit - Google Patents

Abstract

PURPOSE:To make it possible to verify functions of an integrated circuit even in a simple pass fail deciding device or even for integrated circuits forced to test under mixed conditions of passes and fails by enabling tests even when an expected value of a test is either pass or fail. CONSTITUTION:In a coincidence circuit 12, response outputs O from a tested integrated circuit IC are compared successively with a predefined expected value E of a response output, and the number of coincidence outputs A1 from the circuit 12 is counted in a counter circuit 13, and when the count in the circuit 12 is finished, counted number P of passes is compared with a predefined expected value PE of passes in a count comparing circuit 14. Where, when the counted value P and the expected value PE is coincident with each other, the count comparing circuit 14 outputs a count comparing output C1. Then a deciding resistor 15 decides that the tested integrated circuit IC is non- defective, and outputs a synthetic decision output Tj.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention compares the response output of an integrated circuit under test with respect to an input signal and its expected value to check the operation of the integrated circuit under test (pass / fail). It relates to a determination device.

[0002]

2. Description of the Related Art Generally, when determining the quality of an integrated circuit, the response output of an integrated circuit under test to an input signal is compared with its expected value to check the pass / fail of the operation of the integrated circuit under test. A simple type quality determination device is widely used. Here, a configuration of a conventional simple type quality determination device is shown in FIG.

This simple pass / fail judgment apparatus judges whether the integrated circuit is good or bad by hardware, and as shown in FIG.
In accordance with the judgment timing pulse T, the response output O of the integrated circuit under test is compared with its expected value E to detect a mismatch between the two, and a comprehensive judgment is made based on the judgment output J of the mismatch detection circuit 1. The judgment register 2 outputs the output TJ. Then, the mismatch detection circuit 1 determines whether each test passes or fails. When the mismatch detection circuit 1 determines that there is at least one failure, the determination register 2 determines that the product is defective as a comprehensive determination. ..

[0004]

However, in the above-mentioned simple type pass / fail judgment apparatus, the condition that all pass is set as the test condition, and if even one fails, it is judged as the defective product as the comprehensive judgment. Therefore, integrated circuits that must be tested by mixing pass and fail,
For example, for a memory integrated circuit with an enable function, it is difficult to confirm the disable, and it is not possible to confirm all the functions of the integrated circuit. Therefore, for an integrated circuit that must be tested with a mixture of pass and fail, it is inevitable to use a higher quality judgment device that is superior in performance and more expensive than the simple quality judgment device. It had been.

In view of the above, the present invention provides a simple pass / fail judgment device for an integrated circuit, which is capable of performing all the functional confirmation of the integrated circuit even for the integrated circuit in which a test must be performed by mixing a pass and a fail. For the purpose of provision.

[0006]

According to a first aspect of the present invention, when a plurality of input signals are sequentially applied to an integrated circuit under test, a response output of the integrated circuit is determined by a plurality of expected values which are predetermined. Comparing means for sequentially comparing, comparing result outputting means for outputting a signal when the comparing result of the comparing means is either coincident or non-coincident, counting means for counting the number of signals outputted from the comparing result outputting means, and a plurality of When the response output to the input signal of is completely compared with the expected value, the determining means for determining whether the integrated circuit under test is a good product or a defective product is determined based on whether the count value of the counting means is a predetermined value or not. It includes.

According to another aspect of the present invention, there is provided a means for comparing, when a plurality of input signals are sequentially applied to an integrated circuit under test, a response output of the integrated circuit is sequentially compared with a predetermined plurality of expected values. A first comparison result output means for outputting a signal when the comparison results of No. 2 and a second comparison result output means for outputting a signal when the comparison results of the comparison means do not match,
First counting means for counting the number of signals output from the first comparison result output means, second counting means for counting the number of signals output from the second comparison result output means, and the response to the plurality of input signals When the output is completely compared with the expected value, if the count value of the first counting means is the predetermined first value and the count value of the second counting means is the predetermined second value, The test integrated circuit includes a determination means for determining that the test integrated circuit is a non-defective product.

[0008]

In the problem solving means according to claim 1, when a plurality of input signals are sequentially applied to the integrated circuit under test,
The response output of the integrated circuit is sequentially compared with a plurality of expected values determined by the comparison means. The comparison result output means outputs a signal when the comparison result of the comparison means matches or does not match, and the counting means counts the number of signals output from the comparison result output means. Then, when the response outputs for a plurality of input signals are all compared with the expected value, the determining means determines whether the integrated circuit under test is a good product or a defective product based on whether the count value of the counting means is a predetermined value. To judge.

As described above, when the number of passes or fails in a series of tests for one integrated circuit under test is counted and the response outputs for a plurality of input signals are all compared with the expected values of the passes or fails. Since the quality of the operation of the integrated circuit is determined based on whether or not the count value is a predetermined value, it is possible to test whether the expected value of one test is pass or fail. Therefore, even with the simple pass / fail judgment device, it is possible to confirm the function of the integrated circuit even for an integrated circuit in which a test must be performed with a mixture of pass and fail.

When a plurality of input signals are sequentially applied to the integrated circuit under test, the response output of the integrated circuit is sequentially compared with a plurality of expected values determined by the comparing means. When the comparison result of the comparison means is the same, the first
The comparison result output outputs a signal, and when the comparison result of the comparison means does not match, the second comparison result output means outputs a signal. Then, the first counting unit counts the number of signals output from the first comparison result output unit, and the second counting unit outputs the second signal.
The number of signals output from the comparison result output means is counted.
Then, when the determination means finishes comparing all the response outputs with respect to the plurality of input signals with the expected value, the count value of the first counting means is a predetermined first value, and the count value of the second counting means is If the second value is a predetermined value, it is determined that the integrated circuit under test is a non-defective product.

In this way, the number of passes and the number of failures of a series of tests for one integrated circuit under test are separately counted, and the response outputs for a plurality of input signals are all compared with the expected value. At this time, the pass count value is the first predetermined value, and the fail count value is the second predetermined value.
Since the quality of the operation of the integrated circuit is determined based on whether or not the value of is, it is possible to test whether the expected value of one test is pass or fail. It is possible to confirm the function of the integrated circuit even for the integrated circuit which must be mixed and tested.

Further, when both the pass count value and the pass expectation value and the fail count value and the fail expectation value match, the integrated circuit under test is judged as a non-defective product, so the pass count value and the pass expectation value, or the fail value. If the test is missed or the count is incorrect such that only the count value and the expected fail value match, the product is defective. Therefore, a defective product will not be erroneously determined as a non-defective product, and the quality determination accuracy will be higher.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS.
Based on. The configuration of the simple pass / fail judgment apparatus for an integrated circuit according to this embodiment will be described with reference to the block diagram shown in FIG. The simple pass / fail judgment apparatus of this embodiment is for judging whether the integrated circuit IC is good or bad by comparing the response output of the integrated circuit under test IC with respect to a series of input signals and its expected value. An input circuit 10 that sequentially supplies a plurality of input signals I to the circuit IC, and an expected value E of the response output of the integrated circuit IC under test, a decision strobe S, an expected path value PE, and an expected value that sequentially outputs a comprehensive decision strobe TS. The response output O of the output circuit 11 and the integrated circuit under test IC are sequentially compared with the expected value E of the response output determined in advance at the designated time interval of the determination strobe S to detect a match (path) between them, and both match. At the same time, the coincidence circuit 12 that outputs the coincidence output A1, the counting circuit 13 that counts the coincidence output A1 of the coincidence circuit 12, and the pass count value P and the pass count value P in advance when the counting circuit 13 finishes counting the coincidence output A1. Mel path expected value PE
And a numerical comparison circuit 14 that outputs a numerical comparison output C1 when the two coincide with each other, and based on the numerical comparison output C1 of the numerical comparison circuit 14, judges whether the operation of the integrated circuit under test IC is good or bad, and stores the result. The determination register 15 is provided with a comprehensive determination output TJ at a designated time interval of the strobe TS.

The pass / fail judgment operation of the pass / fail judgment apparatus will be described with reference to the timing charts of FIGS. 3 is a timing chart when the quality determination device determines that the product is good, and FIG. 4 is a timing chart when the quality determination device determines that the product is defective. For convenience,
Table 1 for the OR circuit having the input terminals a and b, the output terminal c and the disable terminal d shown in FIG.
The case where the input signal shown in FIG. Table 1
Is an input signal pattern for the OR circuit and an output pattern when the input signal pattern is given,
In the table, -shows the input / output pattern when the disable terminal d is OFF, and-shows the input / output pattern when the disable terminal d is ON.

[0015]

[Table 1]

First, the integrated circuit I under test is input from the input circuit 10.
When the input signal I is sequentially applied to the input terminals a and b of C, the output terminal c of the integrated circuit under test IC sequentially outputs the response output O. On the other hand, the expected value output circuit 11 sequentially outputs the expected value E, the decision strobe S, the expected path value PE, and the comprehensive decision strobe TS of the response output of the integrated circuit under test IC.

Then, the coincidence circuit 12 sequentially compares the response output O of the integrated circuit under test IC with the expected value E of the response output predetermined at the designated time interval of the decision strobe S, and both coincide (pass). At the same time, the coincidence output A1 is output to the counting circuit 13. Then, the coincidence output A1 is counted by the counting circuit 13, and when the counting circuit 13 finishes counting, the count comparison circuit 14 compares whether or not the pass count value P matches a predetermined pass expected value PE. ..

At this time, as shown in FIG. 3, if the pass count value P and the expected pass value PE match, the count comparison circuit 14 outputs the numerical comparison output C1 to the judgment register 15. Then, the decision register 15 decides and stores the integrated circuit under test IC as a non-defective product based on the numerical comparison output C1, and outputs the comprehensive decision output TJ as High at the designated time interval of the comprehensive decision strobe TS. On the other hand, as shown in FIG. 4, when the pass count value P and the pass expected value PE do not match, the count comparison circuit 14 does not output the numerical comparison output C1 to the determination register 15. Then, the judgment register 15 judges that the integrated circuit under test IC is defective and is stored, and the comprehensive judgment output TJ is output as Low at the designated time interval of the comprehensive judgment strobe TS.

Thus, when the number of a series of test passes for one integrated circuit IC under test is counted,
Since the quality of the operation of the integrated circuit is determined based on whether or not the pass count value P matches a predetermined pass expected value PE, it is possible to test whether the expected value of one test is pass or fail. Therefore, even with the simple pass / fail judgment device, all the function confirmation of the integrated circuit is required even for an integrated circuit that must be tested by mixing pass and fail, for example, a memory integrated circuit with an enable function. It can be carried out.

Although an OR circuit is taken as an example for convenience of explanation, it can be similarly applied to a complicated memory integrated circuit with a disable function by only increasing the number of test steps. Next, a second embodiment of the present invention will be described with reference to FIGS. The configuration of the simple pass / fail judgment apparatus for an integrated circuit according to this embodiment will be described with reference to the block diagram shown in FIG.

The simple pass / fail judgment apparatus of this embodiment comprises an input circuit 10 for sequentially supplying a plurality of input signals I to an integrated circuit under test IC, an expected value E of a response output of the integrated circuit under test IC, and a decision strobe. Expected value output circuit 11 for outputting S, expected path value PE, expected fail value FE, and overall decision strobe TS, and expected response output O of response output O of integrated circuit IC under test at predetermined time intervals of decision strobe S The values (E) are sequentially compared to detect a match (path) between them,
A matching circuit 12 that outputs a matching output A1 when they match, a first counting circuit 13 that counts the matching output A1 of the matching circuit 12, and when the first counting circuit 13 finishes counting the matching output A1, Pass count value P and predetermined pass expected value P
E is compared, and when both match, the first numerical comparison output C
The first numerical comparison circuit 14 that outputs 1 and the response output O of the integrated circuit under test IC are sequentially compared with the expected value E of the response output that is predetermined at the designated time interval of the determination strobe S, and a mismatch (fail) between the two is detected. A non-matching circuit 20 which detects and outputs a non-matching output A2 when the two do not match, and a non-matching circuit 2
When the second counting circuit 21 that counts the mismatch output A2 of 0 and the second counting circuit 21 finish counting the match output A2, the fail count value F and the predetermined fail expected value FE are compared, and both match. A second numerical value comparison circuit 22 which sometimes outputs a second numerical value comparison output C2, and both numerical value comparison circuits 14 and 2
Based on each of the numerical comparison outputs C1 and C2 of 2, the quality of the operation of the integrated circuit IC under test is determined and stored, and the overall determination strobe T
A determination register 15 that outputs a total determination output TJ at a designated time interval of S is provided.

The quality determination operation of the quality determination device will now be described with reference to the timing charts of FIGS. 5 is a timing chart when the quality determination device determines that the product is good, and FIG. 6 is a timing chart when the quality determination device determines that the product is defective. For convenience,
Similar to the first embodiment, the case where the input signals shown in Table 1 are applied to the OR circuit shown in FIG. 2 will be described as an example.

First, the integrated circuit I under test is input from the input circuit 10.
When the input signal I is sequentially applied to the input terminals a and b of C, the output terminal c of the integrated circuit under test IC sequentially outputs the response output O, and at the same time, the expected value output circuit 11 outputs the integrated circuit under test. The expected value E, the decision strobe S, the pass expected value PE, the fail expected value FE, and the comprehensive decision strobe TS of the response output of the IC are sequentially output.

Then, the coincidence circuit 12 sequentially compares the response output O of the integrated circuit under test IC with the expected value E of the response output predetermined at the designated time interval of the decision strobe S, and both of them coincide (pass). Sometimes coincidence output A1 is first
It is output to the counting circuit 13. Then, the coincidence output A1
Are counted by the first counting circuit 13, and the first counting circuit 13
At the end of counting, the first count comparison circuit 14 compares the pass count value P with a predetermined pass expected value PE to see if it matches. At this time, if the pass count value P and the pass expected value PE match as shown in FIG. 6, the first count comparison circuit 1
4 outputs the first numerical comparison output C1 to the judgment register 15. On the other hand, as shown in FIG. 7, the pass count value P and the expected path value P
If E does not match, the first count comparison circuit 14 does not output the second numerical comparison output C1 to the determination register 15.

On the other hand, the non-coincidence circuit 20 sequentially compares the response output O of the integrated circuit under test IC with the expected value E of the response output predetermined at the designated time interval of the determination strobe S, and the two are judged as non-coincidence (fail). Sometimes mismatch output A2
Is output to the second counting circuit 21. Then, the mismatch output A2 is counted by the second counting circuit 21, and when the counting of the second counting circuit 20 is completed, the fail count value F in the second count comparison circuit 22 is a predetermined fail expected value FE.
Is compared with or not. At this time, as shown in FIG. 6, if the fail count value F and the fail expected value FE match, the second count comparison circuit 22 outputs the second numerical comparison output C2.
Is output to the determination register 15. On the other hand, as shown in FIG.
If the fail count value F and the fail expected value FE do not match, the second count comparison circuit 22 does not output the second numerical comparison output C2 to the determination register 15.

Then, as shown in FIG. 6, the judgment register 15
When both numerical value comparison outputs C1 and C2 are input to the judgment register 15, the judgment register 15 judges that the integrated circuit under test IC is a good product based on the both numerical value comparison outputs C1 and C2, and stores it, and the specified time interval of the total judgment strobe TS. Total judgment output TJ at High
Output h. On the other hand, as shown in FIG. 7, when both numerical value comparison outputs C1 and C2 are not input to the determination register 15, the determination register 15 stores the determination that the integrated circuit under test IC is a non-defective product, and stores the total determination strobe TS at the specified time. The comprehensive judgment output TJ is output Low at intervals.

In this way, when the number of failures in the series of tests for one integrated circuit IC under test has been counted, the pass count value P becomes a predetermined pass expected value PE, and the fail count value becomes Since the quality of the operation of the integrated circuit is determined based on whether or not F matches the predetermined fail expected value FE, it is possible to test whether the expected value of one test is pass or fail. Therefore, the same effect as the first embodiment can be obtained.

Further, since the integrated circuit under test IC is judged as a non-defective product only when both the pass count value and the pass expected value and the fail count value and the fail expected value match, the pass count value and the pass expected value, or If the test is missed or the counting is incorrect such that only the fail count value and the fail expected value match, the product is defective. As described above, since the present embodiment has the fail-self function, a defective product is not erroneously determined as a non-defective product, and the pass / fail determination accuracy is better than that of the first embodiment.

The present invention is not limited to the above embodiment, and it goes without saying that many modifications and changes can be made within the scope of the present invention. For example, as shown in FIG. 8, the mismatch circuit 20 sequentially compares the response output O of the integrated circuit under test IC with the expected value E of the predetermined response output to detect a mismatch (fail) between the two, and the mismatch circuit 20 detects The non-coincidence output A2 is counted by the counting circuit 21, and when the counting circuit 21 finishes counting, the count comparison circuit 22 compares the fail count value F with a predetermined fail expected value FE. Even if the judgment register 15 judges whether the operation of the integrated circuit IC under test is good or bad on the basis of the numerical comparison output C2 by outputting C2, or for an integrated circuit which has to carry out a test by mixing pass and fail. All functions of the integrated circuit can be confirmed.

[0030]

As is apparent from the above description, according to claims 1 and 2 of the present invention, it is possible to test whether the expected value of one test is pass or fail. There is an excellent effect that the function of the integrated circuit can be confirmed even for the integrated circuit which must be tested by mixing pass and fail.

Further, in claim 2, when both the pass count value and the pass expectation value and the fail count value and the fail expectation value match, it is determined that the integrated circuit IC under test is a non-defective item. If the test is missed or the count is incorrect such that only the pass expected value or the fail count value matches the fail expected value, the product is defective. for that reason,
A defective product will not be erroneously determined as a non-defective product, and the quality determination accuracy will be higher.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a quality determination device for an integrated circuit according to a first exemplary embodiment of the present invention.

FIG. 2 shows an OR circuit with an enable function.

FIG. 3 is a timing chart when the quality determination device determines that the quality is good.

FIG. 4 is a timing chart when the quality determination device determines a defective product.

FIG. 5 is a block diagram showing a configuration of a quality determination device for an integrated circuit according to a second exemplary embodiment of the present invention.

FIG. 6 is a timing chart when the quality determination device determines that the quality is good.

FIG. 7 is a timing chart when the quality determination device determines that the product is defective.

FIG. 8 is a block diagram showing the configuration of a quality determination device for an integrated circuit according to another embodiment.

FIG. 9 is a block diagram showing a configuration of a conventional quality determination device.

[Explanation of symbols]

 11 Expected value output circuit 12 Matching circuit 20 Mismatching circuit 13,21 Counting circuit 14,22 Counting comparison circuit 15 Judgment register

Claims (2)

[Claims] 1. Comparing means for sequentially comparing a response output of the integrated circuit with a plurality of predetermined expected values when a plurality of input signals are sequentially applied to the integrated circuit under test, and comparison results of the comparing means are coincident or non-coincident. Comparing result output means for outputting a signal when any one of the above, counting means for counting the number of signals output from the comparing result output means, and the response output for a plurality of input signals are all compared with the expected value An integrated circuit pass / fail judgment apparatus, comprising: a judgment unit for judging whether the integrated circuit under test is a non-defective product or a defective product based on whether or not the count value of the counting unit is a predetermined value. 2. Comparing means for sequentially comparing the response output of the integrated circuit with a plurality of predetermined expected values when a plurality of input signals are sequentially applied to the integrated circuit under test, and when the comparison result of the comparing means is coincident. First to output a signal to
Comparison result output means, second comparison result output means for outputting a signal when the comparison results of the comparison means do not match, first counting means for counting the number of signals output from the first comparison result output means, second comparison A second counting means for counting the number of signals output from the result output means, and a first counting value of the first counting means when the response outputs for the plurality of input signals are all compared with the expected value. And the value of the second counting means is a predetermined second value, the integrated circuit under test is judged to be a non-defective product. apparatus.