JPH05160735A - Sigmadelta modulator for oversampling a/d converter - Google Patents

Abstract

PURPOSE:To relax the saturation of an integration device by a quadratic retardation double integration SIGMADELTA modulator and to solve the deterioration in the S/N characteristic at a high input level with respect to the SIGMADELTA modulator for the oversampling A/D converter whose sampling frequency is far higher than a frequency band required actually for the conversion. CONSTITUTION:A quadratic retardation double integration SIGMADELTA modulator is provided with a 1st means 21 whose amplification factor alpha1 is 1.0 or below amplifying a signal from an input terminal and giving a signal to a noninverting input terminal of an adder 14 from which the result of sum is outputted to a 1st integration device 15 (in the order of the input terminal), a 2nd means 22 whose amplification factor beta1 is alpha1 amplifying a feedback signal as the conversion result by a D/A converter 19 from an output signal of the modulator and outputting the result to an inverting input terminal of the adder 14, a 3rd means 23 whose amplification factor alpha1 is 1.0 amplifying the output of the integration device 15 and giving an output to a noninverting input terminal of an adder 16 from which the result of sum is outputted to the 2nd integration device 17, a 4th means 24 whose amplification factor alpha1 is 1.0 or below amplifying a feedback signal and giving an output to an inverting input terminal of the adder 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital converter for converting an analog signal into a digital signal,
More specifically, for the purpose of improving the S / N characteristic, the oversampling A / S which takes a sampling frequency at a frequency much higher than the band actually required by the A / D converter is used.
The present invention relates to a ΣΔ modulator for D converter.

[0002]

2. Description of the Related Art As an A / D converter for performing highly accurate analog / digital conversion, oversampling in which the sampling frequency is extremely higher than the frequency band actually required by the A / D converter for conversion. There is an A / D converter.

The quantization noise generated by the execution of A / D conversion is distributed almost uniformly from DC to the Nyquist frequency, and when the number of quantization bits is equal, the total noise power, that is, regardless of the sampling frequency, that is, The area is constant when the frequency is plotted on the horizontal axis and the noise power is plotted on the vertical axis. Therefore, if the sampling frequency is set to a frequency much higher than the band actually required for conversion by the A / D converter, that is, if oversampling is performed, quantization noise is distributed over a wide frequency range and The component of the quantization noise in the range can be reduced. Then, by using a decimation filter, the frequency is decimated (decimated) to the required signal band to remove the quantization noise other than the signal component, and it is possible to obtain a highly accurate S / N characteristic. Become.

The one using this principle is an oversampling A / D converter, and even a general A / D converter can improve accuracy more than its original performance by using oversampling. It is necessary to increase the speed in accordance with the sampling speed, and it is a highly accurate D / A.
A converter or the like is required, which is not always easy to realize.

Therefore, Δ modulation or ΣΔ is used as a feasible circuit format used for the oversampling A / D converter.
Modulators such as modulation are used. Among these ΣΔ
The modulator has the property of noise shaping that pushes the quantization noise into the high frequency band, that is, reduces the noise component in the required signal band and increases the noise component in the high frequency range, and a decimation filter is provided in the subsequent stage. By using it to remove the quantization noise in the high frequency region, the S / N characteristic can be improved. This noise shaping characteristic depends on the order of the ΣΔ modulator. The higher the order, the steeper the noise shaping can be performed, and the double integral ΣΔ modulator is generally used.

FIG. 9 is a block diagram of a conventional double integral ΣΔ modulator. In this double integral ΣΔ modulator, when the input signal X is input from the input terminal, the first adder 1 takes the difference between the input signal X and the feedback signal Y _s, and the difference is the first integral. It is integrated by the instrument 2. The integration result X
_The feedback signal Y _s is subtracted from _s1 by the second adder 3, and the difference is integrated by the second integrator 4. The result of integration X _s2 is determined as a digital value by the quantizer 5 and output as an output signal Y.

The output signal Y of the double integral ΣΔ modulator of FIG. 9 is obtained by using Z conversion display. When the quantization noise generated in the quantizer 5 is represented by Q and the characteristic of the delay device 6 is represented by Z ^-1 , the output of the first adder 1 is

[0008]

[Equation 1]

The output of the first integrator 2 is

[0010]

[Equation 2]

The output of the second adder 3 is

[0012]

[Equation 3]

The output of the second integrator 4 is

[0014]

[Equation 4]

The output of the quantizer 5 is

[0016]

[Equation 5]

Substituting (1) to (4) into (5)

[0018]

[Equation 6]

To summarize this, the output signal is

[0020]

[Equation 7]

It can be seen that the quantization noise given by the above is multiplied by the noise shaping "(1-Z ^-1 ) ² ". However, in FIG. 9, the feedback signal Y _s is obtained by delaying the output signal Y by the delay device 6 and converting it into an analog signal by the D / A converter 7 so that the first adder 1 and the second adder 3 Is input to the
_{Since s} is sent after the second integrator 4 has completed the integration, the time required for the integration is shortened in order to perform conversion within one sampling period, and an integrator that enables high-speed operation is required. ..

As a modulator for solving this problem, a second-order lag double integral ΣΔ modulator is conventionally used. The block diagram of the configuration is shown in FIG. In the figure, a first integrator 9 in which a delay device is inserted in the signal route,
And the second integrator 11 are used, and the time required for the integration to determine the integration results of the first integrator 9 and the second integrator 11 in the next cycle and the next next cycle, respectively. Can be taken sufficiently. Also, in front of the first integrator 9, the first amplifier 8 having the amplification degree of 0.5 and the second amplifier
In front of the integrator 11 of the second amplifier 1 with an amplification factor of 2.0
0 is provided.

In FIG. 10, the output signal Y is obtained in the same manner as in FIG. In consideration of the amplification degree of the first amplifier 8, the input A to the first integrator 9 is the following expression (8), the output X _s1
Is given by equation (9).

[0024]

[Equation 8]

[0025]

[Equation 9]

The input B to the second integrator 11 is the following (1
The expression (0) and the output X _s2 are given by the expression (11), and the output Y of the quantizer 5 is the same as the expression (5).

[0027]

[Equation 10]

[0028]

[Equation 11]

By substituting equations (8) to (11) into equation (5) and rearranging, the following equation is obtained.

[0030]

[Equation 12]

That is, although the output signal is delayed by two samples in the second-order lag double integral ΣΔ modulator, the same effect as that of the normal double integral ΣΔ modulator is exhibited in noise shaping.

[0032]

However, in order to improve the problem of the double integral ΣΔ modulator of FIG. 9, that is, the need for an integrator capable of high speed operation, FIG.
In the second-order lag double-integral ΣΔ modulator, the value input to the second integrator is 6αB because the second amplifier 10 having the amplification factor of 2.0 is provided in front of the second integrator 11. Therefore, when the signal input level is high, the integrator is saturated and the S / N characteristic is deteriorated.

An object of the present invention is to alleviate the saturation of the integrator in the conventional second-order lag double integral ΣΔ modulator and solve the deterioration of the S / N characteristic at a high input level.

[0034]

FIG. 1 is a block diagram showing the principle of the present invention. The figure shows a first adder 14 for obtaining a difference between an input signal input from an input terminal and a feedback signal, and a delay device in a signal route, and a first adder 14 for integrating a subtraction result of the first adder 14. Integrator 15, a second adder 16 that subtracts a feedback signal from the integration result of the first integrator 15, and a delay device in the signal route, and integrates the subtraction result of the second adder 16. A second integrator 17, a quantizer 18 that quantizes the integration result of the second integrator 17, and outputs the result from an output terminal;
FIG. 2 is a principle block diagram of a ΣΔ modulator that includes a D / A converter 19 that digitally / analog converts the output of the quantizer 18 to create a feedback signal, and that improves deterioration of the S / N characteristic at a high input level. is there.

In FIG. 1, the input terminal and the first adder 14
Between the D / A converter 19 and the first adder 14 having the amplification degree α ₁ of 1.0 or less between
Second amplifying means 22 having an amplifying degree β ₁ equal to ₁ , third amplifying means 23 having an amplifying degree α _{2 of} 1.0 between the first integrator 15 and the second adder 16, and D Between the A / A converter 19 and the second adder 16, an amplification degree β of 1.0 or less
A fourth amplification means 24 having ₂ is provided.

[0036]

In the present invention, the amplification degree α ₁ of the first amplifying means 21 provided in the signal route of the input signal inputted from the input terminal is 1.0 or less, and the third amplifying means 23 is provided.
The amplification degree of is set to 1.0. As a result, for example, as shown in FIG. 10, the saturation of the second integrator is significantly relaxed as compared with the case where the second amplifier 10 provided in front of the second integrator 11 has an amplification degree of 2.0. Is possible.

[0037] For example by setting the amplification degree alpha ₁ of the first amplifying means 21 amplifies the degree beta ₁ together 0.25 of the second amplifying means 22, the amplification degree beta ₂ 0.5 of the fourth amplifying means 24, As will be described later as a simulation result, it becomes possible to relax the saturation of the integrator.

[0038]

2 is a block diagram showing the configuration of an embodiment of a .SIGMA..DELTA. Modulator for an oversampling A / D converter according to the present invention. In the figure, the same parts as those in FIGS. 9 and 10 of the conventional example are given the same numbers. Comparing this figure with the conventional example of FIG.
The first amplifier 8 and the second amplifier 1 in FIG.
Instead of 0, there is a first between the input terminal and the first adder 1.
Second amplifier 32, the first integrator 9 and the second adder 3 between the amplifier 31, the D / A converter 7 and the first adder 1.
And a third amplifier 33 between them and a fourth amplifier 34 between the D / A converter 7 and the second adder 3 are different.

In FIG. 2, the analog signal input from the input terminal is X, the amplification degree of the first amplifier 31 is α ₁ , and the second
The amplification degree of the amplifier 32 is β ₁ = α ₁ , and the third amplifier 33
Is represented by α ₂ , the amplification degree of the fourth amplifier 34 is represented by β ₂ , the quantization error generated by the quantizer 5 is represented by Q, and the delay device is represented by Z ^−1. Ask for Y.

In FIG. 2, the input A to the first integrator 9 is
Is given by the following equation (13), and the output X _s1 is the same as the equation (9).

[0041]

[Equation 13]

The input B to the second integrator 11 is
The output X _s2 is given by the equation (14), and the output Y of the quantizer 5 is the same as the equation (5).

[0043]

[Equation 14]

By substituting the equations (13), (9), (14) and (11) into the equation (5), the following equation is obtained.

[0045]

[Equation 15]

By rearranging this, the following expression (16) is obtained.

[0047]

[Equation 16]

Here, γ = Z ⁻² (α ₂ β ₁ −β ₂ +1) +
Z ⁻¹ (β ₂ −2) +1 If we set α ₂ = 1.0 in equation (16), the output signal Y will be

[0049]

[Equation 17]

Here, γ = Z ⁻² (β ₁ −β ₂ +1) + Z ⁻¹
Second-order lag double integral ΣΔ given by (β ₂ −2) +1 and given by equation (12)
The output signal of the modulator is divided by γ.

In the embodiment of FIG. 2, the first amplifier 31
The amplification degree α _{1 of 1} and the amplification degree β ₁ of the second amplifier 32 are both 1.
By setting the amplification factor of the third amplifier 33 to 1.0 and the amplification factor β ₂ of the fourth amplifier 34 to 1.0 or less, it is possible to prevent a signal exceeding the limit value of the operating voltage from being input to the integrator. Moreover, the saturation of the integrator can be relaxed and the S / N characteristic can be prevented from being deteriorated.

FIG. 3 shows frequency characteristics of the ΣΔ modulator of the present invention. This takes into account the integration error due to the gain of the operational amplifier used in the integrator. Compared with the frequency characteristic of the conventional second-order lag double integration ΣΔ modulator of FIG.
Although there are differences in the characteristics in the high frequency range above Hz, almost the same characteristics are obtained in the frequency range below that.

FIG. 5 shows the S / N characteristics of an oversampling A / D converter using the ΣΔ modulator of the present invention and a decimation filter in the latter stage. Since noise in a high frequency region other than the signal band is removed by a decimation filter provided after the ΣΔ modulator, the same S as in the case of using the conventional second-order lag double integral ΣΔ modulator shown in FIG. / N characteristic is obtained.

Next, the simulation result when the amplification degree of each amplifier is changed will be described with reference to FIGS. FIG. 7 shows the results obtained by changing the input signal level for the S / N value in the basic type and the applied type and the output value of each integrator when the gain of the operational amplifier used in the integrator is 54 dB. Shows. Here, the basic type has the same amplification factor α ₁ = β ₁ of the first and second amplifiers as 0.5 and the amplification factor of the third amplifier in order to have the same characteristics as the conventional second-order lag double integration ΣΔ modulator. Although α ₂ is 2.0, which is different from the description in FIG. 2, and the amplification factor β ₂ of the fourth amplifier is also 2.0, which is different from FIG. 2, and α ₁ = β ₁ is 0.25 and α 2 is the applied type. ₂ to 1.
This is the result when 0 and β ₂ are set to 0.5. In the figure, the S / N value of the basic type is deteriorated at the input level of -3.1 dB compared with the applied type, and the cause is considered to be the influence of the saturation of the integrator. That is, in the simulation, the output of the integrator is clipped so as to indicate saturation, so that when the output of the integrator is large, the output is clipped, and a large error occurs from the original output value, resulting in S / S. It is considered that the N value is deteriorated.

FIG. 8 shows a comparison of simulation results between the application type and the application type when the gain of the operational amplifier is variable. Here, in the applied type, α ₁ = β ₁ = 0.25,
α ₂ = 1.0 and β ₂ = 0.6 are used. According to the figure, it can be seen that the output value of the integrator can be further reduced in the applied type without deterioration of the S / N value as compared with the applied type.

In FIGS. 7 and 8, the case where both the amplification degrees α ₁ = β ₁ of the first amplifier and the second amplifier are set to 0.25 is explained as an application type, but the case of α ₁ = β ₁ = 0.5 We also conducted a simulation for
_Since it is the same as in the case of ₁ = β ₁ = 0.25, the values of α ₁ and β ₁ are both set to 1.0 or less in the embodiment of FIG.

It was also found that when the values of α ₁ and β ₁ are not equal, the S / N characteristic is deteriorated as compared with the case of α ₁ = β ₁ . That is, when α ₁ = β ₁ = 0.25, the S / N is 64.3596 dB at the input level -20 dB, and 44.1897d at the input level -40 dB.
On the other hand, when α ₁ = 0.25 and β ₁ = 0.5, the S / N is 63.5396 dB at -20 dB and 4 at -40 dB when α ₁ = 0.25 and β ₁ = 0.5.
The result was 3.0664 dB. This is considered to be because, in the second-order ΣΔ modulator, the first integrator has a greater influence on the S / N characteristic than the second integrator.

[0058]

As described above in detail, according to the present invention, in the ΣΔ modulator for the oversampling A / D converter, the signal exceeding the limit value of the operating voltage of the integrator is prevented from being input to the integrator. , Also relaxes the saturation of the integrator,
The result of the S / N characteristic in the D converter can be improved, and it largely contributes to the improvement of the characteristic of the A / D converter.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 ΣΔ for oversampling A / D conversion of the present invention
It is a block diagram which shows the structure of the Example of a modulator.

FIG. 3 is a diagram showing frequency characteristics of a ΣΔ modulator of the present invention.

FIG. 4 is a diagram showing frequency characteristics of a conventional second-order delay double integral ΣΔ modulator.

FIG. 5 is a diagram showing a simulation result of S / N characteristics of an oversampling A / D converter using a ΣΔ modulator of the present invention.

FIG. 6 is a diagram showing a simulation result of S / N characteristics of an oversampling A / D converter using a conventional second-order lag double integration ΣΔ modulator.

FIG. 7 is a diagram (No. 1) showing a simulation result when the amplification degree of each amplifier is changed.

FIG. 8 is a diagram (No. 2) showing a simulation result when the amplification degree of each amplifier is changed.

FIG. 9 is a block diagram showing a configuration of a conventional double integral ΣΔ modulator.

FIG. 10 is a block diagram showing a configuration of a conventional second-order delay double integral ΣΔ modulator.

[Explanation of symbols]

 1,14 1st adder 3,16 2nd adder 5,18 Quantizer 7,19 D / A converter 9,15 1st integrator 11,17 2nd integrator 21 1st Amplifying means 22 Second amplifying means 23 Third amplifying means 24 Fourth amplifying means 31 First amplifier 32 Second amplifier 33 Third amplifier 34 Fourth amplifier

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Hiroyuki Ujiie 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (5)

[Claims] 1. An input signal from an input terminal and a feedback signal
A first adder (14) for obtaining a difference, and the first adder
Integrates the output of (14), and has a delay device in the signal route
The first integrator (15), and the first integrator (15)
Second adder (16) for obtaining the difference between the output and the feedback signal
And a signal rule for integrating the output of the second adder (16).
A second integrator (17) having a delay device in the
Quantize the output of the integrator (17) and output the quantization result.
And a quantizer (18) for outputting from the input terminal
The output of (18) is D / A converted to create the feedback signal.
In a ΣΔ modulator including a D / A converter (19), a value of 1.0 or less is provided between the input terminal and the first adder (14).
Amplification degree α₁A first amplifying means (21) having: between the D / A converter (19) and the first adder (14)
To the α₁Gain β equal to₁Second amplifying means having
(22) between the first integrator (15) and the second adder (16)
A gain of 1.0₂Third amplifying means (23) having
Between the D / A converter (19) and the second adder (16)
Amplitude β less than 1.0 ₂A fourth amplifying means (2
Oversampling A / characterized by having 4)
ΣΔ modulator for D converter. 2. The ΣΔ modulator for an oversampling A / D converter according to claim 1, wherein the oversampling A / D converter includes a decimation filter at a stage subsequent to the ΣΔ modulator. 3. The amplification factors α ₁ = β ₁ = 0.25, β ₂ =
2. The .SIGMA..DELTA. Modulator for an oversampling A / D converter according to claim 1, wherein the value is 0.5. 4. The amplification factors α ₁ = β ₁ = 0.25, β ₂ =
The ΣΔ modulator for an oversampling A / D converter according to claim 1, wherein the value is 0.6. 5. The oversampling A / according to claim _1, wherein the amplification factor is α ₁ = β ₁ = 0.5.
ΣΔ modulator for D converter.