JPH05160718A - Fuzzy programmable logic array - Google Patents

Abstract

PURPOSE:To provide a fuzzy programmable logic array(FPLA) in which a logic having MIN/MAX circuits or MAX/MIN circuits or other optional combination is formed on a single substrate. CONSTITUTION:The array is the fuzzy programmable logic array(FPLA) in which a MIN circuit and a MAX circuit are combined optionally. The logic array is formed by rows and columns for input and output lines, a MIN transistor(TR) or a MAX TR is arranged to each crossing point of the row and the column to form the logic array. A fuse is provided between the input/ output terminal of the TR and the row and desired logics are combined by melting the fuses selectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a fuzzy programmable logic array (FPLA), particularly a MIN circuit and an MA.
The present invention relates to an FPLA that can be arbitrarily combined with an X circuit.

[0002]

Fuzzy computers have been developed and put into practical use in order to solve some problems of digital computer systems, and so-called ambiguity, vagueness, uncertainty, which cannot be processed by conventional digital computers, It has become possible to handle imperfections or inaccuracies numerically.

In order to deal with such ambiguity, fuzzy computers are characterized by using a membership function, and the size of such membership is usually small.
It is represented by a numerical value in the region between 0.0 and 1.0 and varies within this range.

As is well known, a fuzzy computer is
Basically, it is composed of a plurality of membership function generating circuits and a fuzzy inference engine that performs a predetermined fuzzy operation between the generated membership functions. When calculating the membership function, the fuzzy truth value is an important element, and this fuzzy truth value is shown as a value (grade) of the membership function, and is a continuous value [0, 1] from 0 to 1. ]I take the. Then, the input voltage processed by the fuzzy computer corresponding to the fuzzy truth value is set to, for example, [0V, 5V].

In the above-mentioned fuzzy calculation, the input voltage corresponding to the fuzzy truth value has a meaning unlike the conventional digital computer. Therefore, in order to perform the fuzzy calculation, the input voltage corresponding to the fuzzy truth value is calculated from a plurality of input voltages. It is extremely important to find the minimum or maximum value, for which MIN or MAX circuits are used.

Each of the MIN circuit and the MAX circuit exists independently, but when actually assembling the fuzzy computer, a common input voltage is switched to the MIN circuit or the MAX circuit by an analog switch. The MAX circuit is preferred.

FIG. 16 shows an example of the conventional controlled MIN-MAX circuit described above.

As is apparent from the figure, the MIN circuit and the MAX circuit in FIG. 16 are 2-input 1-output controlled MIN-MAX circuits constituted by using bipolar transistors, and the input voltages are indicated by V ₁ and V ₂ . And the output voltage is designated V _out .

The MIN circuit comprises a MIN comparison circuit and a MIN compensation circuit.

The MIN comparison circuit includes transistors Q ₁₁ and Q ₁₂
In the comparator circuit, the input voltages V ₁ and V ₂ are supplied to the bases of the respective transistors Q ₁₁ and Q ₁₂ via a switcher described later.

Since a constant current flows through the common emitter in this MIN comparison circuit, when S ₁₁ and S ₁₂ are connected to I ₁ , the lowest input voltage V ₁ or V ₂ is applied. The transistor applied to the base becomes conductive, and the other transistors are cut off.

Accordingly, in this state, a voltage obtained by adding the base-emitter voltage of the transistor Q ₁₁ or Q _{12 to} the lowest input voltage appears in the common emitter as the MIN comparison voltage.

The MIN comparison circuit includes a transistor Q.
₃ is connected, and the MIN comparison voltage is applied to the transistor Q ₃
Of the transistor Q ₃ since the true minimum voltage obtained by removing the base-emitter voltage from the MIN comparison voltage is taken _out to the output V _out by passing it through the base-emitter of the transistor Q ₃
And the current source I ₃ will be called a MIN compensation circuit.

The MIN compensation circuit includes the transistor Q ₃
Is connected to a constant current source I ₃ and the collector is supplied with a power supply voltage + V _cc .

Therefore, as described above, the output V _out is
A voltage obtained by subtracting the base-emitter voltage of the transistor Q ₃ from the MIN comparison voltage appears, and each transistor of the MIN comparison circuit and the transistor Q _{3 of the} MIN compensation circuit.
The voltage compensation is achieved by equalizing the characteristics of.

On the other hand, the MAX circuit includes a MAX comparison circuit and M
It consists of an AX compensation circuit. In FIG. 16, the switch S ₁₁
When S and S ₁₂ are adjacent to 2, this circuit operates as a MAX circuit. MAX comparator circuit consists respectively of the bipolar transistor Q ₂₁ to the input to the base voltage V _1, V ₂ is supplied, Q _22, the transistors Q _21, Q
The emitter of ₂₂ is connected to the common constant current source I ₂ , and the MAX comparison voltage is output from the common emitter. In the MAX comparator circuit, the collector of the transistors Q _21, Q ₂₂ is connected to a power source + V _cc.

Therefore, in the MAX comparison circuit, only the transistor to which the largest input voltage is applied to the base becomes conductive, and the other transistors are cut off. Then, the MAX comparison voltage obtained by subtracting the base-emitter voltage of the transistor from the highest voltage of V ₁ and V ₂ is output from the emitter of the transistor in the conductive state.

[0018] Therefore, also the MAX comparator circuit, MAX compensation circuit consisting of transistor Q ₄ is connected, by connecting a constant current source I ₄ to the emitter of the transistor Q _4, subtracted by MAX circuit from the emitter It is possible to obtain the MAX output voltage V _out with the compensated base-emitter voltage.

In the conventional controlled MIN-MAX circuit, switches S ₁₁ , S ₁₂ , and S ₂₀ are provided for switching between the MIN circuit and the MAX circuit, and each switch is set to "1". The MIN circuit is selected by tilting it to the side, and conversely, the MAX circuit is selected by tilting to the "2" side. It is preferable that each of these switching devices is formed of an analog switch.

Many of the above-mentioned MIN circuits or MAX circuits are often used in an actual fuzzy computer. For this reason, it has been conventionally desired to form them as an array on the same substrate.

In a conventional digital computer, a programmable logic array is widely used in which an arbitrary gate in an AND or gate array is selectively used and a desired logic array can be obtained.

In a fuzzy computer, it has been proposed to form an array similar to the programmable logic array in such a conventional digital computer, and a fuzzy programmable logic array (FP) is used.
LA) is under development.

[0023]

However, in the conventional FPLA, a specific logic such as MAX-
There is a problem that only MIN logic can be formed, and it has been impossible to obtain a MIN-MAX circuit composed of an arbitrary combination within a single logic array.

The present invention has been made in view of the above problems of the prior art, and its object is MIN / MAX or MAX.
Another object of the present invention is to provide an FPLA capable of deploying logic with / MIN or any other combination on a single substrate.

[0025]

In order to achieve the above object, the present invention provides a plurality of rows each including an input / output line having an input port at one end and an output port at the other end; A logic array is formed by a column composed of a plurality of intersecting connecting lines and a MIN transistor or a MAX transistor arranged at the row / column intersection, and a fusible input is provided between the input end of the transistor and the row. An insulating thin film that can be short-circuited by a fuse or a dielectric breakdown is provided, and an output fuse that can be blown or an insulating thin film that can be short-circuited by a dielectric breakdown is provided between the output terminal and the row of each transistor. The fuse is selectively blown or the insulating thin film is selectively short-circuited to form a use area on the logic array, or , To form the used area in the processing stage of the aluminum wiring pattern of an IC manufacturing process, characterized in that it is capable of forming any combination logic MIN circuit and MAX circuit on logic array.

[0026]

Therefore, according to the present invention, the MIN or MAX circuit is allocated to the predetermined column selected in advance, and the MIN or MAX circuit is allocated.
A column or a MAX column is made, and a desired MIN or MAX circuit is selected according to the required logic, and only the input fuse or the output fuse of this selected element is left and the other is blown, or the selected element is selected. The insulating thin film related to the above is short-circuited by dielectric breakdown, thereby using the general-purpose FPLA, and consisting of any combination of MIN
It is possible to freely construct the / MAX circuit. In addition, it is possible to inexpensively produce a large number of MIN / MAX circuits of various combinations by only partially changing the aluminum wiring pattern of the semi-finished FPLA prepared by the IC manufacturer according to the user's request. ..

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of the fuse blowing method of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the FPLA according to the present invention.

[0029] As can be seen, the logic array and a plurality of rows R ₁ to R _N consisting of input and output lines having an output port OUT ₁ to OUT _N to the input port IN ₁ to IN _N and other end to one end , Columns R _{1 to} C _{N which} are composed of connecting lines that intersect the rows R _{1 to} R _N.

A preselected MIN transistor or a MAX transistor is arranged at the row / column intersection, and in FIG. 1, MAX transistors Q _{11 to} Q _1N are arranged in the column C ₁ / C ₂ . column C ₃ / C ₄ to be MAX transistor Q ₂₁ to Q _2N are disposed similarly.

The columns C _N-1 and C _N are
MIN transistors Q _{(N-1) 1 to} Q _{(N-1) N} and Q _{N1 to} Q _NN are arranged at column intersections.

Each MAX transistor has its base connected to the row via an input fuse or an insulating thin film, its collector connected to the first column C _1, and its emitter connected to the second column C _2. It is also connected to the column through an output fuse or an insulating thin film.

This situation will be explained with respect to the MAX transistor Q ₁₁ , whose base is connected to the row R ₁ via the input fuse IF ₁₁ , the collector is connected to the first column C ₁ and the emitter is connected to the second column C _2. , Is connected to the row R ₁ via the output fuse OF _11, and
The X-transistor also has a similar configuration.

On the other hand, the base of the MIN transistor is the input fuse I when the transistor Q _N1 is taken as an example.
F _N1 to low R ₁ and the collector is grounded,
The emitter is connected to the column C _N and also connected to the row R ₁ via the output fuse OF _N1 . The other MIN transistors also have a configuration conforming to this. Figure 1
Then, the collector is grounded, but the lowest potential of the circuit −
_May be connected to V _EE .

Therefore, by appropriately selecting the input fuse IF and the output fuse OF, and blowing a blowing current to the fuses to blow the fuses, the remaining MIN transistors or MAX transistors can form desired MIN circuits and MAX circuits. It is formed to enable arbitrary logic programming. In the present invention, a region used as a MIN or MAX circuit without blowing a fuse is defined as a use region.

Next, an embodiment in which some logics are constructed by using the FPLA of FIG. 1 will be described.

FIG. 2 shows an array structure that implements the logic P = (AorB) and (CorD), with the input IN
Input voltages A, B, C, and D are supplied to _{1 to} IN ₄ , respectively, and the result of this operation is taken out to the output port OUT _N as the output voltage P.

In FIG. 2, only the circuitry left on the logic array as a result of the fuse blowing is shown, with the result that the MAX comparison voltage of A and B is brought to low R ₅ , while the input voltages C and D are changed. The MAX comparison voltage is brought to low R _N-1 .
Both outputs are then multiplied by MIN to obtain M
The IN voltage is taken from the low R _N to the output port OUT _N.

As is apparent from FIG. 2, according to the present embodiment, once set as the use area, the input fuse and the output fuse are at the row / column intersection of the same row and column corresponding to this use area. All are blown, the circuit is cut off, and voltage interference is removed.

FIG. 3 shows a programmed array for implementing the logic P = (AandB) or (CandD), where the MIN comparison voltage of voltages A and B and the voltages C and D.
Is supplied to the MAX circuit from the columns C _N-1 and C _N through the rows R ₅ and R _N-1 , respectively, and the MAX values of both are output from the row R _N to the output port OUT _N. There is.

FIG. 4 shows a programming logic array for implementing P = AorB, where the MAX comparison voltage of the input voltages A, B is low R ₅ to M.
IN transistor Q _{(N-1) 5} , where base-emitter voltage compensation of the transistor is performed and then low R _N
From the output port OUT _N.

FIG. 5 shows an FPLA that implements P = A and B, and the input voltages A and B are selected from the low R ₅ to the MAX transistor Q when the MIN comparison voltage is selected.
_The base-emitter voltage is compensated at ₁₅ , and then taken out from the low R _N to the output port OUT _N.

As is clear from the above description, according to the FPLA of the present invention, it is possible to obtain a desired combination of MIN and MAX logic circuits on a single array, and a general-purpose FPLA can be used. It can be used for various fuzzy inference operations.

FIG. 6 shows an embodiment in which an arbitrary fuzzy logic function is realized by using the FPLA according to the present invention.
An arbitrary membership function circuit is connected to each input port of A, and an arbitrary form of membership function circuit can be obtained by supplying the input voltage x to all the membership function circuits.

In FIG. 6, the membership function circuits are S function circuits S ₁ , S ₂ , S ₃ and Z function circuits Z ₁ , Z.
₂ and each S-function and Z-function has the characteristics shown in FIG.

Therefore, by combining the membership function circuits added to these input ports and the MIN / MAX operation of FPLA, for example, the membership function circuit shown in FIG. 8 can be obtained.

FIG. 9 shows another preferred embodiment fuzzy inference engine using the FPLA according to the present invention. Similar to FIG. 6, suitable membership function circuits S and Z are provided at the input ports of the FPLA. Is added, and the input terminals to these functional circuits are appropriately combined to supply the input voltages x, y, and z, so that the antecedent part of the “if-then rule” can be selected from AND and OR. Even if it is expressed as a combination, it is possible to synthesize a circuit that outputs the degree of conformity of fact input to this.

As is clear from FIG. 9, truncation gates are connected to the outputs P ₁ , P ₂ and P ₃ of the FPLA, and the consequent part membership functions Q ₁ , Q ₂ and S are obtained.
₃ is "head off" each at the output P _1, P _2, P ₃ of FPLA.

FIG. 10 shows a simplified fuzzy controller F
It is a preferred embodiment using PLA. The grade controllable membership function circuit and FPLA combine membership function for each input variation x, y, z and A between each variation in the antecedent part of the fuzzy rule.
Both logics such as ND and OR are executed at the same time. At the terminals P ₁ , P ₂ and P ₃ , the conformance between the input and each rule antecedent appears as a ₁ , a ₂ and a ₃ , respectively.
OP2 performs these additions.

As described above, according to the FPLA of the present invention, any logic can be programmed.
A preferred embodiment for blowing the input and output fuses for this purpose is shown in FIG.

FIG. 11 shows a state in which the fuse blowing circuit is built in the FPLA. That is, FPLA
The switches S _{1 to} S ₄ are connected to the respective rows R _{1 to} R ₄ , and the fusing power source E _E1 is connected to one end of these switches S.

Further, switches S ₆ and S ₇ for switching between the power source + V _cc and the fusing power source E _B1 are connected to the collector side column of the MAX circuit, and the fusing power source E _B1 further has a resistor R.
Connected to each row via.

Further, fusing switches S ₉ and S ₁₀ are connected to the emitter column of each MAX circuit via a resistor R _E ,
The fusing power supply E _E1 and the power supply −V _EE are being switched.

On the other hand, a switch S ₈ is connected to the column of the MIN circuit via a resistor R _E , and the fusing power supply E _E2 and the power supply +
Switching to V _cc is performed, and the collector of the MIN circuit can be switched to the ground terminal and the fusing power supply E _B2 via the switch S ₁₁ .

FIG. 11 shows the state in which the switch S ₆ is turned to the terminal "1" side and the switch S ₃ is turned on, whereby the input fuse IF _B1 is blown.

Similarly, when the output fuse OF _E1 of the MAX circuit is blown, the switch S _{9 is set} to the terminal "1" and the switch S ₁ is turned on.

Further, when the input fuse IF _B2 of the MIN circuit is blown, the switch S ₁₁ may be turned to the terminal "1" and the switch S ₂ may be turned on.

Further, when the output fuse OF _{E4 of the} MIN circuit is blown, the switch S _{8 is set} to the terminal "1" and the switch S ₈ is turned on.
₄ should be turned on.

As described above, in this embodiment, the FPL
Arbitrary logic programming is possible by driving the changeover switch built in A by a dedicated decoder.

Of course, in the present invention, each fusing power source and fusing resistor can be externally attached to the FPLA.

In the present invention, the blowing of the input and output fuses is adopted in order to carry out the desired logic programming. However, even when these fuses are blown by the circuit shown in FIG. It is necessary to ensure that the fusing is performed and that the element is not broken by the fusing power source or the fusing current during and after the fusing.

Hereinafter, the fusing action of the input and output fuses for the MIN transistor and the MAX transistor will be described in detail.

FIG. 12 shows the case where the input fuse of the npn transistor used as the MAX transistor is blown.

First, the terminal 10 connected to the emitter of the transistor Q through a resistor is floated,
In this state, the fusing power supply E _B1 is applied to the input fuse IF via the base collector of the transistor Q.

Therefore, at the time of programming (when the fuse is blown), the blowing current flowing through the input fuse IF must be smaller than the forward direction allowable current of the collector diode of the transistor Q, and of course, the input fuse IF is allowed. The current must be sufficient for fusing.

After the input fuse IF is blown,
When the fusing current flows from the fusing power supply E _B1 to the output fuse OF, the output fuse OF is blown. Therefore, the size of the fusing power supply E _B1 must be equal to or less than the reverse withstand voltage of the emitter junction of the transistor Q.

Further, the input fuse IF must be able to flow a sufficient base current through the transistor Q in the operating state when it is not blown, and its resistance value must be suppressed within an allowable range.

FIG. 13 shows the fusing current of the input fuse IF of the pnp transistor used as the MIN transistor, and the characteristics of each part are set under the same conditions as the npn transistor.

FIG. 14 shows a current path for blowing the output fuse OF of the MAX transistor Q. At this time, the collector of the transistor Q is floating at the terminal 20. Even at the time of this output fuse blowing, since the input fuse IF after the output fuse OF blown should not be blown, blown power E _E1 should not exceed the reverse breakdown voltage of the emitter junction of the transistor Q. When the polarity of E _E1 is reversed, the current flowing through the emitter of Q causes the input fuse I
Be careful of the polarity of E _E1 because F may melt.

Of course, the output fuse O which has not been blown
In the operating state, F must be able to pass a current to the base of the transistor in the next stage.

FIG. 15 shows the output fuse OF blowing current path of the MIN transistor Q, and the conditions of each part are the same as the above-mentioned conditions.

In the figure, and = Λ, or =
It was set to V.

As described above, the logic array of the present invention can perform a desired logic program by arbitrarily blowing the input fuse and the output fuse.

[0074]

As described above, according to the present invention,
Desired MIN or M inside a single logic array
It is possible to program by combining AX circuits, and it is possible to create a circuit having an arbitrary logic from a general-purpose logic array with a simple structure.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a preferred embodiment of an FPLA according to the present invention.

FIG. 2 is an explanatory diagram showing an example of logic programming using the FPLA of FIG.

3 is an explanatory diagram showing an example of logic programming using the FPLA of FIG. 1. FIG.

4 is an explanatory diagram showing an example of logic programming using the FPLA of FIG. 1. FIG.

5 is an explanatory diagram showing an example of logic programming using the FPLA of FIG. 1. FIG.

FIG. 6 is a block circuit diagram when the FPLA of the present invention is used as a membership function circuit.

FIG. 7 is an explanatory diagram of a membership function in FIG.

8 is an explanatory diagram of a membership function in FIG.

FIG. 9 is a block circuit diagram showing an embodiment in which a fuzzy inference engine is constructed using the FPLA according to the present invention.

FIG. 10 is a circuit diagram showing an embodiment of the present invention in which an FPLA is used as a simplified fuzzy controller.

FIG. 11 is a circuit explanatory view showing an embodiment in which a fuse blowing circuit is incorporated in the FPLA according to the present invention.

FIG. 12 is an explanatory diagram showing a fuse blowing path according to the present invention.

FIG. 13 is an explanatory diagram showing a fuse fusing path according to the present invention.

FIG. 14 is an explanatory diagram showing a fuse blowing path according to the present invention.

FIG. 15 is an explanatory diagram showing a fuse blowing path according to the present invention.

FIG. 16: Conventional controlled MIN / MAX
It is explanatory drawing which shows an example of a circuit.

[Explanation of symbols]

 R Low C column IN input port OUT output port Q transistor IF input fuse OF output fuse

Claims (1)

[Claims] 1. A plurality of rows, each of which has an input port at one end and an output port at the other end, includes a plurality of rows, a column including a plurality of connecting lines intersecting the rows, and the row / column intersection. And a MIN transistor or a MAX transistor arranged in a matrix form a logic array, and a fuse that can be blown between the input end of the transistor and the low and between the output end of each transistor and the low,
Alternatively, an insulating thin film capable of being short-circuited by dielectric breakdown is provided, and the fuse is selectively blown, or the insulating thin film is selectively short-circuited to form a use area on the logic array, or the transistor is used. The aluminum wiring pattern that connects between the specific input terminal and the row and between the specific output terminal and the row of the transistor is determined in the IC manufacturing process by a photomask, electron beam exposure, etc., and the use area is formed on the logic array. A fuzzy programmable logic array, which is characterized in that it is possible to form any combination logic of a MIN circuit and a MAX circuit on the logic array.