JPH05160125A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH05160125A
JPH05160125A JP31930691A JP31930691A JPH05160125A JP H05160125 A JPH05160125 A JP H05160125A JP 31930691 A JP31930691 A JP 31930691A JP 31930691 A JP31930691 A JP 31930691A JP H05160125 A JPH05160125 A JP H05160125A
Authority
JP
Japan
Prior art keywords
film
insulating film
density
concentration
bpsg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31930691A
Other languages
Japanese (ja)
Inventor
Yukio Nishiyama
山 幸 男 西
Kyoichi Suguro
黒 恭 一 須
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP31930691A priority Critical patent/JPH05160125A/en
Publication of JPH05160125A publication Critical patent/JPH05160125A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To make the surface of an insulating film as flat as possible by forming the P-containing hot-melt insulating film so that the P density on the surface may be lower than that inside the film and by allowing the insulating film to reflow and then by etching back the insulating film to the specified thickness. CONSTITUTION:A film 6 is formed which is formed of high-density P-containing PSG and which is 300nm in thickness. After that, the film is allowed to reflow at 900 deg.C for 60 minutes in N2 and just then the surface region of a BPSG film, where the P density is relatively low and the B density is relatively high, flows. As a result, a region 5 which has a relatively low P density and relatively high B density is formed thick in a recessed part of the BPSG film 4. Nextly, the reflowed insulating films 6 and 4 are etched using deluted HF or deluted NH4F. Since an etch rate is high when the P density is high and the B density is low, a protruding part is etched more rapidly than the recessed part. Consequently, the insulating film 4 having as flat a surface as possible is obtained.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

【0002】[0002]

【従来の技術及び発明が解決しようとする課題】一般に
半導体装置を製造する場合、MOSトランジスタ等の素
子の形成が終わった後、メタル配線を形成するために素
子上に絶縁膜が被覆される。この絶縁膜としては不純物
がドープされていないSiO、及びPやBがドープさ
れたBPSG(borophosphosilicate glass)やPSG
(phosphosilicate glass)がその材料として用いられる
が、これらの絶縁膜の表面は下部層の急峻な段差形状に
より凹凸が存在する。これらの凹凸は次の製造工程で行
われる微細コンタクト開孔やメタル配線のためのリソグ
ラフィでフォトレジストの厚さの不均一化や、露光時の
解像度の不均一化の原因となり、レジストパターンの精
度が悪くなる。又、絶縁膜の表面に凹凸があることによ
りメタル配線がスムーズに行われないという問題があ
る。
2. Description of the Related Art Generally, when manufacturing a semiconductor device, an insulating film is coated on the element to form a metal wiring after the element such as a MOS transistor is formed. As the insulating film, SiO 2 not doped with impurities, and BPSG (borophosphosilicate glass) or PSG doped with P or B
Although (phosphosilicate glass) is used as its material, the surface of these insulating films has irregularities due to the steep step shape of the lower layer. These irregularities cause uneven thickness of photoresist and uneven resolution during exposure due to lithography for fine contact openings and metal wiring that will be performed in the next manufacturing process, and the accuracy of the resist pattern will be increased. Becomes worse. Further, there is a problem that the metal wiring is not smoothly performed due to the unevenness of the surface of the insulating film.

【0003】そこでメタル配線をスムーズに行わせるた
めの、平坦化技術が必要となる。従来の平坦化技術は、
高濃度にPやBを含有しているPSGやBPSG膜を高
温雰囲気にさらして膜の表面の流動性を増して平坦化を
図る、リフロー技術が用いられている。このリフロー技
術を用いると、下地層の急峻な段差に対して絶縁膜の表
面はある程度平坦になるが、完全に平坦になるわけでは
ない。又平坦度を改善するためにPやBの濃度が更に高
いBPSG絶縁膜を用いることが考えられるが、この場
合、PとBの化合物が表面で析出する問題がある。この
問題を解決するために高濃度にPを含有するPSG絶縁
膜をBPSG絶縁膜の上に被膜してリフローすることが
行われている。ところが、このようにPおよびBの濃度
を更に高くした場合でもリフローすることにより絶縁膜
の表面はある程度平坦になるが、リフロー処理に費やす
時間に限りがあるため完全に平坦にならないという問題
がある。又、絶縁膜の表面を平坦化することは素子の高
集積化、配線を多層化する上で増々必要となってきてい
る。本発明は上記事情を考慮してなされたものであっ
て、絶縁膜の表面を可及的に平坦にすることのできる半
導体装置の製造方法を提供することを目的とする。
Therefore, a flattening technique is required for smooth metal wiring. Conventional flattening technology
A reflow technique is used in which a PSG or BPSG film containing P or B at a high concentration is exposed to a high temperature atmosphere to increase the fluidity of the surface of the film for planarization. When this reflow technique is used, the surface of the insulating film becomes flat to some extent with respect to the steep steps of the underlayer, but it is not completely flat. It is possible to use a BPSG insulating film having a higher concentration of P and B in order to improve the flatness, but in this case, there is a problem that the compound of P and B is deposited on the surface. In order to solve this problem, a PSG insulating film containing P at a high concentration is coated on the BPSG insulating film and reflowed. However, even when the P and B concentrations are further increased, the surface of the insulating film is flattened to some extent by reflowing, but there is a problem that the surface is not flattened because the time spent for the reflowing process is limited. .. Further, it is becoming more and more necessary to flatten the surface of the insulating film in order to achieve high integration of elements and multilayer wiring. The present invention has been made in view of the above circumstances, and an object thereof is to provide a method for manufacturing a semiconductor device in which the surface of an insulating film can be made as flat as possible.

【0004】[0004]

【課題を解決するための手段】本発明による半導体装置
の製造方法は、素子が形成された半導体基板上に、Pを
含む熱流動性の絶縁膜を、表面部でのP濃度が膜内部の
P濃度に比べて低くなるように形成するステップと、前
記絶縁膜をリフローした後、前記絶縁膜が所定の膜厚と
なるまでエッチバックするステップと、を備えているこ
とを特徴とする。
According to a method of manufacturing a semiconductor device according to the present invention, a heat-fluidic insulating film containing P is formed on a semiconductor substrate on which an element is formed, and a P concentration at the surface portion is within the film. The method is characterized by including a step of forming the insulating film to have a lower concentration than the P concentration, and a step of reflowing the insulating film and then etching back until the insulating film has a predetermined film thickness.

【0005】[0005]

【作用】このように構成された本発明の製造方法によれ
ば、素子が形成された半導体基板上にPを含む熱流動性
の絶縁膜が形成される。この絶縁膜の表面部は内部に比
べてP濃度が低く、次のステップにおけるリフローによ
って表面部が流動し、凹部にP濃度の比較的低い部分が
比較的厚く、凸部にはP濃度の比較的低い部分が薄く形
成される。P濃度の低い部分のエッチングレートは高い
部分のそれに比べて遅いため、リフロー後の絶縁膜をエ
ッチングすることによって凸部は早く、凹部は遅くエッ
チングされて可及的に平坦な絶縁膜を得ることができ
る。
According to the manufacturing method of the present invention having such a structure, the heat-fluidic insulating film containing P is formed on the semiconductor substrate on which the element is formed. The surface portion of this insulating film has a lower P concentration than the inside, and the surface portion flows due to the reflow in the next step, the portion having a relatively low P concentration is relatively thick in the concave portion, and the P concentration in the convex portion is compared. The lower part is thinly formed. Since the etching rate of the portion having a low P concentration is slower than that of the portion having a high P concentration, by etching the insulating film after the reflow, the convex portions are swiftly etched and the concave portions are slowly etched to obtain an insulating film as flat as possible. You can

【0006】[0006]

【実施例】本発明による製造方法によって製造される半
導体装置の製造工程を図1に示す。まずシリコン基板1
上に膜厚が800nmのポリシリコン膜2を、例えばホッ
トウォール型CVD法を用いて形成する(図1(a)参
照)。この時のガスソースはSiHで600℃の条件
で成膜する。続いてこのポリシリコン膜2をパターニン
グする。すると急峻な段差が形成される(図1(a)参
照)。その後ホットウォール型CVD法を用いて膜厚が
100nmの例えばSiOからなる絶縁膜3を形成する
(図1(a)参照)。この時のガスソースとしてはカバ
レージが良好なTEOS(テトラエトキシオルソシリケ
ート(Si(OC))を用い700℃程度の
条件で成膜する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a manufacturing process of a semiconductor device manufactured by a manufacturing method according to the present invention. First, silicon substrate 1
A polysilicon film 2 having a film thickness of 800 nm is formed thereon by using, for example, a hot wall type CVD method (see FIG. 1A). At this time, the gas source is SiH 4 and is formed under the condition of 600 ° C. Then, the polysilicon film 2 is patterned. Then, a steep step is formed (see FIG. 1A). After that, an insulating film 3 made of, for example, SiO 2 and having a film thickness of 100 nm is formed by using the hot wall type CVD method (see FIG. 1A). At this time, TEOS (tetraethoxy orthosilicate (Si (OC 2 H 5 ) 4 )), which has good coverage, is used as a gas source, and the film is formed at about 700 ° C.

【0007】次に、反応性気体にTEOS、TMB(ト
リメトキシボロン(B(OCH))、PH、O
を用いるホットウォール型LPCVD法により基板1
の全面にBPSGからなる膜厚が500nmの膜24を形
成する(図1(b)参照)。この時、TEOS、TMB
は液体材料気化制御装置を用いて気化し、流量制御手段
(図示せず)によって直接流量調整を行い、ヒータによ
って加熱された配管により反応炉内に導入する。成膜条
件としては炉内温度を600℃程度、炉内圧力を0.8
torrとし、TEOSを200sccm(20℃、1気圧で2
00cc/min)、TMBを0〜50sccm、Heで希釈した
10%濃度のPHを0〜1000sccm、Oを0〜1
000scm 程度、反応炉内に導入し、例えば図3
(a)、(b)に示すように、成膜中に、PH
、TMBの流量を変化させる。すなわちPH、O
は成膜開始から成膜の途中までその流量を増加させ、
その後減少させて成膜終了直前は成膜開始の流量とほぼ
同じ流量となるようにする。又、TMBは成膜開始から
成膜の途中までその流量を減少させ、その後増加させて
成膜終了直前の流量が成膜開始の流量とほぼ同じ値とな
るようにする。すると、BPSG膜4の底面からその表
面までのBPSG膜中のP及びBの濃度は図2に示すよ
うに変化する。すなわち、BPSG膜4の表面付近での
Pの濃度は膜4の内部のPの濃度に比べて低く、膜4の
表面付近4aでのBの濃度は膜4の内部のBの濃度に比
べて高くなる。なお、BPSG膜4の表面は上記急峻な
段差に応じて凹凸がある。
Next, TEOS, TMB (trimethoxyboron (B (OCH 3 ) 3 )), PH 3 and O are added to the reactive gas.
Substrate 1 by the hot wall type LPCVD method using 2
A film 24 made of BPSG and having a film thickness of 500 nm is formed on the entire surface (see FIG. 1B). At this time, TEOS, TMB
Is vaporized using a liquid material vaporization control device, the flow rate is adjusted directly by a flow rate control means (not shown), and is introduced into the reaction furnace through a pipe heated by a heater. As film forming conditions, the furnace temperature is about 600 ° C. and the furnace pressure is 0.8.
TEOS is 200 sccm (2 ° C at 20 ° C and 1 atm)
00 cc / min), TMB 0 to 50 sccm, 10% PH 3 diluted with He 0 to 1000 sccm, O 2 0 to 1
Approximately 000scm is introduced into the reaction furnace, for example, as shown in FIG.
As shown in (a) and (b), PH 3 ,
The flow rates of O 2 and TMB are changed. That is, PH 3 , O
2 increases the flow rate from the start of film formation to the middle of film formation,
After that, the flow rate is decreased so that the flow rate is almost the same as the flow rate at the start of film formation immediately before the end of film formation. Further, the flow rate of TMB is decreased from the start of film formation to the middle of film formation, and then increased so that the flow rate immediately before the end of film formation becomes substantially the same as the flow rate at the start of film formation. Then, the concentrations of P and B in the BPSG film from the bottom surface to the surface of the BPSG film 4 change as shown in FIG. That is, the P concentration near the surface of the BPSG film 4 is lower than the P concentration inside the film 4, and the B concentration near the surface 4a of the film 4 is higher than the B concentration inside the film 4. Get higher The surface of the BPSG film 4 has irregularities according to the steep steps.

【0008】次に、次工程で行われる熱処理による表面
でのPとBの化合物の析出を防ぐためにTEOS、PH
、Oのガスソースを用いて、高濃度のP、例えば5
×1021atm/cm3 程度のPを含んでいるPSGからなる
膜厚が300nmの膜6を形成する(図1(b)参照)。
その後、N中で900℃、60分間のリフローを行
う。するとBPSG膜4の表面領域、すなわちP濃度が
比較的低く、B濃度が比較的高い領域が流動し、結果的
に、BPSG膜4の凹部にP濃度が比較的低く、B濃度
が比較的高い領域5が厚く形成される(図1(c)参
照)。
Next, in order to prevent the precipitation of P and B compounds on the surface due to the heat treatment performed in the next step, TEOS and PH are added.
3 , using a gas source of O 2 , a high concentration of P, for example, 5
A film 6 made of PSG containing P of about 10 21 atm / cm 3 and having a film thickness of 300 nm is formed (see FIG. 1B).
Then, reflow is performed at 900 ° C. for 60 minutes in N 2 . Then, the surface region of the BPSG film 4, that is, the region having a relatively low P concentration and a relatively high B concentration flows, and as a result, the P concentration is relatively low and the B concentration is relatively high in the concave portion of the BPSG film 4. The region 5 is formed thick (see FIG. 1C).

【0009】次にリフローした絶縁膜6,4を希HF又
は希NHFを用いてエッチングを行う。するとエッチ
ングレートはPが高濃度、Bが低濃度の方が早いため、
凸部分が凹部に比べて早くエッチングされて、図1
(d)に示すような可及的に平坦な表面を有している絶
縁膜4を得ることができる。なお、図4に示すようにB
PSG膜4中のBの濃度を一定とし、表面付近のPの濃
度を、膜4の内部のPの濃度よりも比較的低くなるよう
にしても上述と同様の効果を得ることができる。又、B
PSG膜4の代わりに、BをドープしないでPの濃度が
図5に示すように表面付近で低くなるようなPSG膜を
用いても上述の場合と同様の効果を得ることができる。
なおこの時、リフローする温度を高くする必要がある。
Next, the reflowed insulating films 6 and 4 are etched with diluted HF or diluted NH 4 F. Then, since the higher the P concentration and the lower the B concentration, the faster the etching rate,
As the convex portion is etched earlier than the concave portion,
It is possible to obtain the insulating film 4 having a surface as flat as possible as shown in (d). In addition, as shown in FIG.
Even if the B concentration in the PSG film 4 is kept constant and the P concentration in the vicinity of the surface is made relatively lower than the P concentration inside the film 4, the same effect as described above can be obtained. Also, B
Instead of the PSG film 4, it is possible to obtain the same effect as in the above case by using a PSG film which is not doped with B and whose P concentration becomes low near the surface as shown in FIG.
At this time, it is necessary to raise the reflow temperature.

【0010】[0010]

【発明の効果】以上述べたように本発明によれば、可及
的に平坦な絶縁膜を得ることができる。
As described above, according to the present invention, an insulating film as flat as possible can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明によって製造される半導体装置の製造工
程を示す断面図。
FIG. 1 is a sectional view showing a manufacturing process of a semiconductor device manufactured by the present invention.

【図2】本発明にかかる絶縁膜の深さ方向の濃度分布を
示すグラフ。
FIG. 2 is a graph showing a concentration distribution in the depth direction of an insulating film according to the present invention.

【図3】本発明にかかる絶縁膜の生成に用いられるガス
流量特性を示すグラフ。
FIG. 3 is a graph showing gas flow rate characteristics used for forming an insulating film according to the present invention.

【図4】本発明にかかるBPSG膜の深さ方向の濃度分
布を示すグラフ。
FIG. 4 is a graph showing the concentration distribution in the depth direction of the BPSG film according to the present invention.

【図5】本発明にかかる絶縁膜の深さ方向の濃度分布を
示すグラフ。
FIG. 5 is a graph showing the concentration distribution in the depth direction of the insulating film according to the present invention.

【符号の説明】[Explanation of symbols]

1 シリコン基板 2 ポリシリコン膜 3 SiO膜 4 BPSG膜 5 Bが高濃度でPが低濃度のBPSG膜 6 PSG膜1 Silicon substrate 2 Polysilicon film 3 SiO 2 film 4 BPSG film 5 BPSG film with high B concentration and low P concentration 6 PSG film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】素子が形成された半導体基板上に、リンを
含む熱流動性の絶縁膜を、表面部でのリン濃度が膜内部
のリン濃度に比べて低くなるように形成するステップ
と、 前記絶縁膜をリフローした後、前記絶縁膜が所定の膜厚
となるまでエッチバックするステップと、 を備えていることを特徴とする半導体装置の製造方法。
1. A step of forming a heat-fluidic insulating film containing phosphorus on a semiconductor substrate on which an element is formed so that the phosphorus concentration at the surface portion is lower than the phosphorus concentration inside the film. After the reflow of the insulating film, a step of etching back until the insulating film has a predetermined film thickness is provided, and a method of manufacturing a semiconductor device.
JP31930691A 1991-12-03 1991-12-03 Manufacture of semiconductor device Pending JPH05160125A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31930691A JPH05160125A (en) 1991-12-03 1991-12-03 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31930691A JPH05160125A (en) 1991-12-03 1991-12-03 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH05160125A true JPH05160125A (en) 1993-06-25

Family

ID=18108726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31930691A Pending JPH05160125A (en) 1991-12-03 1991-12-03 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH05160125A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100485186B1 (en) * 1997-12-31 2005-08-24 주식회사 하이닉스반도체 Method of forming flattening film of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100485186B1 (en) * 1997-12-31 2005-08-24 주식회사 하이닉스반도체 Method of forming flattening film of semiconductor device

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