JPH05158655A - Clock crossing-over circuit - Google Patents

Abstract

PURPOSE:To miniaturize a device by enabling contention control over a write phase and a read phase while using a single-port RAM. CONSTITUTION:The clock crossing-over circuit, provided with a series-parallel converting circuit 21 which performs series-parallel conversion from series data to parallel data with a 1st clock, the single-port RAM 22 wherein the parallel data from the serial-parallel converting circuit 21 are written, and a parallel-serial converting circuit 23 which performs parallel-serial conversion from data read out of the single-port RAM 22 to series data with a 2nd clock, is provided with a register 24 which is interposed between the single-port RAM 21 and parallel-serial converting circuit 22 and temporarily stored with the read data from the single-port RAM 21 to the parallel-serial converting circuit 22 and a contention control circuit 25 which delays a read of the single-port RAM 22 and writes the read data in the register 24 when the write timing of the single-port RAM 22 conflicts with the read timing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial data clock transfer circuit for performing clock speed conversion or frequency conversion of serial data. Clock transfer circuits are used in, for example, elastic memories, but when the phase relationship between input serial data and output serial data is not always constant,
Since the write phase and the read phase of the conversion memory may have the same timing, in such a case, it is necessary to adjust the timing to be shifted.

[0002]

2. Description of the Related Art Conventionally, in such a serial data clock transfer circuit, as a conversion memory, a FIFO (Firs) which can arbitrarily take a write phase, a read phase and a read phase is usually used.
t In First Out) type memory or dual port RAM with separate write address and read address is used, which allows normal operation even if the write and read phases of the conversion memory overlap. ..

[0003]

However, these FIs
The FO memory and the dual port RAM have a complicated structure and a large size as compared with the commonly used single port RAM. Therefore, these memories are LS
When it is attempted to be built in the I, there is no cell of an appropriate size or the area becomes larger than that of the single-port RAM. Therefore, it is generally used as an external circuit to the LSI.
It has to be provided separately from the SI, which causes an increase in the size of the clock transfer circuit.

The present invention has been made in view of the above problems, and an object thereof is a single port R
The purpose of this is to reduce the size of the device by enabling competitive control of the write phase and the read phase while using the AM.

[0005]

FIG. 1 is an explanatory view of the principle of the present invention. As shown in FIG. 1 (A), the serial data clock transfer circuit according to the present invention has, as one form, a serial-parallel conversion circuit 21 that serial-parallel converts serial data into parallel data at a first clock, Serial-parallel conversion circuit 21
Port RAM to which parallel data from the
22 and a parallel-serial conversion circuit 23 that parallel-serial converts read data from the single-port RAM 22 into serial data at a second clock,
A register 24 that is inserted between the single-port RAM 21 and the parallel-serial conversion circuit 22 to temporarily store read data from the single-port RAM 21 to the parallel-serial conversion circuit 22.
When the write timing and the read timing of the single port RAM 22 conflict with each other, the single port RAM 2
The contention control circuit 25 controls the writing of the read data into the register 24 by delaying the reading of the data of the second data.

Further, as shown in FIG. 1B, the serial data clock transfer circuit according to the present invention is, as another form, a serial-parallel conversion for serial-parallel converting serial data into parallel data at the first clock. Circuit 31 and serial-parallel conversion circuit 31
Port RAM to which parallel data from the
In the serial data clock transfer circuit, the serial-to-parallel conversion circuit 31 and the single-port RA are provided with a serial-to-serial conversion circuit 32 including a serial-to-serial conversion circuit 33 that parallel-serial converts read data from the single-port RAM 32 into serial data at a second clock.
The register 34 that is inserted between the M322 and the serial / parallel conversion circuit 31 to temporarily store the write data to the single port RAM 32 and the register 34 to the single port RAM 32 when the write timing and the read timing of the single port RAM 32 conflict with each other. The contention control circuit 35 controls the writing so as to be delayed.

[0007]

In the former embodiment of the serial data clock transfer circuit, when the write timing and the read timing with respect to the single-port RAM 22 conflict, the conflict control circuit 25 delays the read of the single-port RAM 22 to store the read data in the register 24. The read / write data is held in the register until the next read cycle, and the read / write data is controlled.
Convert to serial data with. By providing the register 24 in this way, there is a margin in the read time of the single-port RAM 2, so that it is possible to give priority to the write side and wait for the read even if there is a conflict, and it is possible to prevent the read data from being lost.

In the latter type of serial data clock transfer circuit, when the write timing and the read timing to the single port RAM 32 conflict, the conflict control circuit 35 delays the write from the register 34 to the single port RAM 32. The control is performed so that the write data temporarily held in the register 34 is written in the single port RAM 32 after the read cycle ends. By providing the register 34 in this way,
Since the writing time of the single port RAM 12 has a margin, it is possible to give priority to the reading side and wait for writing even if there is a conflict, and it is possible to prevent the writing data from being lost.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a clock transfer circuit for serial data as an embodiment of the present invention. In this embodiment, the circuit is configured in the write priority type, and when the write cycle and the read cycle compete with each other, the write cycle is processed first.

In FIG. 2, S _IN is serial data before clock transfer, CLK1 is a clock before clock transfer that is synchronized with this serial data S _IN , S _OUT is serial data after clock transfer, and CLK2 is clock after clock transfer. , WE is a write timing signal generated every eight clocks CLK1 and RE is a read timing signal generated every eight clocks CLK2.

Reference numeral 1 denotes a serial-parallel conversion circuit which serial-parallel converts the serial data S _IN into parallel data by using the clock CLK1. Reference numeral 4 is a write address counter that updates the write address WA in accordance with the write timing signal WE generated based on the first clock CLK1. Reference numeral 7 denotes a contention control circuit which receives the write timing signal WE and the read timing signal RE generated based on the second clock CLK2 and outputs the read timing signal RE as the contention control signal Y. When the read timing signals RE compete with each other, the competition control signal Y is delayed and output so as to avoid the competition.

5 is a competition control signal Y from the competition control circuit 7.
It is a read address counter that updates the read address RA according to the above. Reference numeral 2 denotes a single-port RAM in which parallel data from the serial-parallel conversion circuit 1 is written, which is normally a read mode and is controlled to be in the write mode according to the write timing signal WE. Reference numeral 8 denotes a selector which normally selects the read address RA of the read address counter 5 to write the write timing signal WE.
According to the write address W of the write address counter 4
A is selected and an address is input to the single port RAM 2. Reference numeral 6 is a register for temporarily storing the read data RD from the single port RAM 2 in response to the competition control signal Y from the competition control circuit 7. 3 is read data R from the register 6 according to the read timing signal WE
It is a parallel-serial conversion circuit that performs parallel-serial conversion of D into serial data S _OUT with the second clock CLK2.

FIG. 3 shows a configuration example of the competition control circuit 7 in the above embodiment. As illustrated, a NAND to which the read timing signal RE and the clock CLK2 are input
Flip-flop 72 and flip-flop 7 for holding the rising edges of the outputs of the gate 71 and the NAND gate 71
2 for switching the output signal of 2 to the clock CLK1, an AND gate 74 for opening / closing the output signal of the flip-flop 73 as the contention control signal Y by the write timing signal RE, and a flip-flop for resetting the circuit. And an AND gate 76.

The operation of the apparatus of this embodiment will be described below with reference to the time chart. 4 and 5 show the input side serial data S _IN and the output side serial data S in the embodiment circuit.
It is a figure which shows the phase relationship of _OUT . As shown in the figure, the phase of the serial data S _IN on the input side is the serial data S _IN on the output side.
Since it changes in a certain range with respect to _OUT , the write timing and the read timing may conflict in the single-port RAM 2.

FIG. 6 and FIG. 7 are time charts of signals of respective parts of the clock transfer circuit of the embodiment. In this embodiment, the input serial data S _IN is converted into 8-bit parallel data, then the clock is changed, and the serial data S _OUT is converted and output again.

In the figure, (A) is a clock CLK1 synchronized with the serial data S _IN before clock transfer, (B) is a serial data S _IN input to the serial-parallel conversion circuit 1, and (C) is a clock CLK1. The write timing signals WE and (D) generated for each one are the write address WA generated by the write address counter 4, and (E) is the single port RAM 2
Write / read timing signal XWR (the single port RAM 2 is in the write mode when it is negative logic and is “L”), (F) is the competition control signal Y output from the competition control circuit 7, and (G) is the selection Address / read address selected and output by the device 8, (H) is read data RD from the single port RAM 2, (I) is an EN signal (= contention control signal Y) that gives a write timing to the register 6, (J ) Is the latch data of the register 6, (K) is a read timing signal RE generated every eight clocks CLK2 after clock change, (L) is the clock CLK2 after clock change, and (M) is the clock CLK2 after clock change. Serial data S _OUT (output of the parallel to serial conversion circuit 3)
Is.

First, in a normal state, that is, when the write timing (write cycle) does not conflict with the read timing (read cycle), the single-port RAM
The operation on the writing side of No. 2 will be described. The serial data S _IN is converted by the serial-parallel conversion circuit 1 into parallel data B1 to B8 in 8-bit units using the clock CLK1. The write timing signal WE is generated in synchronization with every 8 bits of the clock CLK1. The write address counter 4 is incremented by one each time the write timing signal WE is input, and the write addresses WA1, WA2,
WA3, WA4 ... Are sequentially generated.

This write timing signal WE is NAND
It is input to the single-port RAM 2 through the gate, which puts the single-port RAM 2 which is normally in the read mode into the write mode. The write timing signal WE is also input to the selector 8 so that the selector 8 selects the write address WA from the write address counter 4. This enables single port RA
The parallel data from the serial-parallel conversion circuit 1 is written into M2 at the write address WA position from the write address counter 4.

Next, the normal single port RAM
The operation on the reading side of No. 2 will be described. The read timing signal RE is generated every eight clocks CLK2 after the clock change. When the read timing signal RE is input during normal operation, the contention control circuit 7 generates and outputs the contention control signal Y having substantially the same timing. The contention control signal Y is input to the read address counter 5 and the register 6. The read address counter 7 is incremented by one each time the contention control signal Y is input, and read addresses RA0, RA1, RA2, RA3, ... Are sequentially generated.

When the write timing signal WE is not input, the selector 8 selects the read address RA from the read address counter 5 and the single port RA.
Since M2 is in the read mode, the read data RD is read from the read address RA position of the read address counter 5 from the single port RAM 2 in this state, and the read data RD becomes the contention control signal Y from the contention control circuit 7. It is taken in the register 6 in synchronization. The read data RD fetched in the register 6 is clocked by the parallel / serial conversion circuit 3 after the clock change to the clock CLK2.
_Is converted into serial data S _OUT and output.
As a result, serial data can be transferred from the clock CLK1 to the clock CLK2.

FIG. 8 is a time chart showing the process of generating the competition control signal Y in the competition control circuit 7 in the normal state. In this time chart, the read cycle and the write cycle are adjacent to each other, but there is no conflict.
To explain the operation, the read timing signal RE is NAN.
When input to the flip-flop 72 via the D gate 71, the flip-flop 72 holds the rising of the read cycle, and the flip-flop 73 switches to the clock CLK1. At this time, since it is not the write cycle, the write timing signal WE is not input, the AND gate 74 is opened, and the read timing signal RE from the flip-flop 73 is ANDed.
The contention control signal Y is output through the gate 74.
Further, the flip-flop 75 is set in the next clock cycle, and its output is given to the reset input of the flip-flop 72 via the AND gate 76 to make the flip-flop 7
Reset 2 and wait for the next read cycle.

Next, the operation when the write timing and the read timing of the single port RAM 2 conflict with each other will be described according to a time chart. Now, it is assumed that the write timing and the read timing overlap with each other in the state where the read address is RA1 and the write address is WA2. In this case, the contention control circuit 7 outputs the contention control signal Y, which was output almost in synchronization with the read timing signal RE, with the clock CL.
By delaying K1 by one and outputting it, it is prevented from overlapping with the write timing signal WE.

The operation on the write side is the same as that described above, and the write address WA2 of the single port RAM 2 is used.
The write data WD2 from the serial-parallel conversion circuit 1 is written in the position of. During this write operation, the read address counter 5 is incremented so that the read address is RA2.
Then, the data of the read address RA1 will be lost thereafter, but in this case, since the contention control signal Y from the contention control circuit 7 is delayed after the write timing signal WE as described above, the single port RAM is used.
The read address RD1 is not incremented during the 2 write operation.

When the write operation of the single port RAM 2 is completed, the selector 8 selects the read address RA1 of the read address counter 5, and the single port RAM is also selected.
2 is in read mode, so single port RAM2
Read data RD1 from the position of the read address RA1 of
Will be read. This read data RD1 is taken into the register 6 at the timing of the delayed competition control signal Y.

At the same time, the read address counter 5 is incremented by 1 to become the read address RD2, so that the read data RD2 is output from the position of the read address RA2 from the single port RAM 2 thereafter, but at the next timing. Since the contention control signal Y of is not yet output, this read data RD2 is not yet taken into the register 6.

Read data RD held in the register 6
1 is taken into the parallel-serial conversion circuit 3 at the timing when the read timing signal RE of the next cycle is generated, and is sequentially converted to the serial data S _OUT at the timing of the clock CLK2. As a result, even when the write timing and the read timing conflict with each other, the clock transfer can be normally performed without causing data loss.

FIG. 9 is a time chart showing a process of generating the competition control signal Y in the competition control circuit 7 at the time of this competition. The operation will be described. As described above, the rising edge of the read timing signal RE is held in the flip-flop 72, and the flip-flop 73 switches to the clock CLK1. At this time, since it is a write cycle, the AND gate 74 is closed by the write timing signal WE, so the read timing signal RE of the flip-flop 73 cannot pass through the AND gate 74, and the contention control signal Y is not output from the AND gate 74. .. In the next clock cycle, the write timing signal WE disappears, and the AND gate 74 is opened, and the read timing signal RE of the flip-flop 73 becomes the AND gate 74.
And is output as a competition control signal Y. The flip-flop 75 is set in the next clock cycle, and the output signal Q resets the flip-flop 72 via the AND gate 76.

FIG. 10 shows a clock data transfer circuit for serial data as another embodiment of the present invention. The circuit of this embodiment has a read-priority type circuit configuration, and when the write cycle and the read cycle compete with each other, the read cycle is performed first and then the write cycle is performed.

In FIG. 10, reference numeral 11 is a serial-parallel conversion circuit for converting serial data S _IN into parallel data by the first clock CLK1. 15 is the second clock CLK2
Is a read address counter for updating the read address RA according to the read timing signal RE generated based on the above. Reference numeral 17 denotes a contention control circuit which receives the read timing signal RE and the write timing signal WE generated based on the first clock CLK1 and outputs the write timing signal WE as the contention control signal Y. The contention control signal Y is delayed and output so that the contention is avoided when the timing signals RE compete.

Reference numeral 14 is a write address counter for updating the write address WA according to the contention control signal Y from the contention control circuit 17. 16 is a write timing signal WE
It is a register for temporarily storing the parallel data from the serial-parallel conversion circuit 11 when receiving the parallel data. 12 is a single port RAM in which the read data from the register 16 is written
In the normal mode, the contention control circuit 1 is in the read mode.
The write mode is controlled in accordance with the competition control signal Y from 7. A selector 18 normally selects the read address RA of the read address counter 15, selects the write address WA of the write address counter 14 according to the contention control signal Y from the contention control circuit 17, and inputs the address to the single port RAM 12. Is.
13 is a single port R according to the read timing signal
The read data RD from the AM is used as the second serial data S _OUT .
Is a parallel-serial conversion circuit that performs parallel-serial conversion with the clock CLK2.

The operation of the circuit of this embodiment will be described below.
First, the operation on the write side of the single port RAM 12 in the normal state will be described. The serial data S _IN is converted by the serial-parallel conversion circuit 1 into 8-bit parallel data using the clock CLK1. The write timing signal WE is generated in synchronization with every 8 clocks of the clock CLK1.
When the write timing signal WE is input during normal operation, the contention control circuit 7 generates and outputs a contention control signal Y having substantially the same timing. This competition control signal Y
Is input to the write address counter 14. The write address counter 14 is incremented one by one each time the contention control signal Y is input to write address WA.
1, WA2, WA3, WA4 ... Are sequentially generated.

The contention control signal Y is input to the selection control terminal of the selector 18 and the write / read mode control terminal of the single port RAM 12. The selector 18 normally selects the output of the read address counter 15, but when the contention control signal Y is generated, the write address counter 14 is selected.
Select the write address WA from the single port R
Input the address to AM12. Single port RAM1
2 is normally in the read mode, but becomes the write mode when the contention control signal Y is input. The write timing signal WE is input to the enable terminal of the register 16.

Therefore, when the write timing signal WE is input, the parallel data converted by the serial-parallel conversion circuit 11 is taken into the register 16 and further the register 1
6 parallel data at the output timing of the contention control signal Y, the write address counter 14 of the single port RAM 12
Is written to the write address WA designated by.

Next, the normal single-port RAM
The operation of the read side 12 will be described. When the write timing signal is not input, the selector 18 selects the read address of the read address counter 15 and inputs it to the single port RAM 12. Also, the single port RAM 12 is in the read mode. Therefore, the read data RD is read from the single port RAM 12 from the read address RA designated by the read address counter 15.

When the read timing signal RE is input here, the read data RD of the single-port RAM 12 is loaded into the parallel-serial conversion circuit 13 by the read timing signal RE and is sequentially converted into serial data S _OUT . Further, the read address counter 15 is incremented by 1 by the read timing signal RE,
Thereafter, the read data RD is read from the read address RA incremented by one in the single port RAM 12.

Next, the operation when the write timing and the read timing of the single port RAM 2 conflict with each other will be described. Now, it is assumed that the write timing and the read timing overlap with each other in the state where the read address is RA1 and the write address is WA2. In this case, the contention control circuit 7 delays the contention control signal Y, which was output almost in synchronization with the write timing signal WE, by one clock CLK1 and outputs the delayed contention control signal Y so as not to overlap with the read timing signal RE.

The operation on the read side is the same as that described above, and the write address RA of the single port RAM 12 is
The read data RD1 is read from the position 1 and loaded into the parallel-serial conversion circuit 13, which is sequentially converted into serial data S _OUT and output.

On the other hand, on the write side, the serial-parallel conversion circuit 11
The parallel data from is temporarily stored in the register 16 by the write timing signal WE.
12 is not in the write mode yet, the parallel data in this register 16 is still in the single port RAM 12
Is not written to. When the read cycle of the read data RD1 is completed, the contention control signal Y is generated, whereby the single port RAM 12 enters the write mode,
Write data WD2 temporarily stored in the register 16
Is written in the position of the write address WA2 of the single port RAM 12, and the write address of the write address counter becomes WA3.

The competition control circuit 17 operates in substantially the same way except that the positions of the write timing signal WE and the read timing signal RE in the circuit of FIG. 3 are interchanged, and therefore detailed description thereof will be omitted. ..

[0040]

As described above, according to the present invention, it is possible to avoid the conflict between the write / read timings caused by using the single-port RAM, and the memory part can be easily integrated into the LSI of the device. LSI
Since it can be included in the inside, it greatly contributes to downsizing of the device.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a clock transfer circuit for serial data as an embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration example of a competition control circuit in the embodiment circuit.

FIG. 4 is a part (1/2) of the time chart for explaining the phase relationship between the serial data on the input side and the serial data on the output side in the embodiment circuit.

FIG. 5 is a part (2/2) of the time chart for explaining the phase relationship between the serial data on the input side and the serial data on the output side in the embodiment circuit.

FIG. 6 is a diagram showing a part (1/2) of a time chart of signals of respective parts for explaining the overall operation of the embodiment circuit.

FIG. 7 is a diagram showing a part (2/2) of a time chart of signals of respective parts for explaining the overall operation of the embodiment circuit.

FIG. 8 is a time chart of signals of respective parts for explaining the operation of the contention control circuit of the embodiment circuit when there is no contention.

FIG. 9 is a time chart of signals of respective parts for explaining the operation at the time of contention of the contention control circuit of the embodiment circuit.

FIG. 10 is a block diagram showing a clock transfer circuit for serial data as another embodiment of the present invention.

[Explanation of symbols]

 1, 11 Serial-parallel conversion circuit 2, 12 Single port RAM 3, 13 Parallel-serial conversion circuit 4, 14 Write address counter 5, 15 Read address counter 6, 16 Register 7, 17 Contention control circuit 71 NAND gate 72, 73, 75 Flip-flop 74, 76 AND gate

Claims (2)

[Claims] 1. A serial-parallel conversion circuit (21) for serial-parallel converting serial data to parallel data at a first clock, a single-port RAM (22) into which parallel data from the serial-parallel conversion circuit is written, and A serial data clock transfer circuit comprising a parallel-serial conversion circuit (23) for parallel-serial converting read data from a single-port RAM into serial data at a second clock, wherein the single-port RAM and the parallel-serial conversion circuit are provided. And a register (24) inserted between the single port RAM and temporarily storing read data from the parallel-serial conversion circuit, and the single port RAM read when the write timing and the read timing of the single port RAM conflict with each other. And a contention control circuit (25) for controlling read data to be written to the register by delaying The clock transfer circuit of serial data. 2. A serial-parallel conversion circuit (31) for serial-parallel converting serial data into parallel data at a first clock, a single-port RAM (32) into which parallel data from the serial-parallel conversion circuit is written, and A serial data clock transfer circuit comprising a parallel-serial conversion circuit (33) for parallel-serial converting read data from a single-port RAM into serial data at a second clock, wherein the serial-parallel conversion circuit and the single-port RAM are provided. Is inserted between the serial-parallel conversion circuit and the single-port RAM
(34) for temporarily storing write data to the single port RAM, and a conflict control circuit (35) for controlling to delay writing from the register to the single port RAM when the write timing and the read timing of the single port RAM conflict with each other. And a serial data clock transfer circuit including.