JPH05153386A - Method and device for image processing - Google Patents

Abstract

PURPOSE:To suppress the increase of scale of a delay circuit despite the increase of types of image processing to be combined by outputting and delaying the area number information accordant with the combination of processing content of the image processing means and converting the area number information into the switch signal of each image processing means. CONSTITUTION:The area number information corresponding to the combination of processing content of a filter processing means 4, a working processing means 5, and a halftone processing means 6 are outputted from an output means 10. Then the area number information are delayed via the delay corrector means 11, 12 and 13 in accordance with the delay of the image signals of those means 4-6. Then the delayed area number information are converted into the switch signals of the means 4-6. In such a constitution, the state of the area number information is delayed in response to the number of means 4-6 which are connected in series. Then the increase of the scale is suppressed for a delay circuit despite of the increase of types image processing to be combined.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus and an image processing method such as a digital copying machine capable of performing different image processing for each designated area in a document image.

[0002]

2. Description of the Related Art Generally, in a digital copying machine, since the read original image data is image-processed by an electric signal,
Image processing and image editing that cannot be done with analog copying machines can be performed. For example, for readability,
It is possible to perform edge emphasis processing on the character part and increase the sharpness of the character by placing emphasis on the resolution of the dither matrix, or on the photo part, smoothing with a filter and putting emphasis on the gradation of the dither matrix. is there. It is also possible to add shadows to a certain area and add value-added special effects such as mosaic and posterization.

Therefore, the image processing is normally performed uniformly on the entire read original, but in the image processing for such an original mixed with pictures, characters, and photographs, or image processing for obtaining a special effect, the original is specified. Image processing different from the others is often performed on the part. When performing processing on a specific portion of a document, a closed area to be processed and its image processing content must be designated in the image processing circuit.

For this purpose, a combination of a plurality of image processing contents for each designated area can be selected as an "area number" has been announced. In an image processing apparatus that performs processing different from other areas in a specific area of such an image, the image is converted into a raster scanning type image signal, and image processing means capable of switching processing contents in real time is provided. At least two or more of them are connected in series, and processing contents can be combined. That is, since the area to be designated is divided into blocks and the area number information is written into and read from the storage means for each block, each area can be specified as usual during image processing after main scanning and sub-scanning. Becomes Further, the actual image processing contents are stored in advance in the storage means,
It may be indirectly specified by the area number.

An image processing apparatus capable of performing similar processing has been proposed by the applicant of the present invention as Japanese Patent Application Laid-Open No. 2-285193. In this proposal, a combination of area numbered image processings is used. After being converted into the image processing switching signal, the switching signals are individually delayed according to the delay of each image signal in the image processing means connected in series.

[0006]

However, according to the proposed example, since delay processing is performed for each switching signal, if the number of types of image processing to be combined is increased, the number of image processing means connected in series is increased. The number (delayed length) and the number of switching signals (delayed width) increase. In response to this, the circuit scale required for delay processing increases two-dimensionally, and it becomes necessary to substantially limit the types of image processing that can be combined.

[0007]

According to a first aspect of the invention, in an image processing apparatus in which a plurality of image processing means are connected in series, the processing contents of which can be switched immediately on the basis of a switching signal. Output means for outputting area number information corresponding to a combination of processing contents, delay means for delaying the area number information according to the delay of the image signal in each image processing means connected in series, and delay by each delay means A conversion means for converting the obtained area number information into a switching signal in each image processing means is provided.

According to a second aspect of the present invention, as the processing method, a plurality of image processing means whose processing contents are switched immediately on the basis of a switching signal are connected in series, and the image processing means whose processing contents are switched are used. In an image processing method for sequentially processing image signals, output means outputs area number information corresponding to a combination of processing contents of each of the image processing means, and the area number information is connected in series to perform image processing. The delay means provided for each of the image processing means in accordance with the delay of the image signal in the means
The area number information delayed by each delay means is converted into a switching signal for the corresponding image processing means by each converting means to switch the processing contents of the image processing means.

[0009]

Even if the number of types of image processing to be combined is increased, the number of image processing means connected in series, that is, the length of the delay can be delayed in response to the area number information. , Increase in circuit scale required for delay processing is 1
It becomes dimensional, and the types of image processing that can be combined are not limited.

[0010]

An embodiment of the present invention will be described with reference to the drawings. This embodiment is applied to, for example, a digital copying machine, and a target image processing unit 1 is electrically provided between a scanner unit 2 and a printer unit 3. Here, the scanner unit 2 reads a document image and outputs a raster scan type image signal to the image processing unit 1. The printer unit 3 performs a recording operation based on the image signal image-processed by the image processing unit 1, and has a laser printer configuration, for example.

The image processing unit 1 performs various kinds of image processing on an image signal. Among them, a plurality of them, in order to simplify the explanation here, a filter processing circuit 4 serving as three image processing means, and a processing process. The circuit 5 and the halftone processing circuit 6 are provided in series. Filter processing circuit 4
Is a circuit that performs spatial filter processing with different coefficients on the image signal, and the filter coefficients can be switched in real time by a switching signal output from the filter control circuit 7. The processing circuit 5 is a circuit that performs image processing on the image signal output after being filtered by the filter processing circuit 4 in the order of shadowing, hollowing (outline extraction), and negative / positive inversion. The ON / OFF of the processing and the hollowing-out processing, the operation mode at the time of ON, and the ON / OFF of the negative / positive inversion processing can be switched in real time by a switching signal output from the processing control circuit 8. The halftone processing circuit 6 performs density adjustment, dithering, on the image signal subjected to the necessary processing by the processing circuit 5.
It is a circuit that performs image processing in the order of erase, density level of density adjustment processing, selection of dither pattern of dither processing,
On / off of the erase process can be switched in real time by a switching signal output from the halftone control circuit 9.

Further, the image processing unit 1 is provided with a region control circuit 10 as an output means. The area control circuit 10 stores area number (area number) information corresponding to a combination of processing contents in the processing circuits 4, 5, and 6,
It is generated according to the progress of the raster scan operation in the scanner unit 2, and is output to each control circuit 7, 8, 9.

Table 1 shows an example of correspondence between combinations of image processing contents and area numbers. Note that Table 1 shows an example in which eight types of filter processing, eight types of shadowing processing, four types of hollowing processing, 16 types of density adjustment processing, and four types of dither processing can be switched, and the control signals for each processing are in order. , 3, 3, 2, 4, 2 bits wide. Also, the area number information is 1 from 0 to 15
There are six types, and the signal width is 4 bits.

[0014]

[Table 1]

In each of the control circuits 7, 8 and 9, the area number information output from the area control circuit 10 corresponds to the processing contents of the processing circuits 4, 5 and 6 as shown in Table 1. A rewritable memory table (not shown) for converting into a switching signal is provided as the converting means. As a result, the selection switching control of the process corresponding to the area number information can be performed. Furthermore, each control circuit 7, 8, 9
Is a delay correction circuit 11, 1 as a delay means for delaying the area number information corresponding to the delay of the image signal generated in the corresponding processing circuit 4, 5, 6 and its internal processing block.
2 and 13 are provided. Thereby, the combination of the processing contents is controlled so as not to shift.

As described above, since the area number information is delayed in order in the delay correction circuits 11, 12 and 13 in response to the delay of the image signal, the delay processing is required even if the number of processing circuits connected in series is increased. The increase in circuit scale becomes one-dimensional, and the types of image processing that can be combined are not particularly limited. Therefore, it is possible to improve multifunctionality regarding image processing.

The structure and operation of the area control circuit 10 used in this embodiment will be described. First, the memory 1 for storing area control data in the area control circuit 10.
An example of address mapping No. 4 will be described with reference to FIG. This memory 14 has a capacity of 512 k words (1 word = 16 bits) as shown in FIG.
The data for one line is supposed to occupy 151 words. Therefore, data of 3472 lines can be stored in the memory 14.

Here, the data structure for one line is shown in FIG.
It is configured as shown in (b). First, the head address of each line is a reference offset address area, and the first to 150th words following this are the bitmap data area.

The relationship between the data of the first to 150th words and the bit map is set as shown in FIG. Each word is MSB first. Also,
The size of the bitmap is 347 as shown in FIG.
The size is 2 lines × 2400 dots, and if the resolution is 8 dots / mm in both the main and sub scanning directions, the size is larger than that of A3 and DLT paper.

Such a memory 14 is accessed by an access circuit having the structure shown in FIG.
The configuration and operation will be described with reference to the timing charts shown in FIGS. First, as shown in FIG. 4, a sub-scanning counter 15 is provided which starts its operation by the effective image area signal FGATE and advances by 151 every time the line synchronization signal LSYNC is input. The address signal SADRS is output. The length of the effective image area signal FGATE is 3
It is controlled not to exceed 472 lines.

Further, as shown in FIG. 5, the pixel synchronization signal CL
A frequency divider circuit 16 for dividing the OCK by 16 and outputting the memory synchronization signal MCLK is provided. This frequency dividing operation is performed in synchronization with the line synchronization signal LSYNC. In addition, the head address signal SA output from the sub-scanning counter 15
DRS is the line synchronization signal LSYNC as shown in this figure.
Changes in synchronization with the rising edge of.

Further, as shown in FIG. 6, there is provided a main scanning counter 17 composed of a counter for counting the memory synchronization signal MCLK which is cleared by the line synchronization signal LSYNC. The main scanning counter 17 outputs an address position signal MADRS in each line and a clear signal CLEAR used in a P / S converter (parallel / serial converter) 18. In addition, the memory 1
A line head detecting circuit 19 is provided for detecting the timing of taking in the reference offset address data output from the No. 4 and outputting the detection signal LHD. The line head detection circuit 19 is provided with a reference offset address holding circuit 20 which holds reference offset address data according to the detection signal LHD and outputs it as an offset address signal OADRS. An adder 21 is provided on the input side of the memory 14, and the address signal ADRS input to the memory 14 is the start address signal SADRS,
It is the sum of the address position signal MADRS and the offset address signal OADRS. Therefore, the reference offset address holding circuit 20 operates so that the held data is cleared according to the line synchronization signal and the reference offset address data corresponding to each line is input.

Further, the P / S converter 18 takes in the 16-bit parallel data PARD output from the memory 14 in synchronization with the memory synchronization signal MCLK and outputs the pixel synchronization signal CLO.
It is output as serial data SERD in synchronization with CK. Since the P / S converter 18 clears the data held according to the clear signal CLEAR output from the main scanning counter 17, the data other than the first to 150th words of each line stored in the memory 14 is cleared. Will not be output.

The memory clear circuit 22 uses the FGATE,
The memory 1 is synchronized with each signal of LSYNC and CLOCK.
4, clear data is actively written, and its operation is controlled by a command from a system control unit (not shown) composed of a microcomputer or the like. The system control unit also writes necessary data in the memory 14.

Data written in the bit map portion will be described with reference to FIG. The data written in the bit map portion is classified into three types as shown in the figure according to the length. The 2-bit length data shown in FIG. 9A is one type of stack reference code, and this code is a special code having no area number attribute. That is, this stack reference code is used when selecting the previous area number, and has the characteristic that its length is extremely short. The 4-bit length data shown in FIG. 2B is of two types, area numbers 0 and 1, and is characterized by a short length. There are 16 types of 7-bit length codes shown in FIG. 7C to represent all area numbers (0 to 15), and the length is standard. In the structure of each bit length code, bit number 1 is the start bit,
By detecting this start bit, the area code detection circuit described later starts its operation. Further, the bit number 2 is used for distinguishing between the 2-bit length code and others (4,7-bit length code), and the bit number 3 is used for distinguishing between the 4-bit length code and the 7-bit length code.

An area code detection circuit for generating and outputting area number information from the serial data SERD output from the P / S converter 18 is constructed as shown in FIG. The configuration and operation will be described with reference to the timing chart shown in FIG. First, the serial data SERD output from the P / S converter 18 is set to the pixel synchronization signal CLOCK.
S / P converter (serial / parallel converter) 2 for converting 6-bit parallel data PD1 to PD6 in synchronization with
3 is provided. A start bit detection circuit 24 is provided which detects the start bit of each bit length code described above based on the data PD1 in the parallel data PD1 to PD6 output from the S / P converter 23. When the start bit detection circuit 24 detects a start bit, it sets a detection flag inside the circuit, and thereby the start bit detection operation is suspended. Further, the 2-bit length code detection circuit 25, the 4-bit length code detection circuit 26, and the 7-bit length code detection circuit 27 each have a detection enable signal EN2, E at a timing corresponding to the code length.
Outputs N4 and EN7.

Here, when the 7-bit length detection circuit 27 receives the detection enable signal EN7, the parallel data PD
Area number is generated based on 1 to 6 and data bus AR
The area number is output on the EA and the acknowledge signal ACK7 is output. This acknowledge signal A
CK7 is flip-flop 2 via OR gate 28
It is input to 9,30. As a result, the flip-flop 29 holds the area number information output by the 7-bit length code detection circuit 27, and the flip-flop 30 holds the area number information output by the flip-flop 29 until then. It Further, the start bit detection circuit 24 resets the detection flag, whereby the start bit detection operation is restarted.

Upon receiving the detection enable signal EN4, the 4-bit length code detection circuit 26 receives the parallel data PD1.
The 4-bit length code is detected based on 3 to 3. At this time, when the 4-bit length code is detected, the detected area number is output on the data bus AREA and the acknowledge signal ACK4 is output. As a result, the flip-flops 29, 30 are detected as in the case of detecting the 7-bit length code.
Of the data held by and the detection flag in the start bit detection circuit 24 is reset. Further, by resetting the detection flag, the start bit detection circuit 2
4 does not output the detection enable signal EN7 at the output timing of the next detection enable signal EN7.

Further, when the 2-bit length detection circuit 25 receives the detection enable signal EN2, the parallel data PD
The 2-bit length code is detected based on 1. At this time, when a 2-bit length code (= stack reference code) is detected, an acknowledge signal ACK2 is output. The acknowledge signal ACK2 is input to the output enable terminal of the flip-flop 30, so that the area number held in the flip-flop 30 is output as it is on the data bus AREA. The acknowledge signal ACK2 also changes the data held in the flip-flops 29 and 30, and resets the detected flag in the start bit detection circuit 24. By resetting the detection flag, the start bit detection circuit 24 does not output the enable signals EN5, 7 at the output timing of the next detection enable signals EN5, 7.

Note that these detection circuits 24, 25, 2
Reference numerals 6 and 27 operate in synchronization with the pixel synchronization signal CLOCK.

The area control circuit 10 is composed of both circuits shown in FIGS. 3 and 8.

By the way, regarding the merit of using the reference offset address shown in FIG. 2, FIG.
Will be described. A digital copying machine in which a combination of a region and image processing contents belonging to the region can be set is known. As an example thereof, FIG.
An example of the relationship with the area number added according to the combination of the image processing contents is shown. Numbers 6, 3 and 7 show examples of area numbers. As in the illustrated example, the area is often set as a rectangular shape, but as described later, it does not necessarily have to be rectangular.

When the area as shown in FIG. 10 (a) is set, the area number pattern in one line output from the area control circuit 10 is highly likely to be the same as the peripheral lines. Therefore, in such a case, as shown in FIG. 10B, the area code data as shown in FIG. 7 is stored in the k-th line and the peripheral lines (k + 1,
A desired area can be controlled simply by storing a predetermined address in the reference offset address in the (+ 2nd line, ...). That is, the system control unit is the memory 14
It is possible to significantly reduce the number of accesses to the memory, and it is possible to significantly reduce the memory setting time.

The advantage of using area codes having different lengths of 2, 4, and 7 bits as shown in FIG. 7 will be described with reference to FIG. 11
As in the case of FIG. 10A, (a) shows a set area,
An example of the relationship with the area code added according to the combination of the image processing contents is shown. Here, the case where area 1 and area 2 are adjacent as triangular areas is shown. This is an example that requires switching of high-definition image processing areas, as indicated by the circles. If a code as shown in FIG. 7 is prepared, an area code having a short length can be assigned to the high-definition switching area in such a case. That is, the system control unit is
As shown in (b), by assigning area number 1 of a 4-bit length code to such an area,
As shown in (c), the next area number can be output with a minimum 4-dot width. This means that the resolution is higher than that when area codes of the same length (for example, all 7-bit length codes) are used.

Further, the merit of using the stack reference code of the 2-bit length code shown in FIG. 7A will be described with reference to FIG. Figure 12 (a)
Shows an example of the relationship between the set area and the area code added according to the combination of the image processing contents, but here, as indicated by the circles, the switching of the image processing contents is high. The case where it is necessary to perform finely is shown. In such cases, the stack reference code can be used to restore the original area number. That is, the system control unit is
Since a 2-bit length code (stack reference code) can be written in such a portion as shown in (b), as a result, as shown in (c) of FIG. The number can be output. This means that high-precision switching control can be performed as compared with using an area code including normal area number information such as a 7-bit length code.

By the way, the system control unit operates the memory clear circuit 22 to enable other control during that time, and it is not necessary to access all the addresses of the memory 14 to erase old data. That is, since it is necessary to access only the changing points of the area, the data setting time can be greatly reduced. Also, FIG.
Since each area code shown in 1 has a length of 2 bits or more, when writing one area code in the memory 14 on the bitmap, there are cases where two addresses are accessed. However, if the memory 14 on the bitmap is cleared in advance, it is only the "1" portion of each code that actually needs to be written. Therefore, the stack reference code (2-bit length code) can be regarded as a code having a length of 1 bit, and the number of times of accessing the memory 14 can be significantly reduced.

[0037]

As described above, according to the present invention, the output means for outputting the area number information corresponding to the combination of the respective processing contents of the image processing means and the image signal in each image processing means connected in series are provided. Since the delay means for delaying the area number information according to the delay and the conversion means for converting the area number information delayed by each delay means into the switching signal in each image processing means are provided, the combination of image processing can be performed. Even if the number of types is increased, it is possible to delay the number of image processing means connected in series, that is, in the state of the area number information in response to the length of delay, thus increasing the circuit scale required for the delay processing. Can be one-dimensional, and the types of image processing that can be combined can be unlimited.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of memory mapping.

FIG. 3 is a block diagram showing a part of a region control circuit.

FIG. 4 is a timing chart showing the operation.

FIG. 5 is a timing chart showing the operation.

FIG. 6 is a timing chart showing the operation.

FIG. 7 is an explanatory diagram showing an example of an area code.

FIG. 8 is a block diagram showing an area code detection circuit in the area control circuit.

FIG. 9 is a timing chart showing the operation.

FIG. 10 is a schematic diagram for explaining the merit of a reference offset address.

FIG. 11 is a schematic diagram for explaining merits of area codes having different lengths.

FIG. 12 is a schematic diagram for explaining the merits of the stack reference code.

[Explanation of symbols]

 4, 5, 6 image processing means 10 output means 11, 12, 13 delay means

Claims (2)

[Claims] 1. An image processing apparatus in which a plurality of image processing means, whose processing contents are switched immediately on the basis of a switching signal, are connected in series, and area number information corresponding to each combination of processing contents of the image processing means is output. Output means to
Delay means for delaying the area number information according to the delay of the image signal in each image processing means connected in series,
An image processing apparatus, comprising: conversion means for converting the area number information delayed by each delay means into a switching signal in each image processing means. 2. Image processing in which a plurality of image processing means whose processing contents are switched immediately based on a switching signal are connected in series and image signals are sequentially processed by these image processing means whose processing contents are switched. In the method, the output means outputs the area number information corresponding to the combination of the processing contents of each of the image processing means, and the area number information is used for each image in accordance with the delay of the image signal in the image processing means connected in series. The area number information delayed by each delay means is converted into a switching signal for the corresponding image processing means by the delay means provided for each processing means to switch the processing contents of the image processing means. An image processing method characterized by the above.