JPH05152859A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05152859A
JPH05152859A JP3312292A JP31229291A JPH05152859A JP H05152859 A JPH05152859 A JP H05152859A JP 3312292 A JP3312292 A JP 3312292A JP 31229291 A JP31229291 A JP 31229291A JP H05152859 A JPH05152859 A JP H05152859A
Authority
JP
Japan
Prior art keywords
operational amplifier
semiconductor device
phase input
analog circuit
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3312292A
Other languages
Japanese (ja)
Inventor
Masami Kurosaki
正己 黒崎
Hiroyuki Sugino
博之 杉野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP3312292A priority Critical patent/JPH05152859A/en
Publication of JPH05152859A publication Critical patent/JPH05152859A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide the semiconductor device whose internal circuit is not malfunctioned even when a high frequency signal is inputted to an external connection pad. CONSTITUTION:An output of an operational amplifier 200 is connected to an opposite phase input terminal and an analog circuit 104, and a voltage division voltage of a power supply potential Vdd is given to a same phase input terminal. An output of an operational amplifier 210 is connected to a wiring pad 105 and an opposite phase input terminal of itself and a voltage division voltage of the power supply potential Vdd is given to the same phase input terminal. A high frequency signal inputted to the wiring pad 105 externally is cut off by the operational amplifiers 200, 210 and not delivered to an analog circuit 104 being the internal circuit. Thus, malfunction of the semiconductor device is avoided.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、外来ノイズに対して
誤動作しにくい半導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device which is less likely to malfunction due to external noise.

【0002】[0002]

【従来の技術】図4は従来の半導体装置を示す回路図で
ある。図において、101,102は抵抗、Vddは電源
電位、Vssは接地電位である。抵抗101と抵抗102
は電源電位Vddと接地電位Vssとの間に直列に接続され
ている。
2. Description of the Related Art FIG. 4 is a circuit diagram showing a conventional semiconductor device. In the figure, 101 and 102 are resistors, Vdd is a power supply potential, and Vss is a ground potential. Resistors 101 and 102
Are connected in series between the power supply potential Vdd and the ground potential Vss.

【0003】演算増幅器103は、ボルテージホロワを
構成している。演算増幅器103は、同相入力端が抵抗
101,102の共通接続点に接続され、出力端がワイ
ヤリングパッド105,自身の逆相入力端およびアナロ
グ回路104に接続されている。
The operational amplifier 103 constitutes a voltage follower. The operational amplifier 103 has an in-phase input end connected to a common connection point of the resistors 101 and 102, and an output end connected to the wiring pad 105, a negative-phase input end of itself, and the analog circuit 104.

【0004】次に動作について説明する。抵抗101と
抵抗102の共通接続点の電位が電源電位Vddの半分の
電位(1/2)Vddになるように抵抗101,102の
抵抗値を設定する。この電位(1/2)Vddは演算増幅
器103の同相入力端に与えられており、また、演算増
幅器103の出力端は逆相入力端に接続されているた
め、演算増幅器103の出力端の電位も(1/2)Vdd
(以下この電位をVrefという)となる。演算増幅器1
03の出力端の電位Vref を基準電位としてIC内部の
アナログ回路104が動作し、また、ワイヤリングパッ
ド105を通してIC外部のアナログ回路が動作する。
Next, the operation will be described. The resistance values of the resistors 101 and 102 are set so that the potential at the common connection point of the resistors 101 and 102 becomes half (1/2) Vdd of the power supply potential Vdd. This potential (1/2) Vdd is given to the in-phase input terminal of the operational amplifier 103, and the output terminal of the operational amplifier 103 is connected to the negative-phase input terminal. M (1/2) Vdd
(Hereinafter, this potential is referred to as Vref). Operational amplifier 1
The analog circuit 104 inside the IC operates with the potential Vref at the output end of 03 as the reference potential, and the analog circuit outside the IC operates through the wiring pad 105.

【0005】[0005]

【発明が解決しようとする課題】従来の半導体装置は以
上のように、IC内部のアナログ回路104とIC外部
のアナログ回路に接続されるワイヤリングパッド105
とが演算増幅器103の出力端で共通接続されているた
め、IC外部からワイヤリングパッド105に高周波が
入力するとIC内部のアナログ回路104が誤動作する
という問題点があった。
As described above, the conventional semiconductor device has the wiring pad 105 connected to the analog circuit 104 inside the IC and the analog circuit outside the IC.
Since and are commonly connected at the output end of the operational amplifier 103, there is a problem that the analog circuit 104 inside the IC malfunctions when a high frequency is input to the wiring pad 105 from outside the IC.

【0006】この発明は上記のような問題点を解決する
ためになされたもので、外部接続用パッドに高周波が入
力しても内部回路が誤動作しない半導体装置を得ること
を目的とする。
The present invention has been made to solve the above problems, and an object thereof is to obtain a semiconductor device in which an internal circuit does not malfunction even when a high frequency is input to an external connection pad.

【0007】[0007]

【課題を解決するための手段】この発明に係る半導体装
置は、外部接続用パッドおよび内部回路にバッファを介
して基準電圧を供給する半導体装置において、前記外部
接続用パッドに基準電圧を供給する第1のバッファと、
前記内部回路に基準電圧を供給する第2のバッファとを
備えている。
A semiconductor device according to the present invention is a semiconductor device which supplies a reference voltage to an external connection pad and an internal circuit via a buffer, wherein a reference voltage is supplied to the external connection pad. 1 buffer,
A second buffer for supplying a reference voltage to the internal circuit.

【0008】[0008]

【作用】この発明においては、外部接続用パッドに基準
電圧を供給する第1のバッファと、内部回路に基準電圧
を供給する第2のバッファとを設けたので、第1,第2
のバッファにより外部接続用パッドに外部から入力され
る高周波の内部回路への伝達が妨げられる。
According to the present invention, the first buffer for supplying the reference voltage to the external connection pad and the second buffer for supplying the reference voltage to the internal circuit are provided.
The buffer prevents the high frequency input to the external connection pad from the outside from being transmitted to the internal circuit.

【0009】[0009]

【実施例】図1はこの発明に係る半導体装置の第1実施
例を示す回路図である。図において、図4に示した従来
回路との相違点は、演算増幅器103をなくし、新たに
ボルテージホロワ構成の演算増幅器200,210をバ
ッファとして設けたことである。演算増幅器200は、
同相入力端が抵抗101と抵抗102の共通接続点に接
続され、出力端がIC内部のアナログ回路104および
自身の逆相入力端に接続されている。演算増幅器210
は、同相入力端が抵抗101と抵抗102の共通接続点
に接続され、出力端がワイヤリングパッド105および
自身の逆相入力端に接続されている。その他の構成は従
来回路と同様である。
1 is a circuit diagram showing a first embodiment of a semiconductor device according to the present invention. In the figure, the difference from the conventional circuit shown in FIG. 4 is that the operational amplifier 103 is eliminated, and operational amplifiers 200 and 210 having a voltage follower configuration are newly provided as buffers. The operational amplifier 200 is
The in-phase input end is connected to the common connection point of the resistors 101 and 102, and the output end is connected to the analog circuit 104 inside the IC and the reverse-phase input end of itself. Operational amplifier 210
Has an in-phase input end connected to a common connection point of the resistors 101 and 102, and an output end connected to the wiring pad 105 and its own negative-phase input end. Other configurations are the same as those of the conventional circuit.

【0010】次に動作について説明する。まず、従来同
様、抵抗101と抵抗102の共通接続点の電位を(1
/2)Vddとする。すると、演算増幅器200の出力端
の電位は(1/2)Vddとなり、この電位がアナログ回
路104に供給される。アナログ回路104はこの電位
を基準電位として動作する。演算増幅器210の出力端
の電位も(1/2)Vddとなり、この電位がワイヤリン
グパッド105を介して外部のアナログ回路に供給さ
れ、該電位を基準電圧として該アナログ回路が動作す
る。
Next, the operation will be described. First, the potential at the common connection point of the resistors 101 and 102 is (1
/ 2) Set to Vdd. Then, the potential of the output terminal of the operational amplifier 200 becomes (1/2) Vdd, and this potential is supplied to the analog circuit 104. The analog circuit 104 operates using this potential as a reference potential. The potential of the output terminal of the operational amplifier 210 also becomes (1/2) Vdd, and this potential is supplied to the external analog circuit via the wiring pad 105, and the analog circuit operates with the potential as a reference voltage.

【0011】アナログ回路104に基準電圧を供給する
演算増幅器200と、ワイヤリングパッド105に基準
電圧を供給する演算増幅器210を別々に設け、アナロ
グ回路104とワイヤリングパッド105が直接接続さ
れないようにしたので、ワイヤリングパッド105に高
周波が入力してもアナログ回路104に入力されず、ア
ナログ回路104が誤動作することがなくなる。
Since the operational amplifier 200 for supplying the reference voltage to the analog circuit 104 and the operational amplifier 210 for supplying the reference voltage to the wiring pad 105 are separately provided so that the analog circuit 104 and the wiring pad 105 are not directly connected, Even if a high frequency is input to the wiring pad 105, it is not input to the analog circuit 104, and the analog circuit 104 does not malfunction.

【0012】図2はこの発明の第2実施例を示す回路図
である。この第2実施例と図1に示した第1実施例との
相違点は、演算増幅器210の同相入力端を抵抗101
と抵抗102との共通接続点ではなく、演算増幅器20
0の出力端に接続したことである。その他の構成は図1
に示した実施例と同様である。
FIG. 2 is a circuit diagram showing a second embodiment of the present invention. The difference between the second embodiment and the first embodiment shown in FIG. 1 is that the common-mode input terminal of the operational amplifier 210 is connected to the resistor 101.
And the resistor 102, not the common connection point, but the operational amplifier 20
0 is connected to the output end. Other configurations are shown in FIG.
It is similar to the embodiment shown in FIG.

【0013】この実施例においてもアナログ回路104
に基準電圧を供給する演算増幅器200と、ワイヤリン
グパッド105に基準電圧を供給する演算増幅器210
を別々に設け、アナログ回路104とワイヤリングパッ
ド105が直接接続されないようにしたので、第1実施
例と同様の効果がある。
Also in this embodiment, the analog circuit 104 is used.
Operational amplifier 200 for supplying a reference voltage to the wiring pad 105 and an operational amplifier 210 for supplying a reference voltage to the wiring pad 105.
Are provided separately so that the analog circuit 104 and the wiring pad 105 are not directly connected, and therefore, the same effect as that of the first embodiment is obtained.

【0014】図3はこの発明の第3実施例を示す回路図
である。図において、第1実施例との相違点は、抵抗1
01,102をなくし、新たに抵抗101a,101
b,102a,102bを設けたことである。抵抗10
1a,102aおよび抵抗101b,102bは各々電
源電位Vddと接地電位Vssとの間に直列に接続されてい
る。そして、抵抗101aと抵抗102aとの共通接続
点が演算増幅器210の同相入力端に、抵抗101b,
102bとの共通接続点は演算増幅器200の同相入力
端に接続されている。その他の構成は第1実施例と同様
である。
FIG. 3 is a circuit diagram showing a third embodiment of the present invention. In the figure, the difference from the first embodiment is that the resistance 1
01 and 102 are eliminated and resistors 101a and 101 are newly added.
b, 102a and 102b are provided. Resistance 10
1a and 102a and resistors 101b and 102b are connected in series between the power supply potential Vdd and the ground potential Vss. The common connection point of the resistors 101a and 102a is connected to the common-mode input terminal of the operational amplifier 210, the resistors 101b,
The common connection point with 102b is connected to the in-phase input terminal of the operational amplifier 200. Other configurations are similar to those of the first embodiment.

【0015】この実施例においてもアナログ回路104
に基準電圧を供給する演算増幅器200と、ワイヤリン
グパッド105に基準電圧を供給する演算増幅器210
を別々に設け、アナログ回路104とワイヤリングパッ
ド105が直接接続されないようにしたので、第1実施
例と同様の効果がある。
Also in this embodiment, the analog circuit 104 is used.
Operational amplifier 200 for supplying the reference voltage to the wiring pad 105 and operational amplifier 210 for supplying the reference voltage to the wiring pad 105
Are provided separately so that the analog circuit 104 and the wiring pad 105 are not directly connected, and therefore, the same effect as that of the first embodiment is obtained.

【0016】なお、上記第1,第2,第3実施例ではボ
ルテージボロワ構成の演算増幅器200,210をバッ
ファとして示したが、その他の構成のバッファを用いて
も上記実施例と同様の効果が得られる。
In the first, second and third embodiments, the operational amplifiers 200 and 210 having the voltage borrower structure are shown as buffers, but the same effect as the above embodiment can be obtained by using the buffers having other structures. Is obtained.

【0017】[0017]

【発明の効果】以上のようにこの発明によれば、外部接
続用パッドに基準電圧を供給する第1のバッファと、内
部回路に基準電圧を供給する第2のバッファとを設けた
ので、第1,第2のバッファにより外部接続用パッドに
外部から入力される高周波の内部回路への伝達が妨げら
れる。その結果、内部回路が誤動作しなくなるという効
果がある。
As described above, according to the present invention, the first buffer for supplying the reference voltage to the external connection pad and the second buffer for supplying the reference voltage to the internal circuit are provided. The first and second buffers prevent the high-frequency input to the external connection pad from the outside to the internal circuit. As a result, the internal circuit does not malfunction.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明に係る半導体装置の第1実施例を示す
回路図である。
FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor device according to the present invention.

【図2】この発明に係る半導体装置の第2実施例を示す
回路図である。
FIG. 2 is a circuit diagram showing a second embodiment of the semiconductor device according to the present invention.

【図3】この発明に係る半導体装置の第3実施例を示す
回路図である。
FIG. 3 is a circuit diagram showing a third embodiment of the semiconductor device according to the present invention.

【図4】従来の半導体装置を示す回路図である。FIG. 4 is a circuit diagram showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

104 アナログ回路 105 ワイヤリングパッド 200,210 演算増幅器 104 analog circuit 105 wiring pad 200, 210 operational amplifier

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 外部接続用パッドおよび内部回路にバッ
ファを介して基準電圧を供給する半導体装置において、 前記外部接続用パッドに基準電圧を供給する第1のバッ
ファと、 前記内部回路に基準電圧を供給する第2のバッファとを
備えた半導体装置。
1. A semiconductor device which supplies a reference voltage to an external connection pad and an internal circuit via a buffer, and a first buffer which supplies a reference voltage to the external connection pad, and a reference voltage to the internal circuit. And a second buffer for supplying the semiconductor device.
JP3312292A 1991-11-27 1991-11-27 Semiconductor device Pending JPH05152859A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3312292A JPH05152859A (en) 1991-11-27 1991-11-27 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3312292A JPH05152859A (en) 1991-11-27 1991-11-27 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05152859A true JPH05152859A (en) 1993-06-18

Family

ID=18027497

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3312292A Pending JPH05152859A (en) 1991-11-27 1991-11-27 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05152859A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03216012A (en) * 1990-01-19 1991-09-24 Fujitsu Ltd Semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03216012A (en) * 1990-01-19 1991-09-24 Fujitsu Ltd Semiconductor device

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