JPH05152794A - Ic chip mounting apparatus - Google Patents
Ic chip mounting apparatusInfo
- Publication number
- JPH05152794A JPH05152794A JP3342450A JP34245091A JPH05152794A JP H05152794 A JPH05152794 A JP H05152794A JP 3342450 A JP3342450 A JP 3342450A JP 34245091 A JP34245091 A JP 34245091A JP H05152794 A JPH05152794 A JP H05152794A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- mounting
- printed circuit
- circuit board
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Supply And Installment Of Electrical Components (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ＩＣチップをプリント
基板上に実装するＩＣチップ実装装置に関し、特に、フ
ェースダウンボンディング方式の実装装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an IC chip mounting apparatus for mounting an IC chip on a printed circuit board, and more particularly to a face down bonding type mounting apparatus.
【０００２】[0002]
【従来の技術】ＩＣチップの実装においては、薄い金属
板を打ち抜いて作製したリードフレームに、金を中心と
した極細線でワイヤボンディングを行うワイヤ方式や、
長尺のシート表面にＩＣチップに適合した配線パターン
を形成し、そのリードとＩＣチップの電極端子（バン
プ）を接続するＴＡＢ（Tape Automated Bonding）方式
などが使用されている。2. Description of the Related Art In mounting an IC chip, a wire system in which a lead frame manufactured by punching out a thin metal plate is wire-bonded with an ultrafine wire centered on gold,
A TAB (Tape Automated Bonding) method or the like is used in which a wiring pattern suitable for an IC chip is formed on the surface of a long sheet and the leads are connected to the electrode terminals (bumps) of the IC chip.
【０００３】ＴＡＢ方式では、図２に示すように、突出
したリード９１にＩＣチップ２０の電極端子２１（バン
プ）が接続される。通常は、ＩＣチップ２０の電極端子
２１（バンプ）を上に向け、その上を通るシートにＩＣ
チップ２０が実装される。この方式は、ワイヤ方式と比
較して、高密度実装・面実装によりディバイスを軽量化
・薄型化できる、多ピンのボンディングが速くかつ信頼
性高くできる、機器搭載前の電気テストができるなどの
利点がある。In the TAB method, as shown in FIG. 2, the electrode terminals 21 (bumps) of the IC chip 20 are connected to the protruding leads 91. Normally, the electrode terminals 21 (bumps) of the IC chip 20 are turned up, and the
The chip 20 is mounted. Compared to the wire method, this method has the advantages of high-density mounting and surface mounting, making it possible to reduce the weight and thickness of the device, fast and reliable multi-pin bonding, and the ability to perform electrical tests before mounting the device. There is.
【０００４】しかしながら、ＴＡＢテープは、柔軟性に
欠けるため、折り曲げて使うには、その部分にスリット
状の溝を必要とし、これが断線不良の原因になってい
る。また、機器搭載前の電気テストで不良が発見されて
も、ＩＣチップの交換ができなかった。However, since the TAB tape lacks flexibility, a slit-shaped groove is required at that portion in order to bend and use it, which causes a disconnection failure. Further, even if a defect was found in the electrical test before mounting the device, the IC chip could not be replaced.
【０００５】そこで、ポリイミドフィルムをベース材に
用いたＦＰＣ（Flexible PrintedCircui）基板にＩＣチ
ップをフェースダウンボンディングするＣＯＦ（Chip O
nFP）方式が開発されている。ＣＯＦ方式では、ＦＰＣ
基板が高屈曲率を有しているため、折り曲げが可能であ
る。また、ＩＣチップとＦＰＣ基板との接合に半田を用
いた場合、ＩＣ不良・接続不良時のＩＣチップの交換が
でき、１基板に複数のＩＣチップを実装するときに特に
効果がある。Therefore, a COF (Chip O) for face-down bonding an IC chip to an FPC (Flexible Printed Circuit) substrate using a polyimide film as a base material.
nFP) method has been developed. In the COF method, FPC
Since the substrate has a high bending rate, it can be bent. Further, when solder is used for joining the IC chip and the FPC board, the IC chip can be replaced when the IC is defective or the connection is defective, which is particularly effective when mounting a plurality of IC chips on one substrate.
【０００６】[0006]
【発明が解決しようとする課題】ところで、ＩＣチップ
の電極端子のピッチは１００μｍ程度であるため、ＩＣ
チップの実装精度は±１０μｍ程度必要となり、高精度
の位置決めが要求される。ＴＡＢ方式では、前述したよ
うに、突出したリード９１にＩＣチップ２０の電極端子
２１（バンプ）が接続されるため、ＩＣチップ２０をＴ
ＡＢテープに重ね合わせた状態で、両者の電極端子を一
つのカメラ９２で撮影することができ、ここでの位置決
め精度が最終的な実装精度となる。従って、実装精度は
高い。By the way, since the pitch of the electrode terminals of the IC chip is about 100 μm, the IC chip
The chip mounting accuracy is required to be about ± 10 μm, and highly accurate positioning is required. In the TAB method, as described above, since the electrode terminals 21 (bumps) of the IC chip 20 are connected to the protruding leads 91, the IC chip 20 is
Both the electrode terminals can be photographed by one camera 92 in a state of being superposed on the AB tape, and the positioning accuracy here is the final mounting accuracy. Therefore, the mounting accuracy is high.
【０００７】ところが、ＣＯＦ方式のようなフェースダ
ウンボンディング実装方式では、図３に示すように、プ
リント基板１０の表面にＩＣチップ２０が直接実装され
るので、プリント基板１０にＩＣチップ２０を搭載した
状態では、両者の電極端子１１、２１を撮影できない。
そのため、図４に示すように、プリント基板１０からＩ
Ｃチップ２０を離した状態で、それぞれが２台のカメラ
９２、９２で別々に撮影される。その結果、撮影の後も
両者が水平移動され、チップ搭載手段の位置合わせ精度
や光学系の位置ずれも、実装精度に影響を与える。従っ
て、ＴＡＢ方式に比べると、実装精度は低い。However, in the face-down bonding mounting method such as the COF method, the IC chip 20 is directly mounted on the surface of the printed circuit board 10 as shown in FIG. 3, so that the IC chip 20 is mounted on the printed circuit board 10. In this state, both electrode terminals 11 and 21 cannot be photographed.
Therefore, as shown in FIG.
With the C chip 20 separated, each of the two cameras 92, 92 takes an image separately. As a result, both are moved horizontally even after photographing, and the positioning accuracy of the chip mounting means and the positional deviation of the optical system also affect the mounting accuracy. Therefore, the mounting accuracy is lower than that of the TAB method.
【０００８】本発明はかかる事情に鑑みて創案されたも
のであり、プリント基板にＩＣチップを搭載した状態で
端子の位置合わせを行うことができないフェースダウン
ボンディング方式に対して、精度の良い実装を行うこと
ができるＩＣチップ実装装置を提供することを目的とす
る。The present invention was devised in view of the above circumstances, and enables accurate mounting in a face-down bonding method in which terminals cannot be aligned with an IC chip mounted on a printed circuit board. It is an object of the present invention to provide an IC chip mounting device that can be implemented.
【０００９】[0009]
【課題を解決するための手段】本発明にかかるＩＣチッ
プ実装装置は、ＩＣチップをプリント基板上に搭載する
搭載手段と、該搭載手段によりプリント基板の上方に誘
導されたＩＣチップとプリント基板との間から、上方の
ＩＣチップおよび下方のプリント基板の各画像をそれぞ
れ入力するように、２台のカメラの光学系を一体化した
画像入力手段と、該画像入力手段により入力されたＩＣ
チップおよびプリント基板の各画像から両者の水平方向
の位置ずれを求める画像処理手段と、該画像処理手段に
より求められた水平方向の位置ずれを解消するように、
搭載手段を制御する制御手段と、水平方向の位置ずれを
解消されてプリント基板上に搭載されたＩＣチップを、
プリント基板に固定するボンディング手段とを具備して
いる。An IC chip mounting apparatus according to the present invention includes a mounting means for mounting an IC chip on a printed circuit board, and an IC chip and a printed circuit board guided above the printed circuit board by the mounting means. Image input means in which the optical systems of the two cameras are integrated so as to input respective images of the upper IC chip and the lower printed circuit board from between, and the IC input by the image input means.
An image processing unit that obtains a horizontal positional displacement between the images of the chip and the printed circuit board, and a horizontal positional displacement obtained by the image processing unit is eliminated.
The control means for controlling the mounting means and the IC chip mounted on the printed circuit board in which the positional displacement in the horizontal direction is eliminated,
Bonding means for fixing to the printed circuit board.
【００１０】[0010]
【実施例】以下、図面を参照して本発明の実施例を説明
する。図１は本発明の一実施例を示すＩＣチップ実装装
置の概略構成図である。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of an IC chip mounting apparatus showing an embodiment of the present invention.
【００１１】本実施例は、ＦＰＣ基板１０上にＩＣチッ
プ２０を搭載して固定するＣＯＦ方式の実装装置であ
り、その搭載を行う搭載手段３０、ＦＰＣ基板１０およ
びＩＣチップ２０の画像を入力する画像入力部４０、画
像入力部４０が入力した画像信号を処理してＩＣチップ
２０の位置ずれ量を計算する画像処理部５０、画像処理
部５０等で得られた情報に基づいて搭載手段３０を制御
する制御部６０、仮接着するためのフラックスを転写す
るフラックス転写手段７０、および本接着を行うボンデ
ィング手段８０を具備している。This embodiment is a COF type mounting apparatus for mounting and fixing the IC chip 20 on the FPC board 10, and the mounting means 30 for mounting the ICF 20 and the images of the FPC board 10 and the IC chip 20 are input. The image input unit 40, the image processing unit 50 that processes the image signal input by the image input unit 40 to calculate the positional displacement amount of the IC chip 20, the mounting unit 30 based on the information obtained by the image processing unit 50, and the like. A control unit 60 for controlling, a flux transfer unit 70 for transferring a flux for temporary bonding, and a bonding unit 80 for main bonding are provided.
【００１２】搭載手段３０としては、基板ステージ３
１、Ｚθステージ３２およびＸ−Ｙステージ３３が設け
られている。基板ステージ３１は、ＦＰＣ基板１０をそ
の電極端子１１を上に向けて吸着保持し、これをＸ−Ｙ
方向に移動させる。Ｚθステージ３２は、ＦＰＣ基板１
０に実装されるＩＣチップ２０を、その電極端子２１を
下に向けて吸着保持し、これをＺ方向およびθ方向に移
動させる。Ｘ−Ｙステージ３３は、Ｚθステージ３２を
Ｘ−Ｙ方向に自在に移動させる。As the mounting means 30, the substrate stage 3 is used.
1, a Zθ stage 32 and an XY stage 33 are provided. The substrate stage 31 sucks and holds the FPC substrate 10 with its electrode terminal 11 facing upward, and holds it by XY.
Move in the direction. The Zθ stage 32 is the FPC board 1
The IC chip 20 mounted on 0 is attracted and held with its electrode terminal 21 facing downward, and moved in the Z direction and the θ direction. The XY stage 33 freely moves the Zθ stage 32 in the XY directions.
【００１３】搭載手段３０により、ＩＣチップ２０は、
ＦＰＣ基板１０の上方に誘導され、Ｘ−Ｙ方向およびθ
方向の位置決めの後、Ｚ方向に下降されて、ＦＰＣ基板
１０上に搭載される。By the mounting means 30, the IC chip 20 is
It is guided above the FPC board 10 in the XY direction and θ.
After the positioning in the direction, it is lowered in the Z direction and mounted on the FPC board 10.
【００１４】画像入力部４０は、２台のカメラ４１ａ、
４１ｂを有する。一方のカメラ４１ａは、プリズム４２
ａを含む光学系を通して、ＦＰＣ基板１０とその上方に
誘導されたＩＣチップ２０との間から、真下を撮影し
て、ＦＰＣ基板１０の画像を入力する。他方のカメラ４
１ｂは、プリズム４２ｂを含む光学系を通して、ＦＰＣ
基板１０とその上方に誘導されたＩＣチップ２０との間
から、真上を撮影して、ＩＣチップ２０の画像を入力す
る。カメラ４１ａ、４１ｂの各光学系は一体化されてい
る。The image input section 40 includes two cameras 41a,
41b. One of the cameras 41a has a prism 42
An image of the FPC board 10 is input by capturing an image right below the space between the FPC board 10 and the IC chip 20 guided above the FPC board 10 through the optical system including a. The other camera 4
1b is an FPC through an optical system including a prism 42b.
An image of the IC chip 20 is input by capturing an image right above from between the substrate 10 and the IC chip 20 guided above the substrate 10. The optical systems of the cameras 41a and 41b are integrated.
【００１５】画像処理部５０は、画像入力部４０が入力
した画像から、ＦＰＣ基板１０とＩＣチップ２０の位置
ずれ量を計測する。計測する方法としては、パターンマ
ッチング法あるいは特徴抽出法を用いる。パターンマッ
チング法では、予め位置決めパターンを登録しておき、
画像入力部４０が入力した画像内から、登録したパター
ンと一致するパターンを検索し、その位置を求める。特
徴抽出法では、ＦＰＣ基板１０のコーナーにある電極端
子の位置と、ＩＣチップ２０のコーナーにある電極端子
の位置を認識する。The image processing unit 50 measures the amount of positional deviation between the FPC board 10 and the IC chip 20 from the image input by the image input unit 40. A pattern matching method or a feature extraction method is used as a measuring method. In the pattern matching method, the positioning pattern is registered in advance,
A pattern matching the registered pattern is searched for in the image input by the image input unit 40, and the position thereof is obtained. In the feature extraction method, the positions of the electrode terminals at the corners of the FPC board 10 and the positions of the electrode terminals at the corners of the IC chip 20 are recognized.
【００１６】制御部６０は、画像処理部５０で得られた
ＦＰＣ基板１０とＩＣチップ２０の位置ずれ量を補正す
るため、基板ステージ３１、Ｚθステージ３２およびＸ
−Ｙステージ３３を移動させる。The control unit 60 corrects the amount of positional deviation between the FPC board 10 and the IC chip 20 obtained by the image processing unit 50, and therefore the control unit 60, the substrate stage 31, the Zθ stage 32, and the X stage.
-Move the Y stage 33.
【００１７】フラックス転写手段７０は、ＦＰＣ基板１
０の電極端子１１またはＩＣチップ２０の電極端子２１
にフラックスを転写する。フラックスは、ＦＰＣ基板１
０上にＩＣチップ２０が搭載されてからそのボンディン
グが完了するまでの間、電極端子１１、２１を仮接着す
る役割と、半田接合の補助を行う役目を有する。The flux transfer means 70 is the FPC board 1
0 electrode terminal 11 or IC chip 20 electrode terminal 21
Transfer the flux to. Flux is FPC board 1
It has a role of temporarily adhering the electrode terminals 11 and 21 from the time the IC chip 20 is mounted on the chip 0 until the bonding is completed, and a role of assisting solder bonding.
【００１８】ボンディング手段８０は、ＦＰＣ基板１０
上に搭載されたＩＣチップ２０を加圧・加熱して、ＦＰ
Ｃ基板１０の電極端子１１とＩＣチップ２０の電極端子
２１を接合する。The bonding means 80 is the FPC board 10.
Pressing and heating the IC chip 20 mounted on the top of the FP
The electrode terminal 11 of the C substrate 10 and the electrode terminal 21 of the IC chip 20 are bonded.
【００１９】ＦＰＣ基板１０にＩＣチップ２０を実装す
るには、ＦＰＣ基板１０が、基板ステージ３１により、
アライメントの行われる位置まで運ばれる。また、ＩＣ
チップ２０が、Ｚθステージ３２に保持されて、Ｘ−Ｙ
ステージ３３により、アライメントの行われる位置まで
運ばれる。更に、画像入力部４０がアライメントの行わ
れる位置まで運ばれる。To mount the IC chip 20 on the FPC board 10, the FPC board 10 is moved by the substrate stage 31.
It is carried to the position where the alignment is performed. Also, IC
The chip 20 is held on the Zθ stage 32, and the XY
By the stage 33, it is carried to a position where alignment is performed. Further, the image input unit 40 is carried to the position where the alignment is performed.
【００２０】ＦＰＣ基板１０の電極端子１１のほぼ真上
に、相対応するＩＣチップ２０の電極端子２１が来る
と、画像入力部４０の２台のカメラ４１ａ、４１ｂによ
り、ＦＰＣ基板１０とＩＣチップ２０の間から、それぞ
れの電極端子１１、２１が撮影される。各画像は、画像
処理部５０に送られ、ここで、電極端子１１、２１のＸ
−Ｙ方向の位置ずれが計測され、更に、その位置ずれが
補正されるように、基板ステージ３１またはＸ−Ｙステ
ージ３３が、制御部６０により制御される。When the corresponding electrode terminal 21 of the IC chip 20 comes directly above the electrode terminal 11 of the FPC board 10, the two cameras 41a and 41b of the image input section 40 are used to drive the FPC board 10 and the IC chip. Each of the electrode terminals 11 and 21 is photographed from between 20. Each image is sent to the image processing unit 50, where the X of the electrode terminals 11 and 21.
The substrate stage 31 or the XY stage 33 is controlled by the control unit 60 so that the displacement in the −Y direction is measured and the displacement is corrected.
【００２１】このようにしてＦＰＣ基板１０とＩＣチッ
プ２０のＸ−Ｙ方向の位置決めが行われた場合には、位
置決め後に、基板ステージ３１またはＸ−Ｙステージ３
３を動かす必要がないので、これらの位置決め精度の影
響が実装精度に及ばない。また、カメラ４１ａ、４１ｂ
の各光学系が一体化されているので、これらの位置決め
精度の影響も排除される。When the FPC board 10 and the IC chip 20 are thus positioned in the XY directions, after the positioning, the substrate stage 31 or the XY stage 3 is positioned.
Since it is not necessary to move 3, the positioning accuracy does not affect the mounting accuracy. In addition, the cameras 41a and 41b
Since these optical systems are integrated, the influence of these positioning accuracy is also eliminated.
【００２２】ＦＰＣ基板１０とＩＣチップ２０のＸ−Ｙ
方向の位置決めが終わると、そのθ方向の位置ずれを検
出するために、画像入力部４０がＸ−Ｙ方向に僅かに移
動され、ＦＰＣ基板１０およびＩＣチップ２０の別の箇
所が撮影される。XY of FPC board 10 and IC chip 20
When the positioning in the direction is completed, the image input unit 40 is slightly moved in the X-Y direction to detect the positional deviation in the θ direction, and another part of the FPC board 10 and the IC chip 20 is photographed.
【００２３】ＦＰＣ基板１０とＩＣチップ２０のＸ−Ｙ
方向およびθ方向の位置決めが終わると、ＦＰＣ基板１
０とＩＣチップ２０との間から画像入力部４０が退避
し、Ｚθステージ３２により、ＩＣチップ２０がＺ方向
に降下される。ＦＰＣ基板１０上にＩＣチップ２０が搭
載されると、ＦＰＣ基板１０の電極端子１１とＩＣチッ
プ２０の電極端子２１が、ボンディング手段８０により
接合される。XY of FPC board 10 and IC chip 20
When the positioning in the direction and θ direction is completed, the FPC board 1
The image input unit 40 is retracted from between 0 and the IC chip 20, and the IC chip 20 is lowered in the Z direction by the Zθ stage 32. When the IC chip 20 is mounted on the FPC board 10, the electrode terminals 11 of the FPC board 10 and the electrode terminals 21 of the IC chip 20 are bonded by the bonding means 80.
【００２４】なお、フラックスの転写は、ＦＰＣ基板１
０上にＩＣチップ２０が搭載されるまでの適当な時期に
行われる。フラックスを必要としない接続方式では、フ
ラックス転写手段７０を省略することができる。The transfer of the flux is performed by the FPC board 1
It is carried out at an appropriate time until the IC chip 20 is mounted on the zero. In the connection method that does not require flux, the flux transfer means 70 can be omitted.
【００２５】[0025]
【発明の効果】以上、本発明にかかるＩＣチップ実装装
置による場合には、プリント基板上に誘導されたＩＣチ
ップとプリント基板との間から、上方のＩＣチップおよ
び下方のプリント基板が撮影されることにより、プリン
ト基板の上方でＩＣチップの水平方向の位置決めがなさ
れる。そのため、位置決め後にＩＣチップを水平方向に
移動させる必要がなく、搭載手段の位置決め精度の影響
を受けずに実装が行われる。また、撮影に使用される２
台のカメラの光学系が一体化されているので、光学系の
位置決め精度の影響も受けない。従って、フェースダウ
ンボンディング方式の実装が行われるにもかかわらず、
ＩＣチップとプリント基板を重ね合わせて位置決めする
のと同程度の優れた実装精度が得られる。As described above, in the case of the IC chip mounting apparatus according to the present invention, the upper IC chip and the lower printed circuit board are photographed from between the IC chip guided on the printed circuit board and the printed circuit board. As a result, the IC chip is positioned in the horizontal direction above the printed circuit board. Therefore, it is not necessary to move the IC chip in the horizontal direction after positioning, and mounting is performed without being affected by the positioning accuracy of the mounting means. Also used for shooting 2
Since the optical system of each camera is integrated, it is not affected by the positioning accuracy of the optical system. Therefore, despite the fact that face-down bonding is implemented,
It is possible to obtain the mounting accuracy as high as that when the IC chip and the printed circuit board are superposed and positioned.
【図１】本発明の一実施例を示すＩＣチップ実装装置の
概略構成図である。FIG. 1 is a schematic configuration diagram of an IC chip mounting apparatus showing an embodiment of the present invention.
【図２】ＴＡＢ方式の実装を説明するための模式図であ
る。FIG. 2 is a schematic diagram for explaining implementation of a TAB method.
【図３】フェースダウンボンディング方式の実装を説明
するための模式図である。FIG. 3 is a schematic diagram for explaining mounting by a face-down bonding method.
【図４】フェースダウンボンディングに使用される従来
の位置決め法を説明するための模式図である。FIG. 4 is a schematic diagram for explaining a conventional positioning method used for face-down bonding.
１０ ＦＰＣ基板（プリント基板） ２０ ＩＣチップ ３０ 搭載手段 ４０ 画像入力部 ４１ａ、４１ｂ カメラ ５０ 画像処理部 ６０ 制御部 ７０ フラックス転写手段 ８０ ボンディング手段 10 FPC board (printed circuit board) 20 IC chip 30 mounting means 40 image input section 41a, 41b camera 50 image processing section 60 control section 70 flux transfer means 80 bonding means
Claims (1)
搭載手段と、該搭載手段によりプリント基板の上方に誘
導されたＩＣチップとプリント基板との間から、上方の
ＩＣチップおよび下方のプリント基板の各画像をそれぞ
れ入力するように、２台のカメラの光学系を一体化した
画像入力手段と、該画像入力手段により入力されたＩＣ
チップおよびプリント基板の各画像から両者の水平方向
の位置ずれを求める画像処理手段と、該画像処理手段に
より求められた水平方向の位置ずれを解消するように、
搭載手段を制御する制御手段と、水平方向の位置ずれを
解消されてプリント基板上に搭載されたＩＣチップを、
プリント基板に固定するボンディング手段とを具備する
ことを特徴とするＩＣチップ実装装置。1. A mounting means for mounting an IC chip on a printed circuit board, and an upper IC chip and a lower printed circuit board from between the IC chip and the printed circuit board guided above the printed circuit board by the mounting means. An image input unit in which optical systems of two cameras are integrated so as to input each image, and an IC input by the image input unit
An image processing unit that obtains a horizontal positional displacement between the images of the chip and the printed circuit board, and a horizontal positional displacement obtained by the image processing unit is eliminated.
The control means for controlling the mounting means and the IC chip mounted on the printed circuit board in which the positional displacement in the horizontal direction is eliminated,
An IC chip mounting apparatus comprising: a bonding means for fixing to a printed circuit board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3342450A JPH05152794A (en) | 1991-11-29 | 1991-11-29 | Ic chip mounting apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3342450A JPH05152794A (en) | 1991-11-29 | 1991-11-29 | Ic chip mounting apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05152794A true JPH05152794A (en) | 1993-06-18 |
Family
ID=18353838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3342450A Pending JPH05152794A (en) | 1991-11-29 | 1991-11-29 | Ic chip mounting apparatus |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05152794A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6141863A (en) * | 1996-10-24 | 2000-11-07 | Fanuc Ltd. | Force-controlled robot system with visual sensor for performing fitting operation |
| JP2001250888A (en) * | 1999-12-22 | 2001-09-14 | General Electric Co <Ge> | Apparatus, method and product therefrom, for aligning die for interconnect metal on flexible substrate |
| DE10012043A1 (en) * | 2000-03-14 | 2001-10-04 | Bosch Gmbh Robert | Device for aligning objects bearing reference marks, has module with two parallel high quality objectives, deflection unit, cameras for transferring acquired images to evaluation unit |
| JP2002280477A (en) * | 2001-03-16 | 2002-09-27 | Sony Corp | Circuit board |
| EP0890989A4 (en) * | 1997-01-24 | 2006-11-02 | Rohm Co Ltd | Semiconductor device and method for manufacturing thereof |
| US10720365B2 (en) | 2016-07-20 | 2020-07-21 | Samsung Electronics Co., Ltd. | Method of measuring misalignment of chips, a method of fabricating a fan-out panel level package using the same, and a fan-out panel level package fabricated thereby |
-
1991
- 1991-11-29 JP JP3342450A patent/JPH05152794A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6141863A (en) * | 1996-10-24 | 2000-11-07 | Fanuc Ltd. | Force-controlled robot system with visual sensor for performing fitting operation |
| EP0890989A4 (en) * | 1997-01-24 | 2006-11-02 | Rohm Co Ltd | Semiconductor device and method for manufacturing thereof |
| JP2001250888A (en) * | 1999-12-22 | 2001-09-14 | General Electric Co <Ge> | Apparatus, method and product therefrom, for aligning die for interconnect metal on flexible substrate |
| DE10012043A1 (en) * | 2000-03-14 | 2001-10-04 | Bosch Gmbh Robert | Device for aligning objects bearing reference marks, has module with two parallel high quality objectives, deflection unit, cameras for transferring acquired images to evaluation unit |
| JP2002280477A (en) * | 2001-03-16 | 2002-09-27 | Sony Corp | Circuit board |
| US10720365B2 (en) | 2016-07-20 | 2020-07-21 | Samsung Electronics Co., Ltd. | Method of measuring misalignment of chips, a method of fabricating a fan-out panel level package using the same, and a fan-out panel level package fabricated thereby |
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