JPH05152533A - Static ram - Google Patents

Abstract

PURPOSE:To provide a static RAM having a small standby current value. CONSTITUTION:A static RAM has a voltage drop resistance region 32 and a high resistance wiring region 31 formed partly at a power source formed of a polycrystalline silicon film 3 for coupling a power source terminal and a latch transistor on a semiconductor substrate 1. A voltage drop occurs by a resistance region 32, a current flowing to the region 31 is reduced, and a standby current value of the RAM is decreased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistance load type static RAM characterized by an electrode line having a resistance region and the like.

[0002]

2. Description of the Related Art In the field of semiconductor devices, particularly semiconductor memories, there is an increasing demand for high speed, low power consumption as well as large capacity. The static RAM is inferior in capacity to 1/4 as compared with the dynamic RAM, but is superior in high speed and low power consumption. However, as CMOS technology has advanced and low power consumption type dynamic RAM has advanced, static RAM is gradually losing its superiority. The most noticeable power consumption is the so-called standby current.

FIG. 3 is a circuit diagram showing the structure of a memory cell of a static RAM. As shown in FIG. 3, the high resistance wirings r ₁ and r ₂ are connected to the power supply terminal Vcc and the latch transistor Q.
It is connected between ₁ and Q ₂ . The sources and drains of the latch transistors Q ₁ and Q ₂ are connected to the ground terminal Vss.
And high resistance wirings r ₁ and r ₂ . Transistors Q ₃ and Q ₄ are for memory cell selection, and the sources and drains of these transistors Q ₃ and Q ₄ are connected between the latch transistors Q ₁ and Q ₂ and a bit line (not shown), and their gates are also connected. Are connected to word lines (not shown).

In the standby state of the static RAM, it is determined only by the current value flowing through the high resistance wiring r ₁ (or r ₂ ) of the circuit shown in FIG. The larger the value of the high resistance wiring r ₁ (or r ₂ ) is, the smaller the standby current value is. However, there are many difficulties in increasing the resistance value of this high resistance wiring. The high resistance wiring is formed of a polycrystalline silicon film, and in order to maximize the resistance value, the wiring width is made small, the film thickness is made thin, and formed as long as possible.
Also, impurities are introduced into this film to increase the resistance.

[0005]

However, in the above conventional configuration, there are various problems in increasing the resistance value of the high resistance wiring in order to reduce the standby current value of the static RAM. There is a limit to processing a polycrystalline silicon film to be thin, thin, and long to form a high resistance wiring, which causes a reduction in device yield. In addition, the method of introducing resistance to increase the resistance is apt to cause deterioration of the temperature characteristics of the device, and is not a very effective method from the future.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a static RAM having a small standby current value.

[0007]

In order to achieve the above object, the present invention provides a voltage drop formed on a part of a power supply line formed of a polycrystalline silicon film connecting a power supply terminal on a semiconductor substrate and a latch transistor. It is configured to have at least a resistance region and a high resistance wiring region.

[0008]

With this configuration, since the voltage of the power supply line itself is lower than the power supply voltage, the current flowing through the high resistance wiring region is reduced and the standby current value of the static RAM is reduced.

[0009]

1 (a) to 1 (e) are sectional views in order of manufacturing steps for illustrating the structure of a static RAM according to an embodiment of the present invention.

As shown in FIG. 1A, a silicon substrate 1
After forming the interlayer insulating film 2 thereon, the polycrystalline silicon film 3 is deposited by the CVD method. Next, as shown in FIG.
Arsenic ions are implanted at 2 × 10 ¹³ cm ^-2 on the polycrystalline silicon film 3 by using a photomask 4 to form a high resistance wiring region 31 and a power line down resistance region 32. However, it is necessary to set the resistance region 32 within a limit of 3/4 of the power supply voltage so as not to cause a malfunction of the latch transistor so as not to drop further.

Next, as shown in FIG. 1 (c), phosphorus ions are formed on the polycrystalline silicon film 3 by using a photomask 5 in an amount of 8 × 1.
By implanting 0 ¹⁵ cm ^-2 , the low resistance wiring region 33 is formed. Next, as shown in FIG. 1D, the polycrystalline silicon film is patterned by dry etching using the photomask 6. Finally, as shown in FIG. 1E, the interlayer insulating film 7, the contact hole 8, the metal wiring 9, and the protective film 1 are further added.
Form 0.

FIG. 2 shows a circuit diagram of the memory cell array portion of the static RAM including the power supply line portion of FIG. In the figure, R represents a resistance region 32 and r represents a high resistance wiring region 31. That is, the resistance region 32 causes the power supply voltage to drop.

[0013]

As is apparent from the above embodiments, the static RAM of the present invention has a resistance region for voltage drop and a high resistance wiring region formed in a part of the power supply line made of a polycrystalline silicon film. Therefore, it is possible to provide a resistance load type static RAM capable of reducing the power supply voltage supplied to the high resistance wiring with a resistor and reducing the standby current value.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process of a power supply line portion of a static RAM according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a memory cell array portion of a static RAM including the power supply line portion of FIG.

FIG. 3 is a circuit diagram of a memory cell array portion of a conventional static RAM.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon substrate (semiconductor substrate) 2 Interlayer insulating film 3 Polycrystalline silicon film 4 Photomask 5 Photomask 6 Photomask 7 Interlayer insulating film 8 Contact hole 9 Metal wiring 10 Protective film 31 High resistance wiring area 32 Resistance area 33 Low resistance wiring region

Claims (3)

[Claims] 1. A resistance region for voltage drop and a high resistance wiring region which are formed in a part of a power supply line made of a polycrystalline silicon film connecting a power supply terminal and a latch transistor on a semiconductor substrate. Static RA
M. 2. A resistance region for voltage drop and a high resistance wiring region formed by selectively introducing impurities into a polycrystalline silicon film connecting a power supply terminal on a semiconductor substrate and a latch transistor, and the resistance region and A static RAM comprising at least a power supply line formed of a low resistance wiring formed by introducing impurities into the polycrystalline silicon film at a high concentration other than a high resistance wiring region. 3. The static RAM according to claim 1, wherein the resistance region and the high resistance wiring region are made of a polycrystalline silicon film having a narrower width and a thinner film thickness than other power supply lines.