JPH05152519A - Manufacture of bicmos element having lge structure - Google Patents

Abstract

PURPOSE: To reduce a leakage current between an emitter and a base, by a method wherein the emitter of an LGE structure is formed from an LDD formed simultaneously at the time of the formation of a low-concentration doped drain(LDD) for CMOS. CONSTITUTION: A prescribed region of an N-type low-concentration silicon layer made of an ion-implantation through a window 35 is covered with oxide sidewalls 38 in such a way as to cover a gate 29 of an N-channel MOS transistor and the sidewalls of a polysilicon layer 26 of an emitter region 31. An extrinsic base diffused region 49 of a V-P-N-P transistor is formed and, at the same time, the ions in the N-type silicon layer covered with the sidewalls 38 are diffused to form an LGE structure having an N-type emitter diffused region 50a of an N-P-N transistor. As an emitter is formed from an LDD formed simultaneously at the time of the formation of a low-concentration doped drain(LDD) for CMOS, the LGE structure can be formed without using an additional mask and a leakage current between the emitter and a base can be reduced.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a polysilicon gate CM.
The present invention relates to a method for manufacturing a BiCMOS device in which an OS transistor and a bipolar transistor are integrated on a single chip, and in particular, LGE (Laterally Graded Emi)
tter) structure NPN transistor and VPNP (Ve
B has a LGE structure that improves the reliability by self-aligning the RTP (Physical PNP) transistor with polysilicon.
The present invention relates to a method for manufacturing an iCMOS device.

[0002]

2. Description of the Related Art According to a conventional general method for manufacturing a BiCMOS device, the NPN transistor and the PNP transistor have a structure in which the emitters / bases thereof are not self-aligned. In addition, the bipolar NPN transistor and the PNP transistor are laterally designed, and the vertically formed NPN transistor and the PN transistor are formed.
It has a drawback that it is inferior to the P-transistor in terms of current driving capability and operating speed.

[0003]

In order to eliminate these drawbacks, polysilicon is used to self-align the emitter-base structures of the bipolar NPN transistor and the VPNP transistor, and a C gate composed of a polysilicon gate is used.
BiCMOS that simultaneously realizes MOS and one chip
A device manufacturing method is disclosed in Japanese Patent Application No.
-277851 (Korea Patent Application No. 91-3021)
No., filed on February 25, 1991),
A cross-sectional view of a BiCMOS device manufactured by this method is shown in FIG. In FIG. 1, although the emitter / base of the NPN transistor and the VPNP transistor have a self-aligned structure, they do not have the LGE structure. Therefore, when the emitter layer of the transistor is thin and the concentration is high, leakage between the emitter / base is caused. There is a drawback that the current increases and the reliability decreases. Further, when the concentration of the junction surface is high and the reverse bias is applied between the emitter and the base, the current gain (h _FE ) is rapidly deteriorated, the aging phenomenon of the transistor is accelerated, and the life of the semiconductor element is shortened. There is a drawback that In addition, in a submicron class or micron class bipolar transistor of 1 μm or less, a reverse carrier bias is applied to the emitter junction to cause a hot carrier phenomenon, so that the deterioration phenomenon of the bipolar transistor becomes more severe. ..

On the other hand, a method for manufacturing an NPN transistor having a self-aligned LGE structure is described by Mitsubishi Electric Corporation in IEDM (1990, pages 227 to 229).
Was announced at. LG manufactured by this method
A vertical cross-sectional view of a transistor having an E structure is shown in FIG. 2, in which an n − -type epitaxial layer is grown on a p-type silicon substrate and then a first oxide layer is formed on the epitaxial layer. A step of growing, a step of forming a p-type base region in a predetermined region of the epitaxial layer, and a step of forming a nitride layer on the first oxide layer,
By opening a predetermined area of the nitride layer and the first oxide layer in order to form a window, the area to be an emitter is opened,
a step of implanting n-type ions to form an n-type emitter region; a step of growing a second oxide layer on the substrate and then performing anisotropic etching to form oxide sidewalls; After implanting ions with low energy through the window formed by the process, heat treatment is performed to form an n + type emitter region, and a polycrystalline silicon layer is formed on the substrate, and then the polycrystal is formed by an ordinary photolithography method. It comprises a step of removing a predetermined region of the silicon layer to form a polycrystalline silicon contact, and a subsequent normal bipolar transistor manufacturing step.

That is, a horizontal electric field is reduced by forming a gradient in the concentration distribution of the emitter in the lateral direction by utilizing the oxide side wall, thereby reducing the bipolar electric field.
A method for manufacturing an NPN transistor having a self-aligned LGE structure that improves the deterioration phenomenon of the N transistor.

However, according to the method of manufacturing a transistor having such an LGE structure, the n region is formed after the emitter region is opened.
-The actual width of the emitter is about twice the width of the oxide side wall, because a high-concentration emitter is formed after implanting ions and covering part of the outside of the emitter region with the oxide side wall. There is a drawback in that the current driving capability is reduced due to the narrowing.

The object of the present invention is to provide a self-aligned emitter /
BiCMOS with a low leakage current of emitter / base by forming an NGE transistor of LGE structure having a base
It is to provide an element. Another object of the present invention is a highly reliable BiCMOS which prevents the aging phenomenon due to h _FE deterioration.
It is to provide an element.

[0008]

In order to achieve the above object, a method of manufacturing a BiCMOS device having an LGE structure according to the present invention is a CMOS having a polysilicon gate.
Bipolar N using transistor and polysilicon
This is realized by forming the emitter of the PN transistor in a self-aligned LGE structure and realizing them in one chip at the same time.

[0009]

The present invention relates to a method of manufacturing a BiCMOS device in which a CMOS transistor composed of a polysilicon gate and a bipolar transistor are integrated on one chip, and particularly, an LGE structure in which the concentration distribution of the emitter is inclined in the lateral direction. Since the emitter / base of the NPN transistor and the VPNP transistor are self-aligned with a polysilicon layer, and the emitter of the LGE structure is formed from the LDD formed at the same time when the lightly doped drain (LDD) for CMOS is formed. An LGE structure can be formed without using an additional mask, and a long-life BiCMOS device having a small emitter / base leakage current and no problem of h _FE deterioration can be obtained.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The BiCMOS of the present invention shown in FIGS.
The present invention will be described in more detail with reference to the drawings showing an example of the manufacturing process of the device and FIG. 7 showing an example of the BiCMOS device obtained by the method of the present invention. As shown in FIG. 3A, after forming a deep n + buried layer for the VPNP transistor, the LOCO is formed by a normal twin well and twin bottom process.
S (Local Oxidation of Sili)
(con) shows a state in which the pad oxide layer has been removed after oxidation. An n + buried layer 60 is formed on the p-type substrate 1 to separate the p + -type bottom layer 2 which becomes the collector region of the VPNP transistor from the substrate 1. After that, a p + bottom layer 2 and an n + type bottom layer 3 are formed by a usual method, an intrinsic epitaxial layer is grown thereon, and then a p well 4 and an n well 5 are formed to prevent field inversion. The channel stop region 6 is formed, and the selective oxide film 7 is formed by the usual LOCOS oxidation method.

Next, as shown in FIG. 3B, the sacrificial oxide film 8 is formed.
Is grown on the substrate for about 40 to 60 nm and then the VPNP
In order to form a collector of the transistor, a photoresist 9 is applied on the substrate, a window 10 is opened in a region which will be a collector of the VPNP transistor by a normal photolithography process, and then boron (B) ions are added at 5 × 10 5. ¹⁴
Ion implantation is performed at ˜2 × 10 ¹⁵ ions / cm ² .

Thereafter, as shown in FIG. 3C, the photoresist 9 is removed and the photoresist 11 is formed on the substrate to form the collector of the NPN transistor.
Is applied, and a window 12 is opened in a region which will be a collector of the NPN transistor by a normal photolithography process.
5 × 10 ¹⁴ to 2 × 10 ¹⁵ phosphorus / (P) ions / cm ²
About ion implantation.

Subsequently, as shown in FIG. 3D, the photoresist 11 is removed, annealing is performed at a high temperature by a usual method, and a collector diffusion region 13 of the NPN transistor and a collector diffusion region 1 of the VPNP transistor are formed.
4 is formed, the sacrificial oxide film 8 is removed by a normal wet etching method to grow a gate oxide film 15 of about 10 to 30 nm, and a polysilicon layer 16 is formed on the substrate to about 30 to 60 nm. After that, a photoresist 17 is applied on the substrate to form a base region of the NPN transistor, and NP is formed by a normal photolithography process.
After opening the window 18 in the base region of the N-transistor, 1 × 10 ^{14 to} 5 × 10 ¹⁴ boron (B) ions /
Ion implantation of about cm ² .

Next, as shown in FIG. 4A, the photoresist 17 is removed and the photoresist 1 is formed on the substrate to form the base of the VPNP transistor.
After applying 9, V in a normal photolithography process
After forming the window 20 in the region that will be the base of the PNP transistor, phosphorus (P) ions are implanted into the ions at about 1 × 10 ^{14 to} 7 × 10 ¹⁴ ions / cm ² . These steps of implanting boron and phosphorus may be performed in any order.

Next, as shown in FIG. 4 (B), the photoresist 19 is removed, and normal high temperature annealing is performed to remove the intrinsic base diffusion region 21 and V of the NPN transistor.
After forming the intrinsic base diffusion region 22 of the PNP transistor, a photoresist 23 is applied on the substrate to form NP.
After forming windows in the diffusion region of the N-transistor and the diffusion region of the VPNP transistor, the polysilicon layer 16 and the gate oxide film 15 are removed by a normal photolithography method to remove the diffusion region 24 and V of the NPN transistor.
A diffusion region 25 of the PNP transistor is formed.

Subsequently, as shown in FIG. 4C, after removing the photoresist 23 on the substrate, 200 to 40 are formed.
A polysilicon layer 26 having a thickness of about 0 nm is formed, and arsenic (As) ions are ion-implanted at about 6 × 10 ¹⁵ to 1 × 10 ¹⁶ ions / cm ² .

Next, as shown in FIG. 4D, a WSi ₂ film 27 of 100 to 20 is formed on the substrate by a normal CVD method.
After forming a film having a thickness of about 0 nm, the oxide film 28 is formed by a similar method.
The oxide film 28, the WSi ₂ film 27, the polysilicon layers 16 and 26, and the gate oxide film 15 are removed by a normal photolithography method to form a film having a thickness of 0 to 4000 nm, and the gate 29 of the n-channel MOS transistor and the p-channel MOS transistor are removed. The gate 30 of the transistor, the emitter region 31 and the collector region 32 of the NPN transistor, and the base region 33 of the VPNP transistor are formed.

Next, as shown in FIG. 5 (A), a photoresist 34 is applied on the substrate by a usual method, and a predetermined region of the photoresist 34 is removed to remove the windows 35, 35a.
Source and drain forming regions of the n-channel MOS transistor, which are formed at the same time and exposed through the windows 35 and 35a, and an intrinsic base diffusion region 2 of the NPN transistor.
1 to each of which phosphorus (P) is ion-implanted to form a lightly-doped drain (LDD; Lightly Doped Dr).
A low concentration n-type silicon layer having an ain structure is formed.

Next, as shown in FIG. 5B, a value obtained by applying the photoresist 36 on the substrate to remove the photoresist 34 and form a p-type LDD structure,
A predetermined area of the photoresist 36 is removed to form a window 37, and the p-channel MO exposed through the window 37 is formed.
Boron (B) ions and BF ₂ ⁺ ions are implanted into the silicon region of the S transistor.

Next, as shown in FIG. 5C, the photoresist 36 is removed, an oxide film is formed to a thickness of about 300 to 700 nm by a normal CVD method, and then the above-mentioned film is formed by a reactive ion etching method. By anisotropically etching the formed oxide film to form the oxide sidewall 38, the gate 29 and the emitter region 31 of the n-channel MOS transistor are formed.
The sidewalls of the polysilicon layers 16 and 26 are covered with the oxide sidewalls 38 to cover predetermined regions of the low-concentration n-type silicon layer ion-implanted through the windows 35 and 35a.

Thereafter, as shown in FIG. 5D, a photoresist 39 is applied, a predetermined region of the photoresist 39 is removed to form a window 40, and then an n-channel M is formed.
Arsenic (As) ions, which are n-type impurities, are added in an amount of 1 × 10 ¹⁵ to form the source and drain of the OS transistor.
Ion implantation is performed at about 9 × 10 ¹⁵ ions / cm ² .

Subsequently, as shown in FIG. 6A, the photoresist 39 is removed, the photoresist 41 is applied, and then a predetermined region of the photoresist 41 is removed to form the windows 42 to 45. The p-channel MOS transistor source / drain, the VPNP transistor emitter / collector, and the NPN transistor extrinsic (ex
In order to form a (trinsic) base, boron (B) ions are ion-implanted at about 1 × 10 ^{15 to} 5 × 10 ¹⁵ ions / cm ² .

Subsequently, as shown in FIG. 6B, the photoresist 41 is removed, and the oxide film 4 is formed by a normal CVD method.
6 is deposited to a thickness of about 200 to 700 nm, and ordinary high temperature annealing is performed to diffuse the ion-implanted window to form the source diffusion region 47 and the drain diffusion region 47a of the n-channel MOS transistor and the p-channel MOS transistor.
Source diffusion region 48 and drain diffusion region 48a of the transistor, extrinsic base diffusion region 49 and emitter diffusion region 49a of the VPNP transistor, extrinsic base diffusion region 50 and emitter diffusion region 50a of the NPN transistor,
50a 'and at the same time, the high-concentration polycrystalline silicon layer 26 of the base electrode of the VPNP transistor is diffused as a diffusion source to form an extrinsic base diffusion region 49 of the VPNP transistor, and at the same time, a high concentration of the emitter region of the NPN transistor is formed. The polycrystalline silicon layer 26 having a high concentration is diffused as a diffusion source, and the n-type silicon layer covered with the oxide side wall 38 is diffused to form an LGE structure having an n-type emitter diffusion region 50a 'of an NPN transistor. ..

Next, the manufacturing process is completed by forming the source electrode S, the drain electrode D, the emitter electrode E, the base electrode B and the collector electrode G by the normal contact process and the metal electrode wiring process, and the manufacturing process is completed, as shown in FIG. A BiCMOS device is obtained.

[0025]

As shown in FIGS. 3A to 3O, when a BiCMOS device is manufactured by the method of the present invention, the LGE formed by grading the concentration distribution of the emitter in the lateral direction.
Since the emitter / base of the NPN transistor and the VPNP transistor of the structure are self-aligned with the polysilicon layer, h due to the reverse bias between the emitter and the base.
There is an advantage that the _FE deterioration phenomenon is prevented and the life of the BiCMOS device is extended.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a conventional BiCMOS device.

FIG. 2 is a cross-sectional view of a transistor having an LGE structure.

FIG. 3 is a diagram showing an example of a manufacturing process of a BiCMOS device according to the present invention.

FIG. 4 is a diagram showing an example of a manufacturing process of a BiCMOS device according to the present invention.

FIG. 5 is a diagram showing an example of a manufacturing process of a BiCMOS device according to the present invention.

FIG. 6 is a diagram showing an example of a manufacturing process of a BiCMOS device according to the present invention.

FIG. 7 is a diagram showing an example of a BiCMOS device obtained by the method of the present invention.

[Explanation of symbols]

1 ... Substrate, 2 ... P + type bottom layer, 3 ... N + type bottom layer,
4 ... p-well, 5 ... n-well, 6 ... channel stop region, 7 ... selective oxide film, 8 ... sacrificial oxide film, 15 ... gate oxide film, 28, 46 ... oxide film, 9, 11, 17, 1
9, 23, 34, 36, 39, 41 ... Photoresist,
10, 12, 18, 20, 35, 35a, 37, 40,
42, 43, 44, 45 ... Window, 13, 14 ... Collector diffusion region, 21, 22 ... Intrinsic base diffusion region, 24, 25
... diffusion region, 16, 26 ... polysilicon layer, 27 ... WS
i ₂ film, 29, 30 ... Gate, 31 ... Emitter region, 3
2 ... Collector region, 33 ... Base region, 38 ... Oxide side wall, 47, 48 ... Source diffusion region, 47a, 48a ... Drain diffusion region, 49, 50 ... Extrinsic base diffusion region,
49a 50a, 50a '... Emitter diffusion region, S, D,
E, B, C ... Electrode, 60 ... Buried layer

Claims (2)

[Claims] 1. An NPN type and a VPNP on a semiconductor substrate.
Method for manufacturing a BiCMOS device including a bipolar transistor and a CMOS transistor
Of the n-type emitter of the n-type transistor and the p + base region are self-aligned by the side wall of the oxide which is formed on the side wall of the emitter and polysilicon which is the diffusion source of the n + emitter region.
The emitter of the PN-type transistor is formed, and the p + emitter region of the VPNP-type transistor is formed in a self-aligned manner by polysilicon as a diffusion source of the n + base region and an oxide sidewall formed on the sidewall of the base.
A method for manufacturing a BiCMOS device having a GE structure. 2. A lightly doped drain region (LDD) for a CMOS transistor is formed at the same time as a lightly doped drain region (LDD) in the emitter region of a bipolar NPN transistor, and n is formed from the obtained lightly doped drain region.
2. The method for manufacturing a BiCMOS device having an LGE structure according to claim 1, wherein the + -type emitter diffusion region and the n-type emitter diffusion region are formed so that the emitter of the NPN transistor has the LGE structure.