JPH05152459A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH05152459A JPH05152459A JP33597691A JP33597691A JPH05152459A JP H05152459 A JPH05152459 A JP H05152459A JP 33597691 A JP33597691 A JP 33597691A JP 33597691 A JP33597691 A JP 33597691A JP H05152459 A JPH05152459 A JP H05152459A
- Authority
- JP
- Japan
- Prior art keywords
- glass epoxy
- integrated circuit
- circuit device
- hybrid integrated
- reinforcing plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は混成集積回路装置に関
し、特に基板の反りを防止して信頼性を改善した混成集
積回路装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit device, and more particularly to a hybrid integrated circuit device in which warpage of a substrate is prevented and reliability is improved.
【０００２】[0002]
【従来の技術】一般に混成集積回路装置は、図３及び図
４に平面図及びそのＢ−Ｂ線断面図を示すように、表面
に所要の配線パターン（図示せず）が形成されたガラス
エポキシ基板１の表面上に１以上の半導体ペレット３を
搭載し、この半導体ペレット３と配線パターンとを金ワ
イヤ６で電気接続する。そして、半導体ペレット３をエ
ポキシ樹脂７で個々にモールドする。又、ガラスエポキ
シ基板１上の他の部分にはチップコンデンサ等のディス
クリート部品４を半田リフロー法等の方法により搭載す
る。更に、外部接続端子５を半田ディップ法により取着
する。尚、図示は省略するが、必要に応じて樹脂により
外装を施している。2. Description of the Related Art Generally, a hybrid integrated circuit device is a glass epoxy having a required wiring pattern (not shown) formed on its surface, as shown in plan views and sectional views taken along line BB of FIGS. One or more semiconductor pellets 3 are mounted on the surface of the substrate 1, and the semiconductor pellets 3 and the wiring pattern are electrically connected by gold wires 6. Then, the semiconductor pellets 3 are individually molded with the epoxy resin 7. Further, a discrete component 4 such as a chip capacitor is mounted on another portion on the glass epoxy substrate 1 by a method such as a solder reflow method. Further, the external connection terminals 5 are attached by the solder dip method. Although not shown in the drawing, an exterior is made of resin if necessary.
【０００３】[0003]
【発明が解決しようとする課題】このような従来の混成
集積回路装置では、ガラスエポキシ基板１と、半導体ペ
レット３をモールドするエポキシ樹脂７との熱膨張係数
が違うために、熱履歴によってガラスエポキシ基板１に
反りが発生する。この反りは、ガラスエポキシ基板１の
厚さが薄いほど、又形状が長細いほど、顕著に発生す
る。このような反りが生じると、搭載された半導体ペレ
ット３に割れが発生するおそれがある。又、混成集積回
路装置をプリント基板に実装する際に、外部接続端子７
がプリント基板の配線面に接触されなくなり、電気接続
が困難になる等の問題がある。In such a conventional hybrid integrated circuit device, since the glass epoxy substrate 1 and the epoxy resin 7 for molding the semiconductor pellets 3 have different thermal expansion coefficients, the glass epoxy is different depending on the thermal history. The substrate 1 is warped. This warpage is more remarkable as the glass epoxy substrate 1 is thinner and the shape is longer and thinner. When such warpage occurs, the mounted semiconductor pellet 3 may be cracked. Also, when mounting the hybrid integrated circuit device on a printed circuit board, the external connection terminal 7
Is no longer in contact with the wiring surface of the printed circuit board, which makes electrical connection difficult.
【０００４】又、半導体ペレット３を封止するためのエ
ポキシ樹脂７が周囲に流れ出し、他の部品４や外部接続
端子５にまで到達して電気的な接続不良を発生させる原
因にもなっている。本発明の目的は、ガラスエポキシ基
板の反りを防ぎ、かつ同時にエポキシ樹脂の流れ出しを
防止して信頼性を改善した混成集積回路装置を提供する
ことにある。Further, the epoxy resin 7 for sealing the semiconductor pellet 3 flows out to the surroundings and reaches the other components 4 and the external connection terminals 5 to cause a defective electrical connection. . It is an object of the present invention to provide a hybrid integrated circuit device in which the glass epoxy substrate is prevented from being warped and at the same time the epoxy resin is prevented from flowing out to improve the reliability.
【０００５】[0005]
【課題を解決するための手段】本発明の混成集積回路装
置は、ガラスエポキシ基板の表面に、少なくとも搭載さ
れる半導体ペレットに対応する部分が開口している補強
板を貼着する。この補強板には、ガラスエポキシ補強
板、或いはアルミニウム補強板を用いることができる。In the hybrid integrated circuit device of the present invention, a reinforcing plate having an opening at least a portion corresponding to a semiconductor pellet to be mounted is attached to the surface of a glass epoxy substrate. As the reinforcing plate, a glass epoxy reinforcing plate or an aluminum reinforcing plate can be used.
【０００６】[0006]
【作用】ガラスエポキシ基板の表面に貼着した補強板に
より、ガラスエポキシ基板の機械的強度を向上させ、半
導体ペレットを封止するためのエポキシ樹脂との熱膨張
係数の違いにより生じるガラスエポキシ基板の反りの発
生を防止し、同時にエポキシ樹脂が周囲に流れ出ること
を防止する。[Function] The reinforcing plate adhered to the surface of the glass epoxy substrate improves the mechanical strength of the glass epoxy substrate and improves the mechanical strength of the glass epoxy substrate. Prevents warpage and at the same time prevents epoxy resin from flowing out.
【０００７】[0007]
【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明の混成集積回路装置の第１実施例の平
面図であり、図２は図１のＡ−Ａ線断面図である。この
混成集積回路装置は、表面に所要の配線パターン（図示
せず）を形成したガラスエポキシ基板１の表面上に、半
導体ペレット３やチップコンデンサ４等の搭載する部品
に対応する部分に開口２ａを設けたガラスエポキシ補強
板２を一体的に貼り付けいる。前記ガラスエポキシ補強
基板２は厚さ約１ｍｍ程度の平板状に形成され、ガラス
エポキシ基板１の外部接続端子５の取り付け部分を除い
た表面上に絶縁性の接着剤で接着される。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. 1 is a plan view of a first embodiment of the hybrid integrated circuit device of the present invention, and FIG. 2 is a sectional view taken along line AA of FIG. In this hybrid integrated circuit device, an opening 2a is formed in a portion corresponding to a mounted component such as a semiconductor pellet 3 or a chip capacitor 4 on the surface of a glass epoxy substrate 1 having a required wiring pattern (not shown) formed on the surface. The provided glass epoxy reinforcing plate 2 is integrally attached. The glass epoxy reinforced substrate 2 is formed into a flat plate having a thickness of about 1 mm, and is adhered to the surface of the glass epoxy substrate 1 excluding the portion where the external connection terminals 5 are attached by an insulating adhesive.
【０００８】その上で、前記ガラスエポキシ補強板２の
開口２ａ内において半導体ペレット３をガラスエポキシ
基板１に搭載し、金ワイヤ６でガラスエポキシ基板１の
配線パターンに電気接続し、更にガラスエポキシ補強板
２の開口２ａ内にエポキシ樹脂７を充填させる。その後
チップコンデンサ４等の他の部品をガラスエポキシ補強
板２の他の開口２ａ内のガラスエポキシ基板１上に半田
付けし、更に外部接続端子５を取付けて混成集積回路を
構成している。Then, the semiconductor pellets 3 are mounted on the glass epoxy substrate 1 in the openings 2a of the glass epoxy reinforcing plate 2, electrically connected to the wiring pattern of the glass epoxy substrate 1 by the gold wires 6, and further glass epoxy reinforcing is performed. The epoxy resin 7 is filled in the opening 2a of the plate 2. After that, other components such as the chip capacitor 4 are soldered onto the glass epoxy substrate 1 in the other openings 2a of the glass epoxy reinforcing plate 2, and the external connection terminals 5 are attached to form a hybrid integrated circuit.
【０００９】このように構成した混成集積回路装置で
は、ガラスエポキシ基板１の表面に貼り付けたガラスエ
ポキシ補強板２によりガラスエポキシ基板１の機械的な
強度が向上され、ガラスエポキシ基板１とエポキシ樹脂
７との熱膨張係数の違いにより生じるガラスエポキシ基
板１の反りの発生が防止できる。又、ガラスエポキシ補
強板２の開口２ａ内に半導体ペレット３を搭載すること
で、半導体ペレット３を封止するためのエポキシ樹脂７
はガラスエポキシ補強板２の板厚が堰となって外部に流
出することを防止することができる。In the hybrid integrated circuit device thus constructed, the mechanical strength of the glass epoxy substrate 1 is improved by the glass epoxy reinforcing plate 2 attached to the surface of the glass epoxy substrate 1, and the glass epoxy substrate 1 and the epoxy resin. It is possible to prevent the warp of the glass epoxy substrate 1 caused by the difference in thermal expansion coefficient from that of the glass epoxy substrate 7. Further, by mounting the semiconductor pellet 3 in the opening 2a of the glass epoxy reinforcing plate 2, an epoxy resin 7 for sealing the semiconductor pellet 3 is formed.
Can prevent the glass epoxy reinforcing plate 2 from becoming a dam and flowing out to the outside.
【００１０】尚、ガラスエポキシ補強基板２の代わりに
アルミニウム補強板を用いることもできる。アルミニウ
ム補強基板を使用することにより、エポキシ樹脂７を充
填する際の熱の放熱性が向上するばかりでなく、半導体
ペレット３で発生した熱の放熱性も向上する。An aluminum reinforcing plate may be used instead of the glass epoxy reinforcing substrate 2. By using the aluminum reinforced substrate, not only the heat dissipation performance of the heat when the epoxy resin 7 is filled but also the heat dissipation performance of the heat generated in the semiconductor pellet 3 is improved.
【００１１】[0011]
【発明の効果】以上説明したように本発明は、ガラスエ
ポキシ基板の表面上に、搭載部品に対応する部分が開口
している補強板を貼着しているので、半導体ペレットを
封止するためのエポキシ樹脂とガラスエポキシ基板との
熱膨張係数の違いにより生じるガラスエポキシ基板の反
りの発生を防止でき、半導体ペレットの割れ等を防止し
て信頼性を向上するとともに、混成集積回路の実装を好
適に行うことができる。又、エポキシ樹脂を開口部内に
充填することで、このエポキシ樹脂がディスクリート部
品や外部接続端子等へ流出することが防止できる効果も
ある。As described above, according to the present invention, since the reinforcing plate having the opening corresponding to the mounted component is attached on the surface of the glass epoxy substrate, the semiconductor pellet is sealed. It is possible to prevent the warp of the glass epoxy substrate caused by the difference in thermal expansion coefficient between the epoxy resin and the glass epoxy substrate, prevent the semiconductor pellet from cracking, etc., and improve the reliability, and it is preferable to mount the hybrid integrated circuit. Can be done. Further, by filling the opening portion with the epoxy resin, there is an effect that the epoxy resin can be prevented from flowing out to the discrete component, the external connection terminal, or the like.
【図１】本発明の混成集積回路装置の第１実施例の平面
図である。FIG. 1 is a plan view of a first embodiment of a hybrid integrated circuit device of the present invention.
【図２】図１のＡ−Ａ線断面図である。FIG. 2 is a sectional view taken along the line AA of FIG.
【図３】従来の混成集積回路装置の平面図である。FIG. 3 is a plan view of a conventional hybrid integrated circuit device.
【図４】図３のＢ−Ｂ線断面図である。FIG. 4 is a sectional view taken along line BB of FIG.
１ ガラスエポキシ基板 ２ ガラスエポキシ補強板 ２ａ 開口 ３ 半導体ペレット ７ エポキシ樹脂 1 Glass Epoxy Substrate 2 Glass Epoxy Reinforcement Plate 2a Opening 3 Semiconductor Pellet 7 Epoxy Resin
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 25/18 7220−4Ｍ Ｈ０１Ｌ 25/04 Ｚ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location H01L 25/18 7220-4M H01L 25/04 Z
Claims (2)
レットを搭載し、かつこの半導体ペレットをエポキシ樹
脂で封止する混成集積回路装置において、前記ガラスエ
ポキシ基板の表面上に少なくとも前記半導体ペレットに
対応する部分を開口した補強板を貼着したことを特徴と
する混成集積回路装置。1. A hybrid integrated circuit device in which a semiconductor pellet is mounted on the surface of a glass epoxy substrate, and the semiconductor pellet is sealed with an epoxy resin, which corresponds to at least the semiconductor pellet on the surface of the glass epoxy substrate. A hybrid integrated circuit device characterized in that a reinforcing plate having an open portion is attached.
ルミニウム補強板で構成する請求項１の混成集積回路装
置。2. The hybrid integrated circuit device according to claim 1, wherein the reinforcing plate comprises a glass epoxy reinforcing plate or an aluminum reinforcing plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33597691A JPH05152459A (en) | 1991-11-27 | 1991-11-27 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33597691A JPH05152459A (en) | 1991-11-27 | 1991-11-27 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05152459A true JPH05152459A (en) | 1993-06-18 |
Family
ID=18294415
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33597691A Pending JPH05152459A (en) | 1991-11-27 | 1991-11-27 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05152459A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007173438A (en) * | 2005-12-21 | 2007-07-05 | Matsushita Electric Ind Co Ltd | Waterproofing construction method and printed wiring board of mounting soldered component |
| JP2012104557A (en) * | 2010-11-08 | 2012-05-31 | Ngk Spark Plug Co Ltd | Wiring board with electronic component and manufacturing method of the same |
-
1991
- 1991-11-27 JP JP33597691A patent/JPH05152459A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007173438A (en) * | 2005-12-21 | 2007-07-05 | Matsushita Electric Ind Co Ltd | Waterproofing construction method and printed wiring board of mounting soldered component |
| JP2012104557A (en) * | 2010-11-08 | 2012-05-31 | Ngk Spark Plug Co Ltd | Wiring board with electronic component and manufacturing method of the same |
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