JPH05152330A - Manufacturing method of thin film transistor - Google Patents

Abstract

PURPOSE:To provide the manufacturing method of a thin film transistor capable of detecting defective products in the initial phase of manufacturing step for increasing manufacturing efficiency. CONSTITUTION:The manufacturing method of thin film transistor is composed of the three steps enumerated as follows, i.e., the first formation step of a gate electrode 2G on a glass substrate 1 (a), the second formation step of an SiNx insulating layer 3, an amorphous silicon layer 9 containing n type impurities and a conductive layer 10 for electrode (b), and the third formation step of a drain electrode 10D, a sourse electrode 10S, a doped layers 9D, 9S by patterning step (c). Next, the shortcircuit test between respective electrodes is made to detect any defective products. Furthermore, as for the acceptable products, the gaps between the doped layers 9D and 9S as well as between the drain electrode 10D and the source electrode 10S are filled up with amorphous silicon so as to form a channel layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor, and more particularly to a technique for improving the yield in the manufacturing process.

[0002]

2. Description of the Related Art Thin film transistors have high utility value especially in the field of liquid crystal displays, and the demand for thin film transistors is expected to increase in the future. A thin film transistor is usually a device in which a gate electrode is formed on a glass substrate, and a source electrode and a drain electrode and a channel layer made of an intrinsic semiconductor are formed on the gate electrode with an insulating layer interposed therebetween. The channel layer is a region formed between the source electrode and the drain electrode, and by controlling the voltage applied to the gate electrode, the channel layer can be turned on or off. It is possible to operate as a switching element in which the source electrode and the drain electrode are turned on / off.

When such a thin film transistor is applied to a liquid crystal display, each transistor is arranged vertically and horizontally in a matrix so that one transistor corresponds to one pixel. Then, for example, by extending the gate electrode in the horizontal direction of this matrix, extending the drain electrode in the vertical direction of this matrix, and connecting the source electrode to the display electrode corresponding to each pixel, by combining the gate electrode and the drain electrode, It becomes possible to control the potential of the display electrode corresponding to an arbitrary pixel.

The mainstream structure of thin film transistors is NSI.
Type (N ⁺ Semiconductor Insulator) and ISI type (Insula
It is a bottom gate type called a tor semiconductor insulator. The NSI type has an advantage over the ISI type in that the manufacturing process is simplified (required mask is reduced). On the other hand, since the ISI type has the etching stopper layer, the intrinsic semiconductor layer in the channel portion is less likely to be damaged by plasma due to patterning, and the uniformity and reproducibility of the film thickness are maintained. Therefore, there is an advantage that a high-quality element having high accuracy regarding electric characteristics can be obtained.

[0005]

As described above, when a liquid crystal display is constructed using thin film transistors,
When the insulation between the gate electrode extending in the horizontal direction of the matrix and the drain electrode extending in the vertical direction becomes defective, the pixels arranged in a matrix become uncontrollable in row or column units. That is, an unnecessary line appears in the vertical or horizontal direction on the screen of the display, and it can no longer be shipped as a product.

Such a defect can be found by a short circuit test performed after the formation process of the source electrode and the drain electrode is completed. However, in the conventional manufacturing method, the step of forming the source electrode and the drain electrode is performed in the latter half of all steps, and therefore, when a defect is found by the short circuit test, most of the steps have already been completed. become. In other words, in the conventional manufacturing method, the short circuit test cannot be performed until the product is almost completed. Therefore, a defective product is subjected to a wasteful process, resulting in a decrease in manufacturing efficiency.

[0007] Therefore, an object of the present invention is to provide a method of manufacturing a thin film transistor capable of detecting a product defect at an early stage of the manufacturing process and improving manufacturing efficiency.

[0008]

Means for Solving the Problems (1) A first invention of the present application is the step of forming a gate electrode on a substrate in a method for manufacturing a thin film transistor, and an insulating layer, a semiconductor impurity-doped layer, an electrode A conductive layer for electrode formation in order, patterning the impurity-doped layer and the conductive layer for electrodes, exposing the insulating layer above the gate electrode, and forming source and drain electrodes by the conductive layer for electrodes. And forming an intrinsic semiconductor layer on the gate electrode and patterning the intrinsic semiconductor layer so that the channel layer made of the intrinsic semiconductor remains above the gate electrode.

(2) A second invention of the present application is, in a method of manufacturing a thin film transistor, a step of forming a gate electrode on a substrate, and an insulating layer, a semiconductor impurity-doped layer, and
Forming a conductive layer for electrodes in order, patterning the impurity-doped layer and the conductive layer for electrodes, exposing the insulating layer in the upper portion of the gate electrode, and forming a source electrode and a drain electrode by the conductive layer for electrodes, By removing part of the source and drain electrodes,
The step of exposing a part of the upper surface of the impurity-doped layer above the gate electrode, and forming the intrinsic semiconductor layer on this, patterning the intrinsic semiconductor layer so that the channel layer made of the intrinsic semiconductor remains above the gate electrode. The steps to do are to do.

[0010]

[Operation] In the conventional method of manufacturing a thin film transistor, the source electrode and the drain electrode are formed after forming the channel layer. On the other hand, in the manufacturing method according to the present invention,
A channel layer is formed after forming the source electrode and the drain electrode. Therefore, in the manufacturing method according to the present invention,
Before forming the channel layer, a short circuit test between electrodes can be performed, and a defective product can be found at an early stage. Further, in the conventional manufacturing method, an etching stopper layer for protecting the channel layer from etching was required when the source electrode and the drain electrode were patterned, but in the manufacturing method according to the present invention, such an etching stopper layer is used. Since the stopper layer is unnecessary, the whole manufacturing process is simplified.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on illustrated embodiments. FIG. 1 is a top view showing a state in which a plurality of thin film transistors are arranged in a matrix when the thin film transistors are used in a general liquid crystal display. The portion shown by the solid line in the drawing is the gate electrode G. The gate electrode G is composed of a main portion that extends in the horizontal direction of the drawing and corresponds to the scanning line of the display, and a gate portion that extends downward from the main portion and that acts as a gate for each transistor element. There is. On the other hand, the portion shown by the broken line in the figure is the drain electrode D, and this drain electrode D extends in the vertical direction of the figure and functions as the data line of the display. In this way, a large number of squares are formed by the plurality of gate electrodes G arranged in the horizontal direction and the plurality of drain electrodes D arranged in the vertical direction, and the display electrodes E (indicated by a chain double-dashed line in FIG. Shown) are formed. Each source electrode S (shown by a chain line in the figure) is formed so as to make electrical contact with each display electrode E, and the active layer A is provided between each source electrode S and the drain electrode D. (Indicated by a dotted line in the figure) are formed. The gate portion of the gate electrode G overlaps with each active layer A.
Depending on the voltage applied to the channel layer in the active layer A,
N / OFF control is possible.

In the above structure, one set of thin film transistors is composed of a source electrode S, a drain electrode D, an active layer A formed between them, and a gate electrode G for controlling the active layer A. Will be. FIG. 1 shows a state in which four sets of thin film transistors are formed, but in reality, a large number of transistors are formed on a two-dimensional plane to form a display in which each display electrode E is one pixel. It By applying a predetermined voltage to the gate electrode G corresponding to one specific scan line, the channel layers of the thin film transistors arranged in a row in the figure can be turned on, and the drain electrodes D as data lines can be applied. The given signal value can be written in the display electrode E. In other words, by selectively applying a voltage to the plurality of gate electrodes G arranged in the horizontal direction of the drawing and the plurality of drain electrodes D arranged in the vertical direction of the drawing, two-dimensional A desired charge can be accumulated in a desired electrode among the large number of display electrodes E arranged on the plane.

The present invention provides a novel method of manufacturing a thin film transistor having the above-mentioned structure. Before describing the method of manufacturing the thin film transistor according to the present invention, for the sake of comparison, a conventional method is used. The general manufacturing method of will be described. Hereinafter, each step of the manufacturing method will be described in order for a cross section corresponding to the cutting plane XX ′ in FIG.

FIG. 2 is a cross-sectional view showing the first half of the steps in this conventional ISI type manufacturing method. First, a gate electrode conductive layer 2 (not shown) is formed on the glass substrate 1 and patterned to form a gate electrode 2G, as shown in FIG. 2 (a). This gate electrode 2
G corresponds to the gate electrode G shown by the solid line in FIG. Subsequently, as shown in FIG. 2B, an insulating layer 3, an intrinsic semiconductor layer 4, and an etching stopper layer 5 are sequentially formed on this. After that, as shown in FIG. 2C, the etching stopper layer 5 is patterned and the etching stopper portion 5 is formed.
leave a. From above, a semiconductor impurity-doped layer 6 is further formed to obtain a structure as shown in FIG. 2 (d).

Next, the latter half of the steps in this conventional manufacturing method will be described with reference to FIG. First, the intrinsic semiconductor layer 4 and the semiconductor impurity-doped layer 6 are patterned to form a channel layer 4a and an impurity-doped layer 6a (corresponding to the active layer A shown by a dotted line in FIG. 1) as shown in FIG. 3 (a). To form. Then, a conductive layer 7 for electrodes (not shown) is formed on this, and as shown in FIG. 3 (b), this is patterned to form a source electrode 7S (source electrode S shown by a chain line in FIG. 1). (Corresponding) and drain electrode 7D (see FIG. 1).
Corresponding to the drain electrode D indicated by the broken line) is formed.
Then, the impurity-doped layer 6a is partially removed by etching to separate it into a drain-side impurity-doped layer 6D and a source-side impurity-doped layer 6S, as shown in FIG. 3 (c). In this etching removal step, the channel layer 4a remains without being etched due to the presence of the etching stopper portion 5a. This completes the manufacturing process of the thin film transistor. When it is used as a liquid crystal display, after that (or in the middle of the above steps), the conductive layer 8 for electrodes is used.
It suffices to form (not shown) and pattern this to form a display electrode layer 8a (corresponding to the display electrode E indicated by a chain double-dashed line in FIG. 1) as shown in FIG.

In the conventional manufacturing method described above, the short circuit test between the drain electrode 7D and the gate electrode 2G is performed as follows.
At least as shown in FIG. 3B, it can be performed only after the drain electrode 7D is formed. If the result of this short circuit test, drain electrode 7D and gate electrode 2
If it is confirmed that there is insulation failure between G and
This display device is to be removed from the manufacturing line as a defective product, and all the processes performed on the display device up to that point are wasted. The manufacturing method according to the present invention makes it possible to perform this short circuit test in the first half step,
It aims to detect defective products at the earliest possible stage and eliminate waste of manufacturing efficiency. Hereinafter, the manufacturing process according to the present invention will be described with reference to FIGS. 4 and 5.

FIG. 4 is a sectional view showing the first half of the steps of the manufacturing method according to the present invention. First, a conductive layer 2 for gate electrode (not shown) is formed on the glass substrate 1, and is patterned to form a gate electrode 2G (chromium in this embodiment, as shown in FIG. 4 (a)). Layers). This gate electrode 2G corresponds to the gate electrode G shown by the solid line in FIG. 1, and this step is similar to the conventional method. Then, as shown in FIG. 4 (b), an insulating layer 3 (SiNx layer in this embodiment) and a semiconductor impurity-doped layer 9 (in this embodiment, n-type impurity-doped amorphous silicon) are formed on the insulating layer 3 (SiNx layer in this embodiment). Hydrogenated layer (n ⁺ a-
Si: H) is used), and a conductive layer 10 for electrodes (chromium layer in this embodiment) is sequentially formed. Subsequently, the semiconductor impurity-doped layer 9 and the electrode conductive layer 10 are patterned to expose the insulating layer 3 above the gate electrode 2G as shown in FIG. 4C, and the drain-side impurity-doped layer 9D and drain The electrode 10D, the source-side impurity-doped layer 9S, and the source electrode 10S are formed. This is the end of the first half process.

Next, the latter half steps of the manufacturing method according to the present invention will be described with reference to FIG. First, Fig. 4 (c)
On the above state, the intrinsic semiconductor layer 11 (in this embodiment, a hydrogen-added amorphous silicon layer (a-Si: H))
Are used) (FIG. 5 (a)). Next, the intrinsic semiconductor layer 11 is patterned to leave the channel layer 11a above the gate electrode 2G (FIG. 5 (b)). Above,
The manufacturing process of the thin film transistor is completed. When used as a liquid crystal display, a step of forming a display electrode layer may be performed thereafter (or in the middle of the above steps).

An advantage of the manufacturing method according to the present invention described above is that the short circuit test between the drain electrode 10D and the gate electrode 2G can be performed in the first half step. That is, when the short-circuit test can be executed at the stage where the structure of FIG. 4C is obtained, and as a result, it is confirmed that insulation failure exists, the display device is removed from the manufacturing line at that time. It can be removed and the latter half process shown in FIG. 5 is not performed. In other words, defective products can be found at the earliest possible stage, and waste of manufacturing efficiency can be eliminated.

For reference, a process that is wasted when a defective product is found will be compared between the conventional manufacturing method and the manufacturing method of the present invention. Generally, in the manufacturing process of a semiconductor device, the photolithography process for patterning is the process that requires the most labor and time, so the number of times the photolithography process is useless can be used as an index of manufacturing efficiency. In the conventional manufacturing method,
The photolithography process performed until the short circuit test is performed is as follows. First, once to form the gate electrode 2G shown in FIG. 2 (a), once to form the etching stopper portion 5a shown in FIG. 2 (c), and the impurity-doped layer 6a shown in FIG. 3 (a). And the channel layer 4a
Once to form the drain electrode 7 shown in FIG. 3 (b).
In order to form the D and the source electrode 7S, the photolithography process is performed once, that is, four times in total.
Therefore, if it is confirmed in the short circuit test that the product is defective, the four photolithography steps performed up to that point are wasted. On the other hand, in the manufacturing method according to the present invention, once to form the gate electrode 2G shown in FIG. 4 (a), the drain side impurity doped layer 9D, the drain electrode 10D, the source side shown in FIG. 4 (c) are formed. Impurity doped layer 9
It is possible to perform the short circuit test after performing the photolithography process once to form the S and source electrodes 10S, twice in total. Therefore, even if the defective product is confirmed by this short-circuit test, the two photolithography processes performed up to that point will be wasted. Thus, in the manufacturing method according to the present invention,
Defective products can be found as early as possible, and manufacturing efficiency can be improved.

Another advantage of the manufacturing method according to the present invention is that it is not necessary to form the etching stopper portion 5a unlike the conventional ISI type manufacturing method. In the conventional method, as shown in FIGS. 3B to 3C, the etching stopper portion 5a is required to protect the channel layer 4a when the impurity-doped layer 6a of the semiconductor is etched. In the method according to the present invention, since the channel layer 11a is formed after each electrode layer is formed, the etching stopper portion 5a becomes unnecessary. Therefore, the total number of steps can be reduced, and more efficient manufacturing can be performed. Further, as compared with the conventional NSI type element, the uniformity and reproducibility of the film thickness of the channel portion can be maintained, so that a high quality element can be obtained. After all, according to the manufacturing method of the present invention, an element of high quality comparable to that of the conventional ISI type element can be produced by the conventional N
It becomes possible to manufacture by the same simple method as the manufacturing method of the SI type element.

A disadvantage of the thin film transistor manufactured by the method of the present invention is that the contact area with the channel layer is smaller than that of the transistor manufactured by the conventional method. This will be explained based on the sectional view. Figure 6
FIG. 4 is a cross-sectional view of the vicinity of a channel of a thin film transistor manufactured by the method of the present invention. Carriers moving between the drain electrode 10D and the source electrode 10S pass through the drain electrode 10D, the drain side impurity doped layer 9D, the channel region C of the channel layer 11a, and the source side impurity doped layer 9S. The source electrode 10S is reached. At this time, the carriers passing through the interfaces between the impurity-doped layers 9D and 9S and the channel region C will pass through the regions indicated by the arrows in the figure. Thus, considering the interface with the channel region C, the thin film transistor manufactured by the conventional method becomes wider. FIG. 7 is a cross-sectional view of the vicinity of a channel of a thin film transistor manufactured by a conventional method,
In this transistor, the interface with the channel region C can be quite wide (the number of arrows shown in the figure corresponds to the area of the interface). In other words, the interface with the channel region C is a vertical plane in the transistor according to the present invention shown in FIG. 6, whereas it is almost horizontal in the conventional transistor shown in FIG. Therefore, as compared with the conventional transistor, the transistor of the present invention has a structure in which the area of the interface with the channel region C is less likely to be large. Therefore, in order to secure a large area of this interface, it is preferable to make the thickness of the impurity-doped layers 9D and 9S as large as possible.

Finally, another embodiment for overcoming the above-mentioned disadvantages will be described. Now, it is assumed that the short-circuit test has passed in the state shown in FIG. 4 (c). In the above-described embodiment, the intrinsic semiconductor layer 11 is formed thereafter as shown in FIG. 5A, but before that, as shown in FIG.
By removing a part of the source electrode 10S and the drain electrode 10D, a step of exposing a part of the upper surfaces of the impurity-doped layers 9S and 9D above the gate electrode 2G is added. As a result of adding such a process,
The structure of the finally obtained transistor is as shown in FIG. The structure of FIG. 9 has an advantage that the area of the interface with the channel region C can be made larger than that of the structure of FIG.

Although the present invention has been described above based on the illustrated embodiment, the present invention is not limited to this embodiment and can be implemented in various modes other than this. In particular, the material of each part constituting the thin film transistor is only one example in the above-mentioned embodiment, and any material may be used. For example, as the insulating layer 3, S
In addition to the _{iNx, SiOx, Ta 2 O 5} , W-TaO
x, Mo-TaOx, etc. can be used, and as each electrode, in addition to chromium, Al, Ta, W-Ta, M
o, Mo-Ta, Mo-Si, Ti, etc. can be used. It is also possible to use polysilicon instead of amorphous silicon.

[0025]

As described above, in the method of manufacturing a thin film transistor according to the present invention, since the channel layer is formed after the source electrode and the drain electrode are formed, the short circuit test between the electrodes can be performed in the initial stage. Product defects can be detected in the early stages of the manufacturing process, and manufacturing efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a top view showing a state in which a plurality of thin film transistors are arranged in a matrix when the thin film transistors are used in a general liquid crystal display.

FIG. 2 is a cross-sectional view showing a first half of steps in a conventional ISI type manufacturing method.

FIG. 3 is a cross-sectional view showing the latter half of the steps of the conventional ISI type manufacturing method.

FIG. 4 is a cross-sectional view showing the first half of the steps in the manufacturing method of the present invention.

FIG. 5 is a cross-sectional view showing the latter half of the steps in the manufacturing method of the present invention.

FIG. 6 is a cross-sectional view in the vicinity of a channel of a thin film transistor manufactured by the method according to the present invention.

FIG. 7 is a cross-sectional view near a channel of a thin film transistor manufactured by a conventional method.

FIG. 8 is a cross-sectional view showing additional steps in a manufacturing method according to another embodiment of the present invention.

9 is a cross-sectional view in the vicinity of a channel of a thin film transistor obtained by adding the step shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Glass substrate 2 ... Conductive layer for gate electrode 2G ... Gate electrode 3 ... Insulating layer 4 ... Channel layer 5 ... Etching stopper layer 5a ... Etching stopper part 6 ... Semiconductor impurity dope layer 6D ... Drain side impurity dope layer 6S ... Source Side impurity doped layer 7 ... Electrode conductive layer 7D ... Drain electrode 7S ... Source electrode 8 ... Electrode conductive layer 8a ... Display electrode layer 9 ... Semiconductor impurity doped layer 9D ... Drain side impurity doped layer 9S ... Source side impurity doped layer 10 ... Electrode conductive layer 10D ... Drain electrode 10S ... Source electrode 11 ... Intrinsic semiconductor layer 11a ... Channel layer 11A ... Active layer C ... Channel region D ... Drain electrode (data line) E ... Display electrode G ... Gate electrode (scanning) Line) S ... Source electrode

Claims (2)

[Claims] 1. A step of forming a gate electrode on a substrate, a step of sequentially forming an insulating layer, a semiconductor impurity-doped layer, and an electrode conductive layer on the substrate, and the impurity-doped layer and the electrode conductive layer. And exposing the insulating layer above the gate electrode, and forming a source electrode and a drain electrode by the conductive layer for electrodes, and forming an intrinsic semiconductor layer on the source electrode and the drain electrode. And a step of patterning the intrinsic semiconductor layer so that a channel layer made of an intrinsic semiconductor remains. 2. A step of forming a gate electrode on a substrate, a step of sequentially forming an insulating layer, a semiconductor impurity-doped layer, and a conductive layer for electrodes on the gate electrode, and the impurity-doped layer and the conductive layer for electrodes. Patterning, exposing the insulating layer above the gate electrode, forming a source electrode and a drain electrode by the conductive layer for electrodes, and removing a part of the source electrode and the drain electrode, Exposing a part of the upper surface of the impurity-doped layer in the upper portion of the gate electrode, forming an intrinsic semiconductor layer on the upper portion, and exposing the intrinsic semiconductor layer so that a channel layer made of an intrinsic semiconductor remains in the upper portion of the gate electrode. A method of manufacturing a thin film transistor, comprising: patterning a semiconductor layer.