JPH05151346A - Image processor - Google Patents

Abstract

PURPOSE:To provide the image processor which can supply image data of an overlap part without a break to the respective processors by using only a memory chip corresponding to divided screens. CONSTITUTION:The image processor is provided with plural memories 1, 2 for storing an image divided into plural areas so that each area is adjacent to each other, respectively, and plural address generating parts provided so as to correspond to plural memories l, 2 in order to generate an independent address at every memory. These plural address generating parts generate continuously an address of the other area as for the areas being adjacent to, each other in plural areas, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing apparatus,
In particular, the present invention relates to a device in which an image memory is divided into several parts and pixels are simultaneously read out from the divided parts.

[0002]

Conventionally, in convolution operations of the image was to confirm the value using the pixel of interest D values D ₂ to D ₉ 8 pixels in the vicinity thereof with respect to ₁ as shown in FIG. 9 .. For example, in order to obtain the value G 1 of the part of ₁ , G ₁ =
_{9 × D 1 -D 2 -D 3} -D 4 -D 5 -D 6 -D 7 -D 8
Calculate using the formula -D ₉ .

Therefore, when an image is divided into two for parallel processing for high-speed processing as shown in FIG. 10, the pixels of S1 and S2, which are the overlapping portions, are processed by both buses B1 and B.
Must output to 2. Therefore, two portions of S1 and S2 are prepared as shown in FIG. 11, and when the image is input to the memory, they are simultaneously written here, and at the time of reading, all the data can be read by reading from another S1 and S2. Was supplied to the processor.

[0004]

However, in the method as described above, the same memory chip cannot be used to simultaneously execute the writing to the memory in the overlapping portion. For example, in order to divide into two, two overlapping memories and two divided memories, that is, a total of four memories are required. The image processing apparatus of the present invention is made in view of such a problem, and an object thereof is to process the image data of the overlapping portion by using only the memory chips corresponding to the divided screens. An object of the present invention is to provide an image processing device which can be supplied to the device without any break.

[0005]

In order to achieve the above object, the image processing apparatus of the present invention comprises a plurality of storage means for respectively storing images divided into a plurality of areas so that the areas are adjacent to each other. , A plurality of address generating means provided corresponding to the plurality of storing means so as to generate independent addresses for each storing means, and the plurality of address generating means are adjacent to each other in a plurality of areas. An image processing apparatus characterized in that an address of another area is continuously generated for an area to be processed.

[0006]

That is, according to the present invention, an image is divided into a plurality of areas so that the areas are adjacent to each other, and an independent address is generated corresponding to each area. Area addresses are generated consecutively.

[0007]

EXAMPLE An example of the present invention will be described below.

FIG. 1 shows an overall view when an image is divided into two. In the figure, image data is sent to memories 1 and 2 through a data bus 5. Addresses for the memories 1 and 2 are given to the memories 1 and 2 through the address bus 6.
A part of them is decoded by the decoder 4 and becomes the memory chip select signals 7 and 8. The image-divided portion is transferred to the memories 1 and 2 by this signal.

When reading data from the memory, the data is transferred from the memories 1 and 2 through the output data buses 9 and 10 to the controller 3, where the overlapping portion is processed by the method described later, and then sequentially through the respective pixel data buses 11 and 12. Is output. At this time, the controller 3 gives the read address of the memories 1 and 2 to the memories through the address buses 13 and 14 respectively. Since the memories 1 and 2 thus receive two types of addresses for writing and reading, the multiplexers 15 and 16 are switched so that the necessary addresses are stored in the memories 1 and 2.
The operation when reading image data will be described below.

FIG. 2 shows the detailed configuration of the controller 3, but the address generation part will be described later. An image to be input is defined prior to the explanation of this circuit. The input image is shown in FIG.
If the respective addresses are 000 to 015 and 100 to 115, each becomes the address of the data output to the output data buses 9 and 10. Hereinafter, the former will be referred to as the 0-side image and the latter will be referred to as the 1-side image, which are stored in the memory 1 and the memory 2 of FIG.

The image data output from the bus 9 is latched by the latch 17 or input to the MUX 19. The output of the latch 17 becomes the input of the MUX 19 or the MUX 20. The data output from the bus 10 is transferred to the latch 18,
21 or MUX 20.

As a result, one of the outputs of the bus 9 and the latches 17, 18, 21 is selectively output as the output of the MUX 19. As the output of the MUX 20, one of the outputs of the bus 10 and the latches 17 and 18 is selectively output.

FIG. 4 shows the timing output of each address and latch. Address 0 is the address for the 0 side image,
The address 1 is given to the memory 1 via the address bus 13, and the address 1 is an address for the 1-side image and is given to the memory 2 via the address bus 14. Where XXX and X are
The content is a good value (value not used) and an indefinite value. Further, it is assumed that the addressed data is output with the same value as that address.

If a circuit using a line buffer as shown in FIG. 6 is used in order to perform 3 × 3 arithmetic operation on an image, only one pixel at a time is read from the image memory, and the arithmetic processor operates 3 pixels. The result of the × 3 matrix operation appears.

That is, the data output from the image memory 100 enters the shifter 101 at the same time as it enters the a input of the arithmetic processor 103. This value is output with the same delay as the number of pixels in the line, and is input to b and at the same time, this value is input to the shifter 102 and similarly to the c terminal.

Further, the shifter can shift the data at the same clock as the clock for outputting the data from the image memory 100 to store the pixels for one line. Therefore, the output is delayed by one line.

When such a circuit is used, it is possible to sequentially provide three pixels to the matrix operation circuit by simply reading one pixel at a time from the pixel memory. Pixels given every 3 pixels can generate data for 3 × 3 matrix calculation by using the latch group of FIG. 7.

First, the address 003 is input to the 0 side image memory, and the output value is latched by the latch 17. At the timing when the next address is output, the 0-side image memory outputs nothing (or the value is not used even if it is output). Next, the address 000 is input, the image data is input to the MUX 19, and the MUX 19 outputs this value.

Next, the addresses 001 and 002 are input to the memory, and the corresponding values are output. This value is also output from MUX 19. The MUX 19 outputs the value first latched by the latch 17 at the timing when the next address 007 is input to the memory. When the memory is outputting the data of 007, the latch 17 latches the value. Therefore, at the timing when this address is input, the MUX outputs the value latched until then in the first half, and the latch tries to newly latch another value in the latter half. 1 when the next address is output
Since the side image data 100 is needed,
The output of the latch 21 comes to be output from the MUX 19.

The latch timing of the latch 21 is performed when the value of the address 100 is being output, as can be seen from the figure. The operation of the one-side image memory will be described later. By the operation up to here, one line, that is, 000,001,00
The value of 2,003,100 was output from the MUX 19 in order. After that, the same operation is repeated and the value of the next line is output.

Next, the operation of the one-side image memory will be described. 1
As for the side address, first, 103 is input to the memory, and the value output from the memory at this time is latched by the latch 18. The MUX 20 selectively outputs the value latched by the latch 17 at the timing when the next address is input to the memory.
Next, 100 addresses are input to the memory, the value output at this time is latched by the latch 21, and the MUX 20
Output selectively.

At the next 101 and 102 addresses, the MU
It is input to X20, and MUX20 outputs at the input timing. At the timing when the next 107 addresses are input to the memory, the value previously latched by the latch 18 is selectively output by the MUX 20. Further, at the same timing, the latch 18 latches the value output from the memory. Therefore, at this timing, the MUX 20 selectively outputs the value latched by the latch 18 in the first half as in the 0-side image, and latches the value output from the memory in the latter half. In this way, the MUX 20 sets the value of one line to 003,10.
Address values 0, 101, 102, 103 are output in order. Similarly, the values on the next line are sequentially output from the MUX 20.

The addresses given to the 0-side and 1-side image memories are not incremented in order as in the case of an ordinary counter, so that they are generated by the circuit shown in FIG. The following values may be repeated as the values generated by this circuit. 3 → 0 → 0 → 1 → 2 → 7 → 4 → 4 → 5 → 6 → 11 → 8 →
8 → 9 → 10 → 15 → 12 → 12 → 13 → 14 → 3 This is the same as the above-mentioned one in which XXX of address 0 is changed to 0.

The values output from the latch 30 and the latch 40 are as shown in FIG. The latch '30 first latches the value '3' in the 33 initial value register, and the latch 40 latches the value '15' in the initial value register 43. The output of the latch 30 is also input to the 4-bit adder circuit 32, and is added to the output of the D latch 35 to output 4.
However, it is assumed that the value 1 is preset in the D latch 35 before the count is started. The value of the latch 30 is (4n
-1) The value is checked by the circuit whose output becomes logic 0 only when the detection circuit 34 has a value smaller than 1 by a multiple of 4. Here, in general, if one line has L pixels and n is a natural number larger than 1, then L / 2 · n−1, but in this embodiment, L = 8, so 4n−1.

Since the output of the latch 30 is now 3, the output of the detection circuit becomes 0. This value is input to the D latch 35.
The output of the adder 32 is input to the latch 30 through the MUX 31, and is latched at the next clock, and at the same time, the value 0 is latched in the D latch 35. The latch 30 outputs the just latched 4, and this value is added to the adder 32 and (4n-1).
It is input to the detection circuit 34. This 4 and D are added to the adder 32.
The output of the latch 35 is input. Since the output of the D latch 35 is 0, the output of the adder becomes 4 again. However, since the output of the (4n-1) detection circuit 34 is 1, this value is input to the D latch 35.

At the next clock, this 1 is sent to the D latch 35,
Further, 4 is latched by the latch 30. The D latch 30 outputs 4 again, but since the input of the adder, that is, the output of the D latch 35 is 1, the output of the adder 32 is 5. In this way, the count advances from 5 → 6 → 7, and when it reaches 7, the input of the D latch 35 becomes 0 again and the output to the adder becomes 0 at the next clock, so that 7 → 8 → 8. Count 4n (multiple of 4) twice. In this way, the latch 30 can output the count value shown in FIG.

Similarly, the latch 40 can output a value starting from the initial value 15. The adder 42 is a 4-bit (generally L / 2-bit adder for one line L pixel, so that 15 + 1 = 0. For these two count values, necessary values are selected and output by the MUX 52. This is output. If the output of the latch 30 is set to be output only when the latch 30 outputs the value of (4n-1), the count value (sequence) to be obtained can be output.

[0028]

As described above in detail, according to the present invention, the image processing capable of seamlessly supplying the image data of the overlapping portion to the respective processing devices by using only the memory chips corresponding to the divided screens. A device can be provided.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing a detailed configuration of the controller of FIG.

FIG. 3 is a diagram showing a configuration example of a pixel.

FIG. 4 is a diagram showing timing output of each address and latch.

FIG. 5 is a circuit configuration diagram for generating an address to be given to the 0-side and 1-side image memories.

FIG. 6 is a diagram showing a configuration of a 3 × 3 arithmetic circuit for an image using a line buffer.

FIG. 7 is a diagram showing a configuration of a latch group for generating data for 3 × 3 matrix calculation.

FIG. 8 is a diagram showing a latch and a value output from the latch.

FIG. 9 is a diagram for explaining an example of convolution calculation.

FIG. 10 is a diagram for explaining a method of parallel processing an image divided into two.

FIG. 11 is a diagram for explaining a problem of the conventional image processing apparatus.

[Explanation of symbols]

1, 2 ... Memory, 3 ... Controller, 4 ... Decoder, 5
... Data bus, 6 ... Address bus, 7,8 ... Chip select signal, 9,10 ... Output data bus, 11,12 ... Pixel data bus, 13,14 ... Address bus, 15,16
… Multiplexer.

Claims (1)

[Claims] 1. A plurality of storage means for respectively storing an image divided into a plurality of areas such that the areas are adjacent to each other, and the plurality of storage means for generating an independent address for each storage means. A plurality of address generating means provided for each of the plurality of address generating means, each of the plurality of address generating means successively generating addresses of other areas with respect to adjacent areas of the plurality of areas. apparatus.