JPH05151084A - Tlb entry clearing system - Google Patents

Abstract

PURPOSE:To clear a TLB entry into the other CPU by using the contents of a 1st STBR in a GOS run by sending out the contents of a 2nd STBR to the CPU as a key for TLB entry clearing when a TLB entry clear request is sent again to the CPU after a TLB entry clear request to the CPU is a failure. CONSTITUTION:Both CPUs 43 and 44 are each provided with the STBR 9 which indicates the head of the segment table in the CPU, the 2nd STBR 10 wherein the contents of the 1st STBR 9 are set when the TLB entry clear request is sent to the other CPU, and a TLB clear failure flag 11 which displays a failure of the TLB entry clear request sent to the other CPU and inhibits the contents from being set in the 2nd STBR 10. When the TLB entry clear request is sent again to the other CPU after the failure of the clear request, the contents of the 2nd STBR 10 are sent to the other CPU as the TLB entry clear key.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TLB (Address Translation Buffer) in a virtual computer system composed of a plurality of central processing units.
TL that clears the entry of (assideBuffer)
B entry clear method.

[0002]

2. Description of the Related Art Conventionally, a main memory unit (MMU) 41 and a system control unit (SCU) 4 as shown in FIG.
A virtual computer system as shown in FIG. 5 is realized by using a system composed of 2 and a central processing unit (CPU) 43, 44.

The virtual computer system shown in FIG. 5 is a host operating system (HO) for running a job.
S) 51 and jobs 65 running under the HOS 51
67 and multiple guest operating systems (GOS) running as one job under HOS 51
A virtual computer monitoring program (V
MCP) 52 and jobs 56 to 64 running under GOS 53 to 55.

By the way, in the virtual computer system as shown in FIG. 5, conventionally, when clearing the entry of the TLB, the following is done.

When the GOS 53 to 55 are running: The TLB entry is cleared by using the content of the segment table base register (STBR) as a key.

When the VMCP 52 is running ... Clears all TLB entries.

When the HOS 51 is running: The contents of STBR are used as keys to clear the TLB entry.

As described above, the HOS 51 and GOS 53 to 5
The reason for clearing the TLB entry by using the contents of STBR as a key during traveling of 5 is that the contents once registered in the TLB should be saved without being cleared as much as possible.

In a system including a plurality of CPUs 43 and 44, it may be necessary to clear the TLB entry of another CPU. At that time, if the system is not a virtual computer system, the content of STBR is only one in the system. Therefore, the content of STBR is not necessary as a key for clearing the TLB entry of another CPU.

On the other hand, when the system is a virtual computer system, the contents of STBR are the same between HOS and VMCP, different between HOS and GOS, and GOS.
-The contents of multiple STBRs exist at the same time in one system, since they differ between GOSs. That is, not all CPUs have the same STBR contents. Therefore, when clearing the TLB entry of the other CPU, it becomes necessary to use the contents of STBR of the own CPU as a key for the other CPU as well as to clear the entry of the TLB of the own CPU.

Now, for example, when the GOS is running, the T of another CPU is
If the attempt to clear the entry of the LB is unsuccessful, the control shifts to VMCP. Therefore, VMCP again issues a TLB entry clear request to another CPU instead of GOS. At this time, VMCP is
Clears all TLB entries without using the contents of BR as a key.

Therefore, the entry of the TLB registered by HOS is also cleared. Therefore, from VMCP to HO
When dispatched to a job under S, the job under the OS must perform address translation again using the address translation table. Eventually, GOS will adversely affect HOS.

It is assumed that the entry clear method of the TLB is changed and the contents of the STBR is used as a key when the VMCP is running. Then, the contents of STBR during VMCP running and the contents of STBR during HOS running are the same,
The entry of TLB will be cleared by using the contents of STBR during HOS running as a key. Therefore, GOS
Other CPU that uses the contents of STBR as a key when driving
TLB entry clear of will not be realized by VMCP.

[0014]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Since the entry clear method clears all TLB entries regardless of the contents of STBR during VMCP running, the TLB entry clearing to other CPUs performed during the running of jobs under GOS and GOS fails. Control shifts to VMCP, VMCP is TL of other CPU
When B entry is cleared, T registered by HOS
Even the entry of LB will be cleared, and H
There is a problem that a job under the OS has to perform address conversion using the address conversion table again.

An object of the present invention is to provide a GOS, GOS, even when the TLB entry of another CPU fails to be cleared and the control shifts to VMCP when a job under the GOS runs.
Another object of the present invention is to provide a TLB entry clear method capable of clearing TLB entries of other CPUs by using the contents of STBR when a job under GOS is running as a key.

[0016]

To achieve the above object, the present invention provides a virtual computer system realized by a system including a plurality of CPUs, wherein each CPU is its own CPU.
First STB indicating the beginning of the segment table in the
When the TLB entry clear request is issued to R and another CPU, the contents of the first STBR are set to the second.
STBR and that the TLB entry clear request made to another CPU has failed, and the second ST is displayed.
When a TLB entry clear request made to another CPU fails and a TLB entry clear request is made to the other CPU again after the TLB clear failure flag for inhibiting the setting to BR, the second STBR
The contents of the above are used as a key for clearing the TLB entry,
It is sent to U.

[0017]

When a certain CPU makes a TLB entry clear request to another CPU, the contents of the first STBR designating the beginning of the segment table are set in the second STBR.

When the TLB entry clear to the other CPU fails, the TLB clear failure flag in the certain CPU indicates that the TLB entry clear request made to the other CPU has failed, and the first STB
Prevents the contents of R from being set in the second STBR.

After that, the certain CPU is again activated by another CPU.
When making a TLB entry clear request to the other CPU, the contents of the second STBR are sent to the other CPU as a TLB entry clear key. At this time, the TLB clear failure flag indicates that the TLB entry clear request made to another CPU has failed, and the first STB
Since the contents of R are prevented from being set in the second STBR, the contents sent as the key to the other CPU are the first contents when the TLB entry clear request is first issued to the other CPU. It becomes the same as the contents of STBR.

[0020]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, showing a configuration example of the CPUs 43 and 44 shown in FIG.

The CPUs 43 and 44 include the address conversion unit 2 and
Arithmetic processing unit 3 and virtual address register (VAR) 4
And a real address register (RAR) 5.

The address conversion unit 2 includes an address conversion unit 7 for performing address conversion using an address conversion table,
Address conversion means 8 for performing address conversion using TLB, STBR 9, and output of address conversion means 8 when STLB hit signal 14 is output, and output of address conversion means 7 when not output. And a selector 15 for selecting.

The address conversion means 8 for performing the address conversion using the TLB comprises an STBR 10, a TLB clear failure flag 11, selectors 12 and 19, a TLB 13 and a clear logic section 16.

When the TLB entry clear request signal 18 is applied from the other CPU via the SCU 42, the selector 12 is applied by the other CPU via the SCU 42 to the other C.
The content 20 of STBR9 of PU is selected, and when that is not right, the content of STBR9 in the own CPU is selected.

The selector 19 uses the TLB clear failure flag 1
When 1 is set to ON and when the TLB entry clear request signal 18 is added from another CPU via the SCU 42, STBR 10 is selected, the TLB clear failure flag 11 is set to OFF, and the TLB entry clear request is made. STB if signal 18 is not applied
Select R9.

Normally, when performing memory access, VA
The virtual address stored in R4 is converted into a real address by the address conversion unit 2 and stored in RAR5. Then, the real address stored in RAR5 is SCU42.
Is supplied to the MMU 41 via the memory and memory access is performed.

The address translation unit 2 having the address translation means 7 for performing the address translation using the address translation table and the address translation means 8 for performing the address translation by using the TLB is the real address in the address translation means 8. Is obtained, the real address is stored in the RAR 5 via the selector 15. If the real address cannot be obtained by the address translation means 8, the real address obtained by the address translation means 7 is sent to the RAR 5 via the selector 15. Supply to.

FIG. 2 is a block diagram showing an example of the structure of the address conversion means 7 for performing the address conversion by the address conversion table, which is composed of a segment table 71 and a page table 72. In addition, in FIG.
The same reference numerals as in FIG.

When a virtual address composed of a segment number 4-1, a page number 4-2, and a displacement 4-3 is stored in VAR4, the segment table 71 whose head position is indicated by the contents of STBR 9 is displayed as the segment number 4-. 1
To be searched by. Further, the page table 7 is searched according to the search contents of the segment table 71 and the page number 4-2.
2 is searched. Then, the search contents of the page table 72 and the displacement 4-3 in the VAR 4 are the RAR as the page number 5-1 and the displacement 5-2, respectively, which form the real address.
Stored in 5.

Further, the address translation means 8 for performing the address translation by TLB adds the segment number 4-to VAR4.
When a virtual address composed of 1, page number 4-2 and displacement 4-3 is set, the TLB 13 is set based on the virtual address set in VAR 4 and the contents of STBR 9.
The actual address is output by searching for.

Each entry of the TLB 13 is, for example, as shown in FIG.
, V bit 13 indicating whether the entry is valid or invalid
-1, virtual space number (WSQ) 13-2, virtual page number 13-3, STBR value 13-4, page number 13-
5, a flag 13-6 indicating the attribute of the page to be accessed.

That is, the address converting means 8 is the TLB 13
In the case where the STBR value 13-4 is the same as the content of STBR9 and the virtual page number 13-3 is the same as the page number 4-2 set in VAR4, the entry from the TLB 13 is changed to that entry. The stored page number 13-5 and the displacement 4-3 set in VAR4 are output, and further the TLB hit signal 14 is output.

When the TLB hit signal 14 is output, the selector 15 selects the real address composed of the page number 13-5 and the displacement 4-2 output from the TLB 13 and sets it in the RAR 5, and the TLB hit signal is output. When 14 is not output, the real address output from the address conversion means 7 is set in RAR5.

Next, using the system shown in FIG.
TL in the case of configuring the virtual computer system shown in
The operation for clearing the entry of B13 will be described.

First, the CPUs 43 and 44 are T
The operation when clearing the entry of the LB 13 will be described.

At this time, the CPUs 43 and 44 supply the contents of the STBR 9 in their own CPUs to the clear logic unit 16 via the selector 19. The clear logic unit 16 is STBR
When the contents of 9 are added, the entries of the TLB 13 are read one by one, and the STBR value 13 of the read entry is read.
If -4 matches the contents of STBR 9, the entry is cleared by invalidating the V bit 13-1 of that entry.

Next, the CPU 43 makes the TLB of the other CPU 44
The operation for clearing the 13 entries will be described.

When the CPU 43 clears the entry of the TLB 13 in the CPU 44, the CPU 43 sends the CPU through the SCU 42.
The TLB entry clear request signal 18 and the output 21 of the selector 19 are supplied to 44. At this time, the TLB clear failure flag 11 is not set to ON, and the CPU 4
Since the TLB entry clear request signal 18 from 4 is not added, the output 21 of the selector 19 indicates the contents of STBR 9. At this time, the contents of STBR 9 are set in STBR 10 via selector 12.

The selector 12 in the CPU 44 is the CPU 43.
When the TLB entry clear request signal 18 is added from ST, the ST in the CPU 43 added via the SCU 42.
Select the content 20 of BR9 and set it in STBR10. S in the CPU 43 set in STBR10
The content 20 of the TBR 9 is added to the clear logic unit 16 via the selector 19. The clear logic unit 16 in the CPU 44 clears the entry of the TLB 13 by using the contents of the added STBR 9 in the CPU 43 as a key.

Next, the CPU 43 sends a T to the CPU 44.
Although the entry clearing of the LB 13 is requested, the CPU 44 is also in the process of clearing the entry of the TLB 13 in its own CPU, so the operation when the entry clearing of the TLB 13 of the CPU 44 fails will be described.

If the system as shown in FIG. 4 realizes the virtual computer system as shown in FIG.
CP52 is one job under HOS51. Therefore, the contents of STBR when the VMCP 52 is running are HOS5.
This is the same as the content of STBR when running 1. On the other hand, GO
S53 to S55 are OSs different from the HOS 51. Therefore, the contents of STBR during running of GOS 53-55 and jobs 56-64 under GOS 53-55 are different from the contents of STBR during running of HOS 51 and VMCP 52.

From the above, in the system shown in FIG.
A virtual computer system as shown in FIG. 5 is realized, and one of the CPUs 43 and 44 runs GOS 53 to 55 under VMCP 52 or jobs 56 to 64 under GOS 53 to 55, and runs jobs under HOS 51 on the other. When 65 to 67 are running, S of CPU43,44
The contents of TBR 9 are different from each other.

Now, the following assumptions are made.

(1) In the CPU 43, the job 56 under the GOS 53 is running. (2) In the CPU 44, the job 65 under the HOS 51 is running. (3) The TLB entry clear request signal 18 is output from the CPU 43 to the CPU 44, but the CPU 44 is also clearing the entry of the TLB 13 in its own CPU.
It is assumed that the clear success failure signal 17 is used to notify the requesting CPU 43 that the TLB entry cannot be cleared.

When the requesting CPU 43 receives the TLB clear success failure signal 17 indicating that the TLB entry cannot be cleared from the CPU 44 through the SCU 42, the TL
The B clear failure flag 11 is set to ON. The TLB clear failure flag 11 set to ON is STBR10.
To set to. Therefore, even if the control shifts from the job 56 under the GOS 53 to the VMCP 52 and the contents of the STBR 9 in the CPU 43 change, the contents of the STBR 10 are guaranteed to the contents when the job 56 is running.

When the CPU 44 receives a TLB entry clear success / failure signal 17 indicating that the TLB entry cannot be cleared, the CPU 43 shifts the control from the job 56 to the VMCP 52, and the VMCP 52 again passes through the SCU 42. The TLB entry clear request signal 18 and the output of the selector 19 are transmitted to the CPU 44.
In this case, the TLB clear failure flag 11 in the CPU 43
Is set to ON, the selector 19 holds the contents of STBR 9 when running job 56.
The content of 10 will be selected. So in this case,
The CPU 44 is supplied with the TLB entry clear request signal 18 and the contents of the STBR 9 during running of the job 56 held in the STBR 10 via the SCU 42. Further, the clear logic unit 16 in the CPU 43 clears the TLB 13 entry in the CPU 43 in the same manner as described above by using the output 21 of the selector 19, that is, the content of the STBR 9 held in the STBR 10 during the traveling of the job 56 as a key.

TLB from CPU43 via SCU42
The CPU 44, to which the contents of the STBR 9 during the traveling of the job 56 held in the entry clear request signal 18 and the STBR 10 is sent, sets the contents of the sent STBR 10 in the STBR 10 in the own CPU 44. CPU
The clear logic unit 16 in 44 is a T from another CPU 43.
When the LB entry clear request can be accepted, the entry of the TLB 13 is cleared using the contents of the STBR 10 as a key.

When the entry clear of the TLB 13 is successful, the CPU 44 sends S to the requesting CPU 43.
TL indicating successful clearing of TLB entry via CU42
The B clear success failure signal 17 is output.

The requesting CPU 43 receives a TLB entry clear success from the CPU 44 via the SCU 42.
When the clear success failure signal 17 is sent, the TLB clear failure flag 11 is set to OFF. The TLB clear failure flag 11 set to OFF controls the selector 19 to input STBR as an input to the clear logic unit 16.
Select 9.

[0051]

As described above, according to the present invention, the CP
First ST indicating the beginning of the segment table in U
BR, the second STBR in which the content of the first STBR is set when a TLB entry clear request is made to the other CPU, and the failure of the TLB entry clear request made to the other CPU causes the first STBR to be cleared. TL that prevents the contents of the STBR of the second STBR from being set to the second STBR
A B clear failure flag is provided, and when a job under GOS or GOS is running, a TLB entry clear request to another CPU fails and control shifts to VMCP.
When P again makes a TLB entry clear request to another CPU, another C is used by using the contents of the first STBR at the time of running GOS held in the second STBR by VMCP.
Since the TLB entry of the PU can be cleared, there is an effect that the entry of the TLB registered by the HOS is not cleared as in the conventional example.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of an address conversion means 7 using an address conversion table.

FIG. 3 is a diagram showing a configuration example of one entry of the TLB 13.

FIG. 4 is a block diagram showing a configuration example of a system used in the present invention.

5 is a block diagram showing a configuration example of a virtual computer system realized on the system shown in FIG.

[Explanation of symbols]

2 ... Address conversion unit 3 ... Arithmetic processing unit 4 ... Virtual address register (VAR) 5 ... Real address register (RAR) 7 ... Address conversion means using address conversion table 8 ... Address conversion means using TLB 9, 10 ... Segment table base register (STB
R) 11 ... TLB clear failure flag 12, 15, 19 ... Selector 13 ... Address translation buffer (TLB) 16 ... Clear logic unit 41 ... Main memory unit (MMU) 42 ... System computer unit (SCU) 43, 44 ... Central processing Device (CPU) 51 ... Host operating system (HOS) 52 ... Virtual computer monitoring program (VMCP) 53-55 ... Guest operating system (GO)
S) 56 to 67 ... Job 71 ... Segment table 72 ... Page table

Claims (3)

[Claims] 1. A virtual computer system realized by a system including a plurality of CPUs, wherein each CPU designates a head of a segment table in its own CPU.
STBR of the second S and the second S in which the contents of the first STBR are set when a TLB entry clear request is issued to another CPU.
A TLB entry made to another CPU, comprising a TBR and a TLB clear failure flag indicating that the TLB entry clear request made to another CPU has failed, and inhibiting the setting to the second STBR. When the TLB entry clear request is made again to the other CPU after the clear request fails, the contents of the second STBR are sent to the other CPU as a TLB entry clear key. Clear method. 2. The virtual computer system includes an HOS that runs a normal job and a plurality of GOSs that run as one job under the HOS.
2. The T according to claim 1, wherein a VMCP that runs an OS and the GOS that runs under the VMCP and runs a normal job run.
LB entry clear method. 3. The CPU, when clearing the entry of the TLB in its own CPU, uses the contents of the first STBR in the CPU as a key to clear the entry of the TLB. TLB entry clear method.