JP2000020399A - Virtual computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To instantaneously judge whether the address buffer entry of a virtual machine on an OS issuing a purge address buffer instruction is to be invalidated or not by operating a flag for discriminating whether the virtual machine exists on the OS or not by an instruction for starting up the virtual machine. SOLUTION: At the time of executing an instruction (SIE instruction) for starting a virtual machine which is issued from a real machine of a level 1 OS, a level 2 validation flag 101 for deciding whether a virtual machine to be a level 2 OS exists or not is validated in a level 1 OS identification entry 100. When the operand address (SP address) of the SIE instruction does not coincide with the SP address 113 of all level 2 OS identification entries 110 validating the virtual machine identification code (VMID) validation flag 112 indicating the validity of the VMID of the virtual machine, the VMID of the virtual machine, the SP address of the SIE instruction and the VMID validation flag 112 are registered in a new level 2 OS identification entry 110.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a virtual machine system, and more particularly, to a TLB control method in a virtual machine system suitable for efficiently controlling a virtual machine using an address translation buffer (TLB).

[0002]

2. Description of the Related Art Conventionally, a virtual machine control program (Virtual Machine C) is executed on a single real machine.
A virtual computer system is known in which a virtual computer system (hereinafter, abbreviated as "VMCP") is operated to construct a plurality of virtual computers under the control of the VMCP.

In general, in an information processing apparatus using a virtual storage system, a logical address specified when a virtual computer accesses an instruction or data on the virtual storage is assigned to a logical address on a main storage provided in the real computer. It must be converted to an absolute address (hereinafter referred to as "physical address"). Therefore, in the above-described conventional virtual computer system, the VMCP operating on the real computer (hereinafter referred to as “level 1”)
OS ”) is an address translation table (hereinafter“ Level 1 translation ”) showing a correspondence between a logical address (hereinafter,“ Level 1 logical address ”) and a physical address in a virtual address space on the level 1 OS. In addition to generating a virtual address space by managing a table “described”, an OS of a lower-level virtual machine (hereinafter referred to as “level 2 OS”) operates on the virtual address space in the level 1 OS. The level 2 OS is an address conversion table (hereinafter, referred to as “level 2 OS”) indicating a correspondence between a logical address (hereinafter referred to as “level 2 logical address”) in a virtual address space on the level 2 OS and a level 1 logical address. Conversion table "
) To generate a virtual address space. That is, in order to convert between a level 2 logical address and a physical address, it was necessary to perform address conversion using two sets of address conversion tables, a level 1 conversion table and a level 2 conversion table.

In recent years, level 1 OS (VMC)
Level 2 OS which is a virtual machine operating under the control of P)
Level 2 by using VMCP as a kind of
A technique for further operating a virtual machine, that is, a level 3 OS under the control of the OS (VMCP) is disclosed in, for example, Japanese Patent Laid-Open No.
This is disclosed in Japanese Patent No. 5642.

In the virtual machine system disclosed in Japanese Patent Application Laid-Open No. 7-84884, an address translation buffer (hereinafter referred to as "
TLB "), the address translation information is converted to level 10
S, by adding a virtual machine identifier (hereinafter referred to as “VMID”) for identifying which one of the level 2 OS or the level 3 OS is related, T
Level 1 OS, Level 2 OS and Level 30 on LB
S entries can be held at the same time.

[0006]

When the OS invalidates all address translation information relating to the OS, the TL
A purge TLB command (hereinafter referred to as a “PTLB” command) for invalidating all entries registered in B is issued. At this time, the PTLB instruction was issued at level 3
In the case of the OS, only the entry corresponding to the level 3 OS on the TLB is invalidated. If the PTLB instruction is issued by the level 2 OS and the level 3 OS exists on the level 2 OS, the entry corresponding to the level 2 OS and the entry corresponding to the level 3 OS on the TLB must be invalidated. This is because the address conversion information indicating the individual correspondence between the level 3 logical address and the physical address is:
The virtual machine is generated with reference to the level 1 translation table, the level 2 translation table, and the level 3 translation table. Therefore, if the level 2 logical address is invalidated, the virtual computer in the level 3 OS which is a virtual machine operating under the control of the level 2 OS is generated. This is because the level 3 logical address indicating the address space must also be invalidated. When the PTLB instruction is issued at the level 1 OS and the level 2 OS exists on the level 1 OS, the level 10 OS on the TLB is also used for the above reason.
The entry corresponding to S and the entry corresponding to the level 2 OS must be invalidated.

In the above-described virtual machine system disclosed in JP-A-7-84884, a VM is used as means for determining whether or not a virtual machine exists on the OS that has issued the PTLB instruction.
A configuration is provided in which a plurality of sets of identification information entries each consisting of an ID and its execution level are held. For example, when the OS that issued the PTLB instruction is the level 2 OS, there is at least one entry whose execution level of the identification information entry is the level 3 OS. It is determined whether a virtual machine exists on the OS that has issued the PTLB instruction. That is, if the level 3 OS does not exist, it is necessary to determine all the execution levels of a plurality of sets of identification information entries.

In the above virtual computer system, the TLB
As a means for invalidating a TL that matches the VMID selected by the TLB control device and the VMID of the TLB entry.
B entry can be invalidated. For example, when the OS that issued the PTLB instruction is the level 2 OS, the TL in which the VMID of the execution level is the level 2 OS and the level 3 OS is present
All B entries must be invalidated.

Further, in a multiprocessor configuration, an instruction to invalidate TLB entries of all the central processing units configured, for example, a CSP instruction (Compare S)
The processing in the case where a “wap and purge instruction” is issued has not been considered in the virtual computer system. For example, the virtual computer system includes communication means for directly transmitting and receiving information between the central processing units,
Even if an identification information entry composed of two persons having the same execution level is communicated to the other central processing unit via the communication means, the information identification entry is generated independently by each central processing unit. Even with the VMID, it cannot be specified as the same virtual machine. As a result, in the PTLB processing of the central processing unit that receives the information identification entry,
As a result, all TLB entries are invalidated, including TLB entries that do not need to be invalidated.
This leads to a significant decrease in the usage efficiency of B, and is a problem that cannot be ignored in the performance of the virtual machine system.

[0010] A first object of the present invention is to provide a flag for identifying whether a virtual machine exists on the currently running OS, so as to execute a process related to the TLB such as the PTLB instruction. It is an object of the present invention to provide a virtual machine system capable of instantaneously determining whether to invalidate a TLB entry of a virtual machine on an OS that has issued an instruction by using the flag.

[0011] A second object of the present invention is to execute a process relating to the TLB such as the PTLB instruction in a local central processing unit which requests the instruction, when the VM of each virtual machine is executed.
By performing control so that the ID does not match the VMID of the TLB entry, the VMID and TL selected by the TLB control device can be used without actually invalidating the TLB entry.
It is an object of the present invention to provide a virtual machine system capable of obtaining the same effect as invalidating a TLB entry without using a configuration that can invalidate a TLB entry that matches a VMID of a B entry.

A third object of the present invention is to directly transfer information between central processing units when executing an instruction accompanied by invalidation of the address translation buffers of all the central processing units in a multiprocessor configuration. Communication means to perform;
Means for transmitting the execution level identification information of the OS that issues the instruction to the other central processing unit via the communication unit, so that the execution level of the OS that issues the instruction in all the central processing units can be changed. It is to provide a virtual computer system that can be recognized.

[0013] A fourth object of the present invention is to provide a method for invalidating, based on the OS execution level identification information, when a process relating to a TLB such as a PTLB instruction is executed in another central processing unit which requires the instruction. Since it is possible to determine whether the TLB entry needs to be performed, it is possible to omit the process of invalidating an extra TLB entry. If invalidation processing is required, the execution level of the OS that issues the instruction is determined based on the OS execution level identification information without actually invalidating the TLB entry,
By performing control so that the VMID of each virtual machine does not match the VMID of the TLB entry, a virtual machine system that can achieve the same effect as invalidating the TLB entry without actually invalidating the TLB entry is provided. To provide.

[0014]

(1) To achieve the above object, the present invention provides two or more central processing units provided with a plurality of virtual machines, and a main memory shared by each of the virtual machines. A device, a logical address when each virtual machine has accessed the main storage device in the past, an absolute address corresponding to the logical address, a virtual machine identification code assigned to the virtual machine of the access source, and an execution level identification of the virtual machine A virtual computer system including a plurality of entries for storing a plurality of sets of information as one set, and an address translation buffer for translating a logical address to an absolute address by referring to the entry when each virtual machine accesses the main storage device , The execution level identification information is a level 1 OS
A level 1 OS identification entry consisting of a virtual computer identification code of the real computer and a flag for identifying whether a virtual computer that is a level 2 OS exists on the real computer, and an execution level of the virtual computer For each virtual machine whose identification information is level 2OS, a virtual machine identification code of the virtual machine, an operand address of an instruction for starting the virtual machine, a flag indicating the validity of the virtual machine identification code of the virtual machine, and the virtual machine A level 2 OS identification entry made up of four flags for identifying whether a virtual machine that is a level 3 OS exists on the computer, and the execution level identification information of the virtual machine is a level 3 OS
For each of the virtual machines, a level 3 OS identification consisting of a virtual machine identification code of the virtual machine, an operand address of an instruction for starting the virtual machine, and a flag indicating the validity of the virtual machine identification code of the virtual machine. Means for validating a flag for identifying whether there is a virtual machine which is a level 2 OS of the level 1 OS identification entry when executing an instruction for starting a virtual machine issued by a real computer of the level 1 OS; If the operand address of the instruction does not match the operand address of any level 2 OS identification entry for which the flag indicating the validity of the virtual computer identification code of the virtual computer is valid, the virtual computer identification code of the virtual computer and the virtual computer Address and virtual machine identification code of the instruction that invokes Means for registering a flag indicating validity to a new level 2OS identification entry level 2OS
Executing the instruction for starting the virtual machine issued by the real machine of
Means for enabling a flag for identifying whether or not a virtual machine which is S exists; and for all level 3 OS identification entries for which the operand address of the instruction and the flag indicating the validity of the virtual machine identification code of the virtual machine are valid. If the operand addresses do not match, the virtual machine identification code of the virtual machine, the operand address of the instruction for starting the virtual machine, and a flag indicating the validity of the virtual machine identification code of the virtual machine are added to the new level 3 OS identification entry. And a registration means.

(2) In addition to the configuration of (1), in executing the processing in the own central processing unit of the instruction accompanied by invalidation of the address translation buffer issued by the real computer of the level 1 OS, the real computer has a new configuration. The virtual computer identification code of the real computer is stored, and if the flag for identifying whether a virtual computer that is a level 2 OS exists on the real computer is valid, all the level 2 OS identification entries are referred to and the level 2 OS identification is referred to. If there is an entry for which the validity flag of the virtual machine identification code of the entry is valid, the flags of all valid entries are invalidated, and the flag for identifying whether a virtual machine which is a level 3 OS exists is valid. When a certain entry exists, all the level 3 OS identification entries are referred to, and the virtual computer ID of the level 3 OS identification entry is referred to. If there is an entry for which the code validity flag is valid, the flag of all valid entries is invalidated, and the local central processing unit of the instruction accompanied by invalidation of the address translation buffer issued by the virtual machine of the level 2 OS In executing the processing in the above, when the virtual machine identification code of the new virtual machine is stored in the virtual machine, and the flag for identifying whether the virtual machine which is the level 3 OS exists on the virtual machine is valid, With reference to the level 3 OS identification entry, if there is an entry in which the validity flag of the virtual machine identification code of the level 3 OS identification entry is valid, the flags of all valid entries are invalidated, and the level 3 OS virtual machine Execution of processing in the local central processing unit of an instruction accompanied by invalidation of an address translation buffer to be issued Per, in which as the may be stored the virtual machine identification code of the new virtual machine to the virtual machine, not coincide with the virtual computer identification codes of all the address translation buffer entries.

(3) Communication means for directly transmitting and receiving information between the central processing units, and in a multiprocessor configuration, instructions for invalidating address translation buffers of all the configured central processing units. Upon execution, means for transmitting execution level identification information of the OS issuing the command to the other central processing unit via the communication means is provided.

(4) In addition to the configuration of (1), in addition to the instruction issued by the computer of each level OS and accompanied by invalidation of the address translation buffer, the CPU is currently running in executing the processing in the central processing unit. A new virtual machine identification code is stored in the computer of the level, and when the execution level identification information of the OS transmitted by the communication means is the level 1 OS, all the level 2 OS identification entries and the level 3 identification entries are stored. If there is an entry for which the validity flags of the virtual machine identification codes of the level 2 OS identification entry and the level 3 OS identification entry are valid, the flags of all valid entries are invalidated and transmitted by the communication means. If the execution level identification information of the OS is level 2 OS, all the level 2 OS identification entries and level Referring to identify entry level 2
When there is an entry in which the validity flags of the virtual machine identification codes of the OS identification entry and the level 2 OS identification entry are valid, the flags of all valid entries are invalidated, and the execution of the OS transmitted by the communication means is executed. If the level identification information is level 3 OS, all level 3
With reference to the OS identification entry, if there is an entry where the validity flag of the level 2 OS identification entry and the virtual machine identification code of the level 2 OS identification entry is valid, the flags of all valid entries are invalidated, and all the valid entries are invalidated. This does not match the virtual machine identification code of the address translation buffer entry.

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the virtual machine system of the present invention will be described in detail with reference to some drawings.

FIG. 1 is a functional block diagram showing the configuration of one embodiment of the virtual machine system of the present invention.

(Embodiment 1) In FIG. 1, reference numeral 100 denotes a level 1 OS identification entry.
Level 20 for identifying whether there is a virtual machine that is S
It is composed of an S valid flag 101 and the VMID 102 of the real computer. Reference numeral 103 denotes a level 1 OS identification entry stack, which is composed of a set of level 1 OS identification entries 100.

Reference numeral 110 denotes a level 2 OS identification entry, which is a level 3 OS valid flag 111 for identifying whether a virtual machine which is a level 3 OS exists on the virtual machine, a VMID valid flag 112 indicating validity of the VMID of the virtual machine, and An instruction to start the virtual machine (hereinafter “SI
An E-instruction "is described. The operand address 113 (hereinafter, referred to as" SD address ") and the VMID 114 of the virtual machine. Reference numeral 115 denotes a level 2 OS identification entry stack. Consists of

Reference numeral 120 denotes a level 3 OS identification entry, which is a VMID valid flag 121 indicating the validity of the VMID of the virtual machine, and an SD of an SIE instruction for starting the virtual machine.
It comprises an address 122 and a VMID 123 of the virtual machine. Reference numeral 124 denotes a level 3 OS identification entry stack, which comprises a plurality of sets of level 3 OS identification entries 120. Reference numeral 125 denotes a group of level 3 OS identification entry stacks. It comprises an identification entry stack 124.

Reference numeral 130 denotes a level 2 OSSD address register that is set when an SIE instruction for activating a level 2 OS is provided, and 131 is a level 3 OSSD address register that is set when an SIE instruction for activating a level 3 OS is performed.

The AND gate 140 is an AND gate that takes the logical product of the VMID valid flag 112 and the SD address 113, and the AND gate 141 is the AND gate that takes the logical product of the VMID valid flag 121 and the SD address 122.

The comparator 150 is a data comparator for comparing the value of the level 2 OSSD address register 130 with the data sent from the AND gate 140.
Reference numeral 51 denotes a data comparator for comparing the value of the level 3 OSSD address register 131 with the data sent from the AND gate 141.

The MAXVMID register 160 stores the VMI
A register that holds the maximum value of D, and an adder 170 is an adder that adds 1 to the value of the MAXVMID register 160.

The selector 180 is a selector for selecting and sending the value of the MAXVMID register 160 and the value of the VMID 114 by a hit signal indicating a data comparison match sent from the comparator 150, and sending the selected value.
This selector selects the value of the MAXVMID register 160 and the value of the VMID 14 based on a hit signal indicating a data comparison match transmitted from the comparator 151, and transmits the same.

The OS level register 27 stores the running O
This register holds the S level.

The selector 28 converts the data sent from the selector 25 and the data sent from the selector 26 into O
This is a selector that selects and sends out according to the value of the S level register.

192 is an address translation buffer (TLB)
It is.

The VMID register 193 stores the TLB 192
This is a register for holding a VMID used for registration of HIT and HIT determination.

FIG. 2 is an explanatory diagram showing the processing of the SIE instruction in the virtual machine system of FIG.

(1) When the OS that issued the SIE instruction is the level 1 OS. In this case, the OS level register 1
Since 1 (level 1 OS) is set in 90, the process branches from step 200 to step 201. In step 201, the SD address of the SIE instruction is
Set in the SD address register 130.

In step 202, 2 (level 2 OS) is set in the OS level register 190.

Further, in step 203, level 10
Of the S identification entries 100, the level 20
Level 20 for identifying whether there is a virtual machine that is S
“1” is registered in the S valid flag 101.

In step 204, processing is performed to determine whether a valid VMID exists. The SD address 113 of the level 2 OS identification entry 110 existing in the level 2 OS identification entry stack 115 and the level 2 OSS
The value set in the D address register 130 is compared by the comparator 150. As for the SD address 113 sent to the comparator 150, only the SD address 113 whose VMID valid flag 112 of the same level 2 OS identification entry 110 is 1 is sent out by the AND gate 140. The comparator 150 compares the SD address 113 with the value set in the level 2 OSSD address register 130 to identify whether there is a valid level 2 OS identification entry 110 of the virtual machine activated by the SIE instruction, Branch according to this result.

When no valid level 2 OS identification entry 110 exists. In this case, the process branches from step 204 to step 205. In step 205, the SIE
Since there is no valid level 2 OS identification entry 110 of the virtual machine activated by the instruction, new registration processing of the level 2 OS identification entry 110 is performed. The level 3OS valid flag 111 is registered as 0 because there is no level 3OS. The SD address 113 has a level 2
The value of the OSSD address register 130 is set. The value obtained by adding 1 to the value of the MAXVMID register 160 output by the adder 170 is selected by the selector 180, and 2 (level 2OS) is set in the OS level register 190. The value obtained by adding 1 to 1 is selected by the selector 191, and this value is registered in the VMID 114. Further, the VMID valid flag 112 is registered as 1.

In step 206, the value of the MAXVMID register 160 and 1
Is updated in the VMID register 193.

In step 207, the process of updating the MAXVMID is performed, and the MAX
By the value obtained by adding 1 to the value of the VMID register 160,
The MAXVMID register 160 is updated.

When a valid level 2 OS identification entry 110 exists. In this case, the process branches from step 204 to step 208. In step 208, since there is a valid level 2 OS identification entry 110 of the virtual machine activated by the SIE instruction, continuation control processing of the matched level 2 OS identification entry 110 is performed. VMID1
Since 14 is selected by the selector 180 and 2 (level 2 OS) is set in the OS level register 190, the VMID 114 value is selected by the selector 191 and the VMID register 193 is updated with this value.

The OS that issued the SIE instruction is a level 3 OS
If it was. In this case, since 2 (level 2 OS) is set in the OS level register 190, the process branches from step 200 to step 211.

In step 211, the SD address of the SIE instruction is set in the level 3 OSSD address register 131.

In step 212, 3 (level 3 OS) is set in the OS level register 190.

In step 213, of the level 2 OS identification entry 110 of the level 2 OS that has issued the SIE instruction, the level 3 OS valid flag 111 for identifying whether or not a virtual machine which is a level 3 OS exists on the virtual machine is set to 1
Register

In step 214, processing is performed to determine whether a valid VMID exists. The level 3 OS identification entry stack 115 corresponding to the level 2 OS identification entry 110 of the level 2 OS that issued the SIE instruction is:
SD address 1 of the level 3 OS identification entry 120 selected from the level 3 OS identification entry stack group 125 and existing in the level 3 OS identification entry stack 115
22 is compared with the value set in the level 3 OSSD address register 131 by the comparator 151. The SD address 122 sent to the comparator 151 is A
The ND gate 141 sends out only the SD address 122 in which the VMID valid flag 121 of the same level 3 OS identification entry 120 is 1. The comparator 151 uses the SD address 122 and the level 3 OSSD address register 131
By comparing the values set in the SIE instruction, it is determined whether there is a valid level 3 OS identification entry 120 of the virtual machine activated by the SIE instruction, and the process branches according to the result.

When no valid level 3 OS identification entry 120 exists. In this case, the process branches from step 214 to step 215. In step 215, the SIE
Since there is no valid level 3 OS identification entry 120 of the virtual machine activated by the instruction, new registration processing of the level 3 OS identification entry 120 is performed. SD address 1
In 22, the value of the level 3 OSSD address register 131 is set. M output from the adder 170
Since a value obtained by adding 1 to the value of the AXVMID register 160 is selected by the selector 181, and 3 (level 3 OS) is set in the OS level register 190, a value obtained by adding 1 to the value of the MAXVMID register 160 is used as the selector. 191 and this value is
Register at 114. Further, the VMID valid flag 121 is registered as 1.

At step 216, the value of the MAXVMID register 160 and 1
Is updated in the VMID register 193.

At step 217, the process of updating the MAXVMID is performed, and the MAX
By the value obtained by adding 1 to the value of the VMID register 160,
The MAXVMID register 160 is updated.

When a valid level 3 OS identification entry 120 exists. In this case, the process branches from step 214 to step 218. In step 218, since there is a valid level 3 OS identification entry 120 of the virtual machine activated by the SIE instruction, continuation control processing of the matching level 2 OS information identification entry 120 is performed. VMID
123 is selected by the selector 181, and since 3 (level 3 OS) is set in the OS level register 190, the VMID 123 value is selected by the selector 191 and the VMID register 193 is updated with this value.

FIG. 3 is an explanatory diagram showing the processing of the PTLB of the own central processing unit in the virtual computer system of FIG. When the PTLB processing is issued, at step 300, O
The S level register 190 identifies the current OS level, that is, the OS level that issues the PTLB process,
Branch according to the level.

The OS that has issued the PTLB processing is level 10
If S. In this case, the process branches from step 300 to step 311. Level 3 in step 311
Reference is made to the level 1 OS identification entry 100 in the OS identification entry stack 103. In step 312, the process branches depending on the value of the level 2 OS valid flag 101 in the entry.

When the level 2 OS valid flag 101 is 0. In this case, the process branches from step 312 to 320.

When the level 2 OS valid flag 101 is 1. In this case, the process branches from step 311 to 330. In step 330, a plurality of level 2 OS identification entries 1 in the level 2 OS identification entry stack 115
10 and the VMID valid flag 11 in the same entry.
The VMID is invalidated (valid flag 7 is set to 0) for all entries in which 2 is 1.

In step 331, a plurality of level 2 OS identification entries 110 in the level 2 OS identification entry stack 115 are referred to.

In step 332, the process branches depending on the value of the level 3 OS valid flag 11 in the entry.

When all the level 3 OS valid flags 111 are 0. In this case, the process branches from step 332 to 320.

When the level 3 OS valid flag 111 is not all 0s. In this case, the process branches from step 332 to 340. In step 340, the level 3 OS identification entry stack 124 corresponding to the level 2 OS identification entry 110 whose level 3 OS valid flag is 1 is set to level 3
Select from the OS identification entry stack group 125.

At step 341, the selected level 3
Multiple levels 3 in OS identification entry stack 124
Referring to the OS identification entry 120, the VM in the entry is referred to.
VMID invalidation processing for all entries whose ID valid flag 121 is 1 (valid flag 12 is set to 0)
I do.

The OS that has issued the PTLB processing is level 20
If S. In this case, the process branches from step 300 to step 350. In step 350, level 2
Reference is made to the level 2 OS identification entry 120 of the currently running OS in the OS identification entry stack 115.

In step 351, the process branches according to the value of the level 3 OS valid flag 111 in the entry.

When the level 3 OS valid flag 111 is 0. In this case, the process branches from step 351 to step 320.

When the level 3 OS valid flag 111 is 1. In this case, the process branches from step 351 to 360.

In step 360, the currently running O
Referring to a plurality of level 3 OS identification entries 120 in the level 3 OS identification entry stack 124 corresponding to the level 2 OS identification entry 120 of S, the V in the entry is referred to.
The VMID invalidation process (sets the validity flag 7 to 0) is performed for all entries whose MID validity flag 112 is 1.

The OS that has issued the PTLB processing is level 30
If S. In this case, the process branches from step 300 to step 320.

At step 320, the VMID in the OS identification entry is updated. When the OS level register 190 is at level 1 OS, the VMID 102 is updated by the value obtained by adding 1 to the value of the MAXVMID register 160, and the level 2 OS is updated. At the time, the VMID 114 is updated, and at the time of the level 3 OS, the VMID 123 is updated.

In step 321, the VMID register 1
93 is updated, and the MAXVMID register 16
The value obtained by adding the value of 0 and 1 to the VMID register 19
3 is updated. After that, TLB192 registration and HI
The updated value of the VMID register 193 is used for the T determination.

At step 322, the process of updating the MAXVMID is performed, and the MAX
By the value obtained by adding 1 to the value of the VMID register 160,
The MAXVMID register 160 is updated.

As described above, in this embodiment,
A flag for identifying whether a virtual machine exists on the OS is set to S
Since the operation is performed by the IE instruction, when the processing related to the TLB such as the PTLB instruction is executed, the flag is used to instantaneously determine whether to invalidate the TLB entry of the virtual machine on the OS that has requested the PTLB processing. Can be determined.

When processing relating to the TLB such as the PTLB instruction is executed in the local central processing unit, control is performed so that the VMID of the virtual machine does not match the VMID of the TLB entry, even if the instruction is executed on any level of OS. By doing so, V selected by the TLB control device
Even if the TLB entry that matches the MID and the VMID of the TLB entry is not invalidated,
An effect equivalent to invalidating the TLB entry can be obtained without invalidating the entry.

(Embodiment 2) Next, an embodiment of the virtual computer system of the present invention in a multiprocessor configuration will be described in detail with reference to some drawings.

FIG. 4 is a diagram showing an apparatus configuration in a multiprocessor configuration. Although the example of FIG. 4 is a configuration example of three CPUs, a configuration of four or more CPUs or a configuration of less than three CPUs may be employed. In FIG. 4, CPUs A 401 and C
The PUA 402 and the CPU C 403 can mutually exchange information between the CPUs via a signal line 400.

Information transmitted and received via the signal line 400 includes:
PTLB processing start request, waiting state release instruction request information to the partner CPU, request acceptance report information as a response from the partner CPU, and the CPU that issued the PTLB processing start request
, Etc. of the OS level register 190.

Hereinafter, the CPUs A 401 and CPs in FIG.
A normal information exchange method between the UB 402 and the CPU C 403 will be described in detail with reference to FIG.

FIG. 5 is a flowchart showing a processing procedure for a method of transmitting and receiving information between CPUs.

At step 501, CPU A 401
When requesting a PTLB process from the PUB 402 and the CPU 403, the CPU A 401
A request for starting the PTLB process and the contents of the OS level register 190 are sent to the device 3 via the signal line 400.

In step 503, the CPU A 401
The process enters a wait state until a report signal indicating that the requested operation has been completed from the CPUB 402 and the CPUC 403 is returned via the signal line 400.

In steps 511 and 521,
When receiving the PTLB process activation request from the CPU 401 via the signal line 400, the CPUB 402 and the CPUC 403 temporarily suspend the currently executing process and break in.

In steps 512 and 522,
The CPUB 402 and the CPU C 403 temporarily suspend the processing being executed and start the PTLB processing operation by the break-in.

In steps 514 and 524,
The CPUB 402 and the CPU 403 execute the PTLB operation based on the contents of the OS level register 190 transmitted via the signal line 400.

In steps 515 and 525,
When the execution of the PTLB operation specified by the CPU A 401 is completed, the CPU B 402 and the CPU C 403 send an operation end signal to the CPU A 401 via the signal line 400.

In steps 516 and 526,
The CPUB402 and the CPUC403 are the CPUA401
Then, after sending an operation end signal via the signal line 400, the CPU A 401 enters a wait state until a signal instructing continuation of normal processing is returned via the signal line 400.

At step 504, the CPUA 401
In step 503, a wait state has been entered.
And that the operation end signal is returned from the both via the signal line 400. Therefore, both CPUBs 402
If the operation end signal has been returned from the CPUC 403 via the signal line 400, the process proceeds to step 505.

At step 505, both CPUs B40
When the operation end signal is returned from the CPUB 401 and the CPUC403, the CPUA401 ends the operation of the steps 503 and 504, and the CPUB402 and the CPUC4.
A normal processing continuation request signal is sent to the control unit 03 via the signal line 400. After that, the normal processing is restarted.

In steps 519 and 529,
When the CPUB 402 and the CPU C 403 receive the normal processing continuation request signal from the CPU A 401 via the signal line 400, the CPU B 402 and the CPU C 403 execute the currently executed steps 516 and 52.
The waiting state executed in step 6 is terminated, and the normal processing is restarted.

Next, PTLB processing (steps 514 and 5) performed by CPUB 402 and CPUC 403
24) will be described in detail with reference to FIG.

FIG. 6 is an explanatory diagram showing PTLB processing of another central processing unit in the virtual machine system of FIG. In step 600, the PTL is sent according to the contents of the OS level register 190 sent via the signal line 400.
The level of the OS that issues the B processing is identified, and branching is performed according to the level.

The OS that has issued the PTLB processing is level 10
In the case of S or level 2 OS In this case, the process branches from step 600 to step 610. Step 6
At 10, regardless of the level of the OS currently running,
With reference to a plurality of level 2 OS identification entries 110 in the level 2 OS identification entry stack 115, VMID invalidation processing (setting the valid flag 7 to 0) for all the entries in which VM ID valid flag 112 is 1 .)I do.

In step 620, all levels 3
A plurality of levels 30 of the OS identification entry stack 124
Referring to the S identification entry 120, the VMI
For all entries whose D valid flag 121 is 1,
The VMID is invalidated (the valid flag 7 is set to 0).

The OS that has issued the PTLB processing is level 30
If S. In this case, the process branches from step 600 to step 620.

At step 630, the OS level register 190 identifies the current OS level, that is, the OS level of the central processing unit that receives the PTLB processing request, and branches according to the level.

The OS that has received the PTLB processing is level 10
If S. In this case, the process branches from step 630 to step 640, and in step 640, the level 1 OS identification entry 100 of the OS is updated. MAXVMID output by the adder 170
VMID1 is obtained by adding 1 to the value of the register 160.
Update 02. The level 2 OS valid flag 101 is not updated.

The OS that has received the PTLB processing is level 20
If S. In this case, the process branches from step 630 to step 650, and in step 650, the level 2 OS identification entry 110 of the OS is updated. MAXVMID output by the adder 170
VMID1 is obtained by adding 1 to the value of the register 160.
14 is updated, and the VMID valid flag 112 is set to 1. The level 3 OS valid flag 111 and the SD address 113 are not updated.

The OS that has received the PTLB processing is level 30
If S. In this case, the process branches from step 650 to step 680, and in step 680, the level 3 OS identification entry 120 of the OS is updated. MAXVMID output by the adder 170
VMID1 is obtained by adding 1 to the value of the register 160.
23 is updated, and the VMID valid flag 121 is set to 1. The SD address 122 is not updated.

At step 670, the VMID register 1
93 is updated, and the MAXVMID register 16
The value obtained by adding the value of 0 and 1 to the VMID register 19
3 is updated. After that, TLB192 registration and HI
The updated value of the VMID register 193 is used for the T determination.

In step 680, the process of updating the MAXVMID is performed, and the MAX
By the value obtained by adding 1 to the value of the VMID register 160,
The MAXVMID register 160 is updated.

As described above, in this embodiment,
In a multiprocessor configuration, when executing an instruction accompanied by invalidation of the address translation buffers of all the configured central processing units, communication means for directly transmitting and receiving information between the central processing units, and an OS for issuing the instruction Means for transmitting the execution level identification information to the other central processing unit via the communication means, whereby all the central processing units can recognize the execution level of the OS issuing the instruction.

When processing related to a TLB such as a PTLB instruction is executed in another central processing unit that requires an instruction, it is possible to determine whether it is necessary to invalidate the processing based on the OS execution level identification information. Therefore, it is possible to omit extra TLB entry invalidation processing. If invalidation processing is required, the execution level of the OS that issues the instruction is determined based on the OS execution level identification information without actually invalidating the TLB entry, and the VMID of each virtual machine and the VMID of the TLB entry are determined. By performing control that does not match, an effect equivalent to invalidating the TLB entry can be obtained without actually invalidating the TLB entry.

[0098]

As described above, according to the present invention, (1) the above-mentioned PT is provided by providing a flag for identifying whether or not a virtual machine exists on the currently running OS.
When executing processing related to TLB such as LB instruction, P
The determination as to whether to invalidate the TLB entry of the virtual machine on the OS on which the TLB instruction has been issued can be instantaneously determined by the flag.

(2) When processing related to the TLB such as the PTLB instruction is executed in the own central processing unit that requests the instruction, control is performed so that the VMID of each virtual machine does not match the VMID of the TLB entry. The VMID selected by the TLB control device and the VMID of the TLB entry without invalidating the TLB entry
Even if it is not configured to invalidate the TLB entry that matches the above, an effect equivalent to invalidating the TLB entry can be obtained.

(3) Further, in the multiprocessor configuration, when executing an instruction accompanied by invalidation of the address translation buffers of all the configured central processing units, communication means for directly transmitting and receiving information between the central processing units; Means for transmitting the execution level identification information of the OS issuing the instruction to the other central processing unit via the communication means, so that all the central processing units issue the instruction.
The execution level of S can be recognized.

(4) TL such as PTLB instruction
In the case where the processing related to B is executed in another central processing unit that requires an instruction, it is possible to determine whether or not the processing needs to be invalidated based on the OS execution level identification information. Invalidation processing can be omitted. If invalidation processing is required, the execution level of the OS that issues the instruction is determined based on the OS execution level identification information without actually invalidating the TLB entry, and the VMID of each virtual machine and the VMID of the TLB entry are determined. By performing control that does not match, an effect equivalent to invalidating the TLB entry can be obtained without actually invalidating the TLB entry.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing a configuration of a virtual computer system according to the present invention.

FIG. 2 is an explanatory diagram showing the entire processing of an SIE instruction in the virtual machine system of FIG. 1;

FIG. 3 is an explanatory diagram showing a PTLB process of a self-central processing unit in the virtual machine system of FIG. 1;

FIG. 4 is a diagram of a device configuration in a multiprocessor configuration.

FIG. 5 is a flowchart illustrating a processing procedure for a method of exchanging information between CPUs.

FIG. 6 is an explanatory diagram showing PTLB processing of another central processing unit in the virtual machine system of FIG. 1;

[Explanation of symbols]

 100 Level 1 OS Identification Entry 101 Level 2 OS Valid Flag 102 VMID 103 Level 1 OS Identification Entry Stack 110 Level 2 OS Identification Entry 111 Level 3 OS Valid Flag 112 VMID Valid Flag 113 SD Address 114 VMID 115 Level 2 OS Identification Entry Stack 120 Level 3 OS Identification Entry 121 VMID Valid flag 122 SD address 123 VMID 124 Level 2 OS identification entry stack 125 Level 2 OS identification entry stack group 130 Level 2 OSSD address 131 Level 3 OSSD address 140 AND gate 141 AND gate 150 Comparator 151 Comparator 160 MAXVMID register 170 Adder 180 Selector 181 Selector 190 OS level Register 191 selector 192 TLB 193 VMID register

 ──────────────────────────────────────────────────続 き The continuation of the front page F term (reference) 5B005 JJ01 KK13 MM36 MM51 PP21 RR01 5B098 AA10 HH01

Claims (4)

[Claims] A central processing unit having a plurality of virtual machines, a main storage shared by each of the virtual machines, and a logic when each of the virtual machines has accessed the main storage in the past; A plurality of entries for storing a plurality of sets of an address, an absolute address corresponding to the logical address, a virtual machine identification code assigned to the access source virtual machine, and execution level identification information of the virtual machine as one set; In a virtual computer system having an address translation buffer for translating a logical address to an absolute address by referring to the entry when the computer accesses the main storage device, a real computer whose execution level identification information is a level 1 OS And whether the virtual computer which is the level 2 OS exists on the real computer. And a virtual machine identification code of the virtual machine and an operand address of an instruction for activating the virtual machine for each virtual machine whose execution level identification information of the virtual machine is the level 2OS. A flag indicating the validity of the virtual machine identification code of the virtual machine, and a level 30 on the virtual machine.
4 of a flag for identifying whether a virtual machine of S exists
For each of the virtual machines whose execution level identification information is a level 3 OS, a virtual machine identification code of the virtual machine, an operand address of an instruction for starting the virtual machine, and the virtual machine And a level 3 OS identification entry consisting of three flags indicating the validity of the virtual computer identification code of the level 1 OS. In executing an instruction issued by a real computer of the level 1 OS to activate the virtual computer, the level 2 OS of the level 1 OS identification entry is executed. Means for enabling a flag for identifying whether or not a virtual machine exists, and all level 2 OS identification entries for which the operand address of the instruction and the flag indicating the validity of the virtual machine identification code of the virtual machine are valid. If the operand addresses do not match, the virtual Means for registering a machine identification code, an operand address of an instruction for starting the virtual machine, and a flag indicating the validity of the virtual machine identification code in a new level 2OS identification entry; and a virtual machine issued by a real machine of the level 2OS. Means for validating a flag for identifying whether there is a virtual machine that is a level 3 OS of the level 2 OS identification entry upon execution of the activation instruction;
If the operand address of the instruction and the operand address of all the level 3 OS identification entries for which the flag indicating the validity of the virtual machine identification code of the virtual machine does not match, the virtual machine identification code of the virtual machine and the virtual machine Means for registering an operand address of an instruction to be activated and a flag indicating the validity of the virtual machine identification code of the virtual machine in a new level 3 OS identification entry. 2. The virtual computer system according to claim 1, wherein the local computer executes processing of an instruction accompanied by invalidation of an address translation buffer issued by the real computer of the level 1 OS in the own central processing unit. If the flag for identifying whether a virtual machine which is a level 2 OS exists on the real computer is valid, all the level 2 OS identification entries are referred to, and the level 2 OS identification entry of the level 2 OS identification entry is referred to. If there is an entry in which the validity flag of the virtual machine identification code is valid,
The flags of all valid entries are invalidated. If there is an entry with a valid flag for identifying whether a virtual machine that is a level 3 OS exists, all the level 3 OS identification entries are referred to and the level 3 OS identification is performed. When there is an entry in which the validity flag of the virtual machine identification code of the entry is valid, the instruction is performed in which the flags of all valid entries are invalidated and the address translation buffer issued by the level 2 OS virtual machine is invalidated. In executing the process in the own central processing unit, a virtual machine identification code of a new virtual machine is stored in the virtual machine, and a flag for identifying whether a virtual machine which is a level 3 OS exists on the virtual machine is effective. In the case of, all level 3 OS identification entries are referred to, and the virtual If there is an entry for which the validity flag of the computer identification code is valid, the flags of all valid entries are invalidated, and the instruction with invalidation of the address translation buffer issued by the virtual computer of the level 3 OS is disabled. A virtual machine system, wherein the virtual machine stores a virtual machine identification code of a new virtual machine in execution of processing in the central processing unit, and does not match the virtual machine identification codes of all address translation buffer entries. 3. A communication means for directly transmitting and receiving information between the central processing units, and, in a multiprocessor configuration, executing instructions accompanied by invalidation of address translation buffers of all the configured central processing units. A means for transmitting execution level identification information of the OS issuing the command to the other central processing unit via the communication means. 4. The virtual computer system according to claim 1, wherein the instructions issued by the computer of each level OS and accompanied by invalidation of the address translation buffer are used to execute the processing in the central processing unit. A new virtual machine identification code is stored in the computer, and when the execution level identification information of the OS transmitted by the communication means is a level 1 OS, all the level 2 OS identification entries and the level 3 identification entries are referred to. , Level 2 OS
If there is an entry in which the validity flag of the virtual machine identification code of the identification entry and the level 3 OS identification entry is valid, the flags of all valid entries are invalidated, and the execution level of the OS transmitted by the communication means is invalidated. If the identification information is a level 2 OS, all level 2 OSs
If the validity flag of the virtual machine identification code of the level 2 OS identification entry and the level 2 OS identification entry exists with reference to the identification entry and the level 3 identification entry, the flags of all the valid entries are invalidated. When the execution level identification information of the OS transmitted by the communication means is a level 3 OS, all the level 3 OS identification entries are referred to, and the validity flags of the level 2 OS identification entry and the virtual machine identification code of the level 2 OS identification entry are set. A virtual machine system, wherein when there is a valid entry, the flags of all valid entries are invalidated and are not matched with the virtual machine identification codes of all address translation buffer entries.