JPH05151029A - Watch dog timer device - Google Patents

Abstract

PURPOSE:To provide the watch dog timer capable of monitoring the state of a microcomputer even in s standby state. CONSTITUTION:When the charge/discharge power of a charge/discharge circuit reaches a second threshold level VH in a standby state, a second timing signal *TIM from a timing signal generation circuit 9 is forcedly generated at constant intervals. Thereby operating the charge/discharge circuit to execute the operation of a watch dog timer, normally turning the computer 1 from the standby state to the normal operation state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a watchdog timer device capable of monitoring the operation of a microcomputer even in a standby state.

[0002]

2. Description of the Related Art An oscillating clock is applied to a microcomputer, and the oscillating clock is divided through a plurality of stages of flip-flops or the like until it becomes a system clock of a predetermined frequency. Then, in synchronization with this system clock, the program data is read from the ROM and is decoded according to the contents of the C in the microcomputer.
PU is running.

Here, in the microcomputer, it is desirable that the program instructions are normally executed and the CPU operates normally, but sometimes the program runs away due to external noise or the like. Then, there arises a problem that the CPU does not operate normally and the expected calculation result cannot be obtained. In this case, it is necessary to reset the operation of the microcomputer as soon as possible to return the microcomputer to normal operation.

Therefore, conventionally, a timer counter for monitoring whether or not the microcomputer is normally operating is provided, and the timer operation of the timer counter is reset by a timing signal generated at regular intervals by a program command. I was doing Specifically, when the program instruction is executed normally, the timer counter is reset by the timing signal before the timer counter generates the overflow output, that is, the overflow output is obtained from the timer counter. It disappeared, and it was judged from this that the microcomputer was operating normally. On the contrary, if the program goes out of control, the timing signal will not be generated. Therefore, an overflow output is generated from the timer counter, and it is determined that the microcomputer is malfunctioning due to this overflow output, and the operation of the microcomputer is reset.

[0005]

The above description is only for the case where the microcomputer is in the normal operating state, and in this case, the operating state of the microcomputer can be monitored. However, when the microcomputer is changed from the normal operation state to the standby state, the oscillation operation of the oscillator is stopped and the program instruction cannot be executed. That is, the timing signal is not generated at regular intervals, and the watchdog timer operation cannot be performed.

In the standby state, if the power supply voltage drops for some reason, the program data cannot be read correctly from the ROM when the standby state shifts to the normal operation state, and program runaway may occur. Further, it may happen that the oscillator cannot be started when the standby state shifts to the normal operation state due to the decrease in the power supply voltage. Further, in the standby state, the operation result based on the program instruction is held in the RAM, the register or the like, but the held data may be destroyed by external noise or the like. In other words, the conventional microcomputer cannot monitor the above-mentioned inconvenient state because the watchdog timer operation cannot be performed in the standby state.

Therefore, the conventional microcomputer has a problem that it cannot monitor whether or not there is an abnormal state when the microcomputer shifts from the standby state to the normal operation state. Therefore, an object of the present invention is to provide a watchdog timer device capable of monitoring the state of the microcomputer even in the standby state.

[0008]

The present invention has been made to solve the above-mentioned problems, and is characterized in that when the CPU is in a normal operation state, the oscillator is operated to operate. Execute program instruction based on oscillation output,
First generated at constant intervals based on the program instruction
In a microcomputer that performs a watchdog timer operation in synchronization with the timing signal of 1) and stops the operation of the oscillator when the CPU is in a standby state, the microcomputer charges (or discharges) in synchronization with the first timing signal. And a charging / discharging circuit for discharging (or charging) based on a time constant from the first timing signal until the next first timing signal is generated, and having a first threshold level, A first buffer circuit to which the charge / discharge output of the charge / discharge circuit is applied, a reset control circuit that performs reset control of the microcomputer based on the output of the first buffer circuit, and a second timing signal that is constant. A timing signal generating circuit which is generated at every interval;
And a timing signal control circuit for controlling the timing signal generation circuit based on the output of the second buffer circuit, the second buffer circuit having a threshold level of And when the CPU is in a standby state and the charge / discharge output of the charge / discharge circuit reaches the second threshold level of the second buffer circuit, the timing signal generating circuit outputs the second timing signal. The point is that a signal is forcibly generated and the charge / discharge circuit is charged / discharged.

[0009]

According to the present invention, when the charging / discharging output of the charging / discharging circuit reaches the second threshold level in the standby state, the timing signal generating circuit forcibly generates the second timing signal at regular intervals, As a result, the charge / discharge circuit can be charged / discharged to execute the watchdog timer operation, and the operation of the microcomputer in the standby state can be monitored.

[0010]

The details of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing a watchdog timer device of the present invention. In FIG. 1, (1) is a microcomputer, and the microcomputer (1) has a ROM (not shown) in which program data is stored.
Then, in the normal operation state, in synchronization with the system clock obtained by dividing the oscillation output of the oscillator, the program data is read from the ROM and the program instruction is executed, and the CPU (not shown) is kept in a predetermined state. It's working. At this time, each time a program instruction is executed, a pulse-shaped first timing signal is generated at a constant time interval. This timing signal will be described later, but the microcomputer (1) normally operates according to the program instruction. It is used as a control signal for monitoring whether or not it is.

The capacitor (2) and the resistor (3) are provided outside the microcomputer (1), and the capacitor (2)
And resistor (3) are connected in parallel between terminal (4) and ground V _SS . (5) is a P-type MOS transistor (charging / discharging transistor) whose drain / source path is connected between the power source V _DD and the terminal (4), and includes a capacitor (2) and a resistor.
This is for controlling the charging / discharging operation according to (3). That is, during normal operation of the program, P-type MOS transistor
The first timing signal described above is applied to the gate of (5), and the capacitor (2) is synchronized with this timing.
And the resistor (3) is in charge / discharge operation. Specifically, the pulse-shaped first timing signal which becomes a low level (hereinafter referred to as “L”) at regular intervals is the P-type MOS transistor (5).
When applied to the gate of the capacitor, the capacitor (2) performs a charging operation and the potential of the terminal (4) rises rapidly to V _DD . In addition, from the generation of the first timing signal to the generation of the next first timing signal, the charged charge of the capacitor (2) depends on the time constant determined by the capacitor (2) and the resistor (3). Is discharged, that is, the potential of the terminal (4) gradually falls according to the time constant. This charging / discharging operation is repeated in synchronization with the first timing signal. In addition, the capacitor (2), the resistor (3), and the P-type MO
A charging / discharging circuit is constituted by the S transistor (5).

(6) is an inverter (first buffer circuit) having a first threshold level V _L, to which the output of the charging / discharging circuit appearing at the terminal (4) is applied.
Reference numeral (7) is a reset circuit, which generates a reset signal when the output of the inverter (6) becomes high level (hereinafter referred to as "H"). The reset signal may be a signal that systematically resets the CPU, ROM, RAM, peripheral circuits, etc. inside the microcomputer (1), or specifies the port, clock generation circuit, etc. of the microcomputer (1). The signal may be a signal for completely stopping the operation of the microcomputer (1) after being set to the state. That is, when the program command is normally executed, the potential of the terminal (4), that is, the charge / discharge input to the inverter (6) is constantly changing at a level higher than the first threshold level V _L , that is, The output of the inverter (6) is always "L" and the reset signal (7) does not generate a reset signal, and the microcomputer (1) normally operates. Also, when the program runs out of control, the first timing signal is not generated, so the inverter
The charge / discharge input to (6) is the first threshold level V _L.
Thus, the output of the inverter (6) becomes "H" and the reset signal output from the reset circuit (7) resets the microcomputer (1).

(8) is a first inverter set in the inverter (6)
Is an inverter (second buffer circuit) having a second threshold level V _H higher than the threshold level V _{L of}
It is connected to (4). The inverter 8 is disabled in the normal operation state and enabled in the standby state.

(9) is the first task in the standby state.
The second timing signal * TIM instead of the imming signal
It is a timing signal generation circuit for generation. Standby
State, the system clock is set based on the stoppage of the oscillator.
The lock no longer occurs and the program runs
And the first timing signal is no longer generated
As a result, the operation of the microcomputer (1) cannot be monitored.
It gets worse. Therefore, even in the standby state,
In order to monitor the status of the microcomputer (1),
The imming signal generating circuit (9) is provided. Thymin
The oscillation signal obtained from the oscillator is included in the signal generator circuit (9).
Timing signal control circuit to be described later.
The oscillation clock is divided by the output of
Second pulse-shaped timing signal that becomes “L” at every interval *
Generate a TIM. (10) is the timing signal control described above
Circuit, timing according to the output of the inverter (8)
The second timing signal * TIM from the signal generation circuit (9)
It is forcibly generated. For more information, stand by
In the initial state of the state, fully charge the capacitor (2).
In this state, the first timing signal is not generated.
Therefore, the potential of the terminal (4) is the capacitor (2) and the resistor (3).
It will gradually fall according to the time constant of. That
The potential of the terminal (4) becomes the second threshold level V_H
When it goes down, the “H” output of the inverter (8) is tied.
Applied to the ming signal control circuit (10)
Standby state monitor stored in ROM by restarting oscillation
The service routine program for viewing is read and
The second timing of "L" is output from the minging signal generating circuit (9).
Signal * TIM will be forcibly generated. this
Turns on the P-type MOS transistor (5)
The terminal (4) instantly changes to V_DD
Will stand up. The potential of the terminal (4) is V _DDTo
When it rises, the timing signal control circuit (10)
Oscillation until the "H" output of the inverter (8) is applied again
The instrument will stop oscillating.

This state is shown in the waveform diagram of FIG.
is there. That is, the power source V _DDAnd the second thresh
Level V_HBetween the capacitor (2) and the resistor
Charging / discharging is repeated according to the time constant of (3), and standby
State of the microcomputer (power state,
Data retention status, etc.) will be monitored. Obey
And the potential of the terminal (4) is the power supply V_DDAnd the second threshold
Level V_HIf there is a change between
Operation of the black computer (1) in standby mode
The condition is judged to be normal. However, outside
Incoming noise affects microcomputer (1)
Then, the timing generator circuit (9) divides the oscillation clock.
Cannot be performed and the second timing signal * TIM is generated
Hold RAM, registers, etc.
Suppose the data is also destroyed at the same time. Alternatively,
Power supply voltage V_DDIs lowered for some reason,
Oscillator does not oscillate normally, RAM, register
Data is no longer retained in the
Even if the standby state is changed to the normal operation state, the
Program data cannot be read normally.
To try In this case, the potential of the terminal (4) is the inverter (6)
First threshold level V of_LGoing down to
From this, the reset signal from the reset circuit (7)
Occurs, the microcomputer (1) is reset
It will be. Therefore, the microcomputer (1) is
Even if you shift from the standby state to the normal operation state,
It is possible to prevent normal operation in a proper state.
It

The first timing signal and the second timing signal * TIM may have the same waveform, and the potential of the terminal (4) is the power source V when the program operates normally.
If it changes between _DD and the first threshold level V _L , the interval at which the first timing signal is generated is T
It may be more than or less than T. 3, 4, and 5 are diagrams showing other embodiments of the charging / discharging circuit shown in FIG. The same elements as those in FIG. 1 are designated by the same reference numerals.

In FIG. 3, the capacitor (2) and the resistor (3) are connected in series between the power source V _DD and the ground V _SS, and the drain / source path of the P-type MOS transistor (5) is connected to the capacitor (2).
It is connected in parallel with. In this case, the first timing signal or the second timing signal * TIM that becomes “L”
Is applied to the gate of the P-type MOS transistor (5), the capacitor (2) discharges and the inverter (6)
(8) The input instantly rises to V _DD, and during the period when the first or second timing signal is not applied to the gate of the P-type MOS transistor (5), the time constant is determined by the capacitor (2) and the resistor (3). The charging operation is performed, and the inputs of the inverters (6) and (8) gradually fall. Even if the charging / discharging circuit of FIG. 3 is used instead of the charging / discharging circuit of FIG. 1, the charging / discharging output appearing at the terminal (4) is the same, so the watchdog timer device is configured without changing the other configurations of FIG. You can do it.

FIG. 4 shows a capacitor (2) and a resistor.
One end of (3) is connected to the power supply V _DD, and the other end is connected to the ground V _SS via the N-type MOS transistor (11). In this case, the first timing signal and the second timing signal TIM applied to the gate of the N-type MOS transistor (11) are set to pulse-like "H" signals. When the gate of the N-type MOS transistor (11) becomes "H", the capacitor (2) performs a charging operation, and the output of the charge / discharge circuit instantly falls to V _SS . After that, until the first or second timing signal that becomes "H" is generated, the discharging operation is performed according to the time constant determined by the capacitor (2) and the resistor (3), and the output of the charge / discharge circuit is output. Will gradually rise. Here, comparing the charging / discharging characteristics of the charging / discharging circuit of FIG. 3 and the charging / discharging circuit of FIG. 4, when FIG. 3 instantaneously performs the discharging operation, FIG. 4 instantaneously performs the charging operation, and FIG. When performing the charging operation according to the constant, FIG. 4 performs the discharging operation according to the time constant, that is, the charge / discharge characteristics of FIGS. 3 and 4 are opposite. Therefore, when the charge / discharge circuit of FIG. 4 is used instead of the charge / discharge circuit of FIG. 1, an inverter (12) having a high threshold level V _H ′ is used instead of the inverter (6) connected to the reset control circuit (7). ) And an inverter (13) for inverting the output of the inverter (12) are connected in series. Further, instead of the inverter (8) connected to the timing signal control circuit (10), a low threshold level V
An inverter (14) having _L '(< _VH ') and the inverter (1
The inverter (15) for inverting the output of 4) may be connected in series.

FIG. 5 shows a resistor (3) and a capacitor.
(2) is connected in series between the power supply V _DD and the ground V _SS, and the drain-source path of the N-type MOS transistor (11) is connected in parallel with the capacitor (2). In this case, when the pulse-shaped "H" first timing signal or second timing signal TIM is applied to the gate of the N-type MOS transistor (11), the capacitor (2) performs a discharging operation to charge and discharge. The output of the circuit instantaneously falls to V _SS, and in the period until the next first or second timing signal is generated,
The output of the charge / discharge circuit gradually rises according to the time constant. Therefore, since the charge / discharge waveforms of FIGS. 4 and 5 are the same, the charge / discharge waveforms of FIGS. 4 and 5 are compared with the configuration when the charge / discharge circuit of FIG. 4 is used instead of the charge / discharge circuit of FIG. All you have to do is replace the circuit.

[0020]

According to the present invention, it is possible to monitor the malfunction of the microcomputer such as the arrival of noise and the drop of the power supply voltage in the standby state. Therefore, there is an advantage that the standby state can be normally shifted to the normal operating state.

[Brief description of drawings]

FIG. 1 is a diagram showing a watchdog timer device of the present invention.

FIG. 2 is a waveform diagram showing charge / discharge waveforms in the standby state of FIG.

FIG. 3 is a diagram showing a second embodiment of the charging / discharging circuit used in FIG.

FIG. 4 is a diagram showing a third embodiment of the charge / discharge circuit used in FIG.

5 is a diagram showing a fourth embodiment of the charging / discharging circuit used in FIG. 1. FIG.

[Explanation of symbols]

 (1) Microcomputer (2) Capacitor (3) Resistor (5) P-type MOS transistor (6) (8) (12) (14) Inverter (7) Reset control circuit (9) Timing signal generation circuit (10) Timing Signal control circuit

Claims (2)

[Claims] 1. When a CPU is in a normal operation state, an oscillator is operated to execute a program command based on an oscillation output of the oscillator, and is synchronized with a first timing signal generated at regular intervals based on the program command. In the microcomputer that stops the operation of the oscillator when the CPU is in the standby state by performing the watchdog timer operation, the charging (or discharging) is performed in synchronization with the first timing signal. Discharge based on the time constant from the timing signal of 1 to the generation of the next timing signal
A charging / discharging circuit for performing (or charging), a first buffer circuit having a first threshold level, to which the charging / discharging output of the charging / discharging circuit is applied, and based on the output of the first buffer circuit. A reset control circuit that performs reset control of the microcomputer, a timing signal generation circuit that generates a second timing signal at regular intervals, a second threshold level, and a charge / discharge output of the charge / discharge circuit is applied. A second buffer circuit, and a timing signal control circuit for controlling the timing signal generation circuit based on the output of the second buffer circuit,
When the CPU is in the standby state and the charge / discharge output of the charge / discharge circuit reaches the second threshold level of the second buffer circuit, the second timing signal is output from the timing signal generation circuit. A watchdog timer device characterized in that it is forcibly generated and the charge / discharge circuit is charged / discharged. 2. The charging / discharging circuit includes a capacitor, a resistor, and a charging / discharging transistor to which the clock signal is applied so that a charging / discharging operation by the capacitor and the resistor is periodically executed. The watchdog timer device according to claim 1, wherein: