JPH0514984A - Line processing unit control system - Google Patents

Line processing unit control system

Info

Publication number
JPH0514984A
JPH0514984A JP16062891A JP16062891A JPH0514984A JP H0514984 A JPH0514984 A JP H0514984A JP 16062891 A JP16062891 A JP 16062891A JP 16062891 A JP16062891 A JP 16062891A JP H0514984 A JPH0514984 A JP H0514984A
Authority
JP
Japan
Prior art keywords
line
echo canceller
line processing
control
path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16062891A
Other languages
Japanese (ja)
Other versions
JP2935293B2 (en
Inventor
Tatsuya Igarashi
達哉 五十嵐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KDDI Corp
Original Assignee
Kokusai Denshin Denwa KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kokusai Denshin Denwa KK filed Critical Kokusai Denshin Denwa KK
Priority to JP16062891A priority Critical patent/JP2935293B2/en
Publication of JPH0514984A publication Critical patent/JPH0514984A/en
Application granted granted Critical
Publication of JP2935293B2 publication Critical patent/JP2935293B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Time-Division Multiplex Systems (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

PURPOSE:To attain the control of the line processing unit from an exchange system independently of the installing location of the line processing unit by sharing a control information path of various line processing units in common in the exchange system accommodating an inter-station line so as to simplify the hardware of the exchange system. CONSTITUTION:A control signal S1 is transferred by using bits A-D on a specific time slot on a same transmission highway path VI in compliance with the CCITT recommendations Q.50 ANNEX A and various line processing units are controlled unifiedly by using the same transmission highway path VI in the case of controlling the various line processing units such as a digital line multiplexer 1 on a line, an echo canceller 3a and an A/mu converter 3b in an exchange system 4 accommodating an inter-station line.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、局間回線を収容する交
換システムにおける回線上の回線処理装置の制御方式に
関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control system for a line processing device on a line in a switching system accommodating an interoffice line.

【0002】[0002]

【従来の技術】この分野における従来の技術を図4に示
す。図中、1はディジタル回線多重化装置(Digital Ci
rcuit Multiplication Equipment、以下「DCME」と
略称する)、2は伝送同期端局設備、3はエコーキャン
セラ3a,A/μ変換器3b等から構成されるエコーキ
ャンセラ装置、4は各種通信種別を扱う交換システム、
4a,4bはDCME制御用伝送ハイウェイパスIII と
エコーキャンセラ装置制御用パスIVにそれぞれ対応する
交換システム4内のDCME制御部とエコーキャンセラ
装置制御部、Ia〜IdはDCME1と伝送同期端局設
備2との間の伝送路、IIは伝送同期端局設備2とエコー
キャンセラ装置3との間の伝送ハイウェイ、III はエコ
ーキャンセラ装置3と交換システム4との間のDCME
制御用伝送ハイウェイパス、IVはエコーキャンセラ装置
3と交換システム4との間のエコーキャンセラ装置3制
御用パス、VはDCME1に入出力される外部との伝送
路である。
2. Description of the Related Art A conventional technique in this field is shown in FIG. In the figure, 1 is a digital circuit multiplexer (Digital Cipher).
rcuit Multiplication Equipment, abbreviated as "DCME" hereinafter), 2 is a transmission synchronization terminal equipment, 3 is an echo canceller device composed of an echo canceller 3a, A / μ converter 3b, etc., 4 is an exchange that handles various communication types. system,
4a and 4b are the DCME control unit and the echo canceller device control unit in the switching system 4 corresponding to the DCME control transmission highway path III and the echo canceller device control path IV, respectively, and Ia to Id are the DCME 1 and the transmission synchronization terminal equipment 2. , II is a transmission highway between the transmission synchronization terminal equipment 2 and the echo canceller device 3, and III is DCME between the echo canceller device 3 and the switching system 4.
A control transmission highway path, IV is a control path for controlling the echo canceller device 3 between the echo canceller device 3 and the switching system 4, and V is a transmission path to the outside that is input to or output from the DCME 1.

【0003】図4に示すように、従来の回線処理装置制
御方式においては、国際電信電話諮問委員会(以下「C
CITT」と略称する)勧告で定められたDCME1制
御用パスIII の他、エコーキャンセラ3a,A/μ変換
器3b等から構成されるエコーキャンセラ装置3用の制
御情報パスIVを別に設定する必要があった。
As shown in FIG. 4, in the conventional line processor control system, the International Telegraph and Telephone Advisory Committee (hereinafter referred to as "C
It is necessary to separately set the control information path IV for the echo canceller device 3 including the echo canceller 3a, the A / μ converter 3b, etc. in addition to the DCME1 control path III defined by the recommendation). there were.

【0004】[0004]

【発明が解決しようとする課題】前記のような従来の回
線処理装置制御方式では、交換システム4の内部にDC
ME1制御用パスIII ,エコーキャンセラ装置3用制御
パスIV等の各制御用パスに対応した独立の制御機能をも
つことが必要となるため、交換システム4の構成が複雑
となり、そのハードウェア規模が増大するという課題が
あった。
In the conventional line processor control system as described above, the DC is provided inside the switching system 4.
Since it is necessary to have an independent control function corresponding to each control path such as the ME1 control path III and the echo canceller device 3 control path IV, the configuration of the exchange system 4 becomes complicated and its hardware scale becomes large. There was a problem of increasing.

【0005】[0005]

【課題を解決する手段】前記課題の解決は、本発明が次
の新規な特徴的構成方式を採用することにより達成され
る。即ち、本発明の特徴は、局間回線を収容する交換シ
ステムで回線上のディジタル回線多重化装置,エコーキ
ャンセラ,A/μ変換器等の種々の回線処理装置を制御
する場合において、CCITT勧告Q.50 ANNE
X Aに準拠する同一伝送路上の特定タイムスロット上
のビットを用いて制御信号を転送し、前記種々の回線処
理装置を同一の伝送路を用いて統一的に制御してなる回
線処理装置制御方式である。
The above-mentioned problems can be solved by the present invention by adopting the following novel characteristic construction system. That is, the feature of the present invention is that CCITT Recommendation Q is used when controlling various line processing devices such as a digital line multiplexer, an echo canceller, an A / μ converter on the line in a switching system accommodating an interoffice line. . 50 ANE
A line processing device control method in which a control signal is transferred by using a bit on a specific time slot on the same transmission line conforming to XA, and the various line processing devices are uniformly controlled using the same transmission line. Is.

【0006】[0006]

【作用】本発明は、前記のような方式を講じて、交換シ
ステム内に設けた統一的な制御部から同一伝送路上の特
定タイムスロット上のビットを用いて各種回線処理装置
用の統一的な制御信号を送信し、当該送信信号により各
種回線処理装置の制御を行うから、従来のように各々の
回線処理装置ごとに伝送用制御パスや交換システム内の
制御機能を設ける必要はない。
According to the present invention, by adopting the above-mentioned method, the unified control unit provided in the switching system uses the bits on the specific time slot on the same transmission line to make a unified system for various line processing devices. Since a control signal is transmitted and various line processing devices are controlled by the transmission signal, it is not necessary to provide a transmission control path or a control function in the switching system for each line processing device as in the conventional case.

【0007】[0007]

【実施例】次に、本発明方式の実施例について図面を参
照して説明する。図1は本実施例を適用した構成接続
例、図2は同・2メガbit/s 伝送路タイムスロット16
相当信号のフレームフォーマット、図3は同・エコーキ
ャンセラ装置制御用に割り当てたC,Dビットの構成を
示す表である。図中、4cは交換システム4内に設けら
れたDCME1及びエコーキャンセラ装置3の統一的な
制御部、VIは統一されたDCME及びエコーキャンセラ
装置制御用伝送ハイウェイパスである。なお、従来のも
のと同一の要素には、同一の符号を付した。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the method of the present invention will be described with reference to the drawings. FIG. 1 shows an example of the configuration and connection to which this embodiment is applied, and FIG. 2 shows the same 2 megabit / s transmission line time slot 16
FIG. 3 is a table showing the frame format of the equivalent signal, and the configuration of the C and D bits allocated for controlling the echo canceller device. In the figure, 4c is a unified control unit of the DCME 1 and the echo canceller device 3 provided in the switching system 4, and VI is a unified transmission highway path for controlling the DCME and echo canceller device. The same elements as those of the conventional one are designated by the same reference numerals.

【0008】本実施例を図1を参照して説明する。図1
において、交換システム4は各種通信種別を扱う交換シ
ステムであり、ユーザからの通信種別に応じて、DCM
E1及びエコーキャンセラ装置3等の回線処理装置を制
御する場合、交換システム4から2メガbit/s 伝送路タ
イムスロット16に対応する伝送ハイウェイVI(8.4
メガbit/s )のタイムスロット67〜70上に制御信号
S1を転送する。エコーキャンセラ装置3は、転送され
てきた制御信号S1のうち自装置に関係する信号を用い
て、エコーキャンセラ3a及びA/μ変換器3bのイネ
ーブル/ディセイブルの制御を行う。さらに本制御信号
S1は伝送ハイウェイII(8.4メガbit/s )から伝送
同期端局設備2を透過的に転送され、伝送路Ia〜Id
(2メガbit/s )を介してDCME1に転送される。D
CME1は、エコーキャンセラ装置3と同様に、自装置
に関係する信号を用いて、ユーザからの要求による各種
通信種別に応じた伝送路の捕捉等の制御を行う。
This embodiment will be described with reference to FIG. Figure 1
In the above, the exchange system 4 is an exchange system that handles various communication types, and depending on the communication type from the user, the DCM
When controlling the line processing devices such as the E1 and the echo canceller device 3, the switching highway VI (8.4) corresponding to the 2 megabit / s transmission line time slot 16 from the switching system 4 is used.
The control signal S1 is transferred onto the time slots 67 to 70 of megabit / s). The echo canceller device 3 controls the enable / disable of the echo canceller 3a and the A / μ converter 3b by using the signal related to the own device in the transferred control signal S1. Further, the control signal S1 is transparently transferred from the transmission highway II (8.4 megabit / s) to the transmission synchronous terminal equipment 2, and the transmission lines Ia to Id are transmitted.
It is transferred to DCME1 via (2 megabit / s). D
Similar to the echo canceller device 3, the CME 1 uses signals related to its own device to perform control such as capture of a transmission line according to various communication types requested by a user.

【0009】図2のフォーマットは、本実施例が採択し
た特定タイムスロット上のビットとしてCCITT勧告
Q.50 ANNEX Aに示されているDCME制御
のためのフレームフォーマットと同一である。まず、本
フレームフォーマットの概要を説明する。図2のフレー
ムフォーマットにおいて、タイムスロット16を2メガ
bit/s 16フレームで1マルチフレームを組み、フレー
ム0でマルチフレーム同期信号(ビットB1〜B4が全
て“0”)及び2メガbit/s (30チャンネル)単位で
のベアラリソース状態情報並びに保守情報を転送し、フ
レーム1〜15で回線対応にベアラ設定/解放情報及び
伝送路障害情報(制御用ビット:A,B,C,D)を転
送する。なお、CCITT勧告ではDCME制御にA,
BもしくはC,Dの何れかの2ビットを使用することと
しているから、本実施例では、A,BビットをCCIT
T勧告に準拠したDCME1制御に、C,Dビットをエ
コーキャンセラ装置3の制御に割り当てている。
The format of FIG. 2 is CCITT recommended Q.264 as bits on a specific time slot adopted by this embodiment. It is the same as the frame format for DCME control shown in 50 ANNEX A. First, an outline of this frame format will be described. In the frame format shown in FIG. 2, the time slot 16 has 2 megabytes.
Bit / s 16 frames form one multi-frame, frame 0 multi-frame sync signal (bits B1 to B4 are all "0") and bearer resource status information and maintenance information in units of 2 megabit / s (30 channels) , And bearer setting / release information and transmission path failure information (control bits: A, B, C, D) are transferred in frames 1 to 15. According to CCITT recommendation, A is used for DCME control.
Since two bits of B, C, or D are used, in the present embodiment, the A and B bits are CCIT.
The C and D bits are assigned to the control of the echo canceller device 3 for the DCME1 control based on the T recommendation.

【0010】次に、各装置制御用に割り当てたA,B及
びC,Dビットの詳細につき説明するが、前記したよう
に、DCME1制御に割り当てたA,BビットはCCI
TT勧告に準拠していることから、説明を省略する。図
3において、交換システム4からエコーキャンセラ装置
3方向の信号S1について、Cビットの“0”がエコー
キャンセラ3aのイネーブル,“1”がディセイブル、
Dビットの“0”がA/μ変換器3bのディセイブル,
“1”がイネーブル状態と対応づけており、論理的には
Cビット=“0”(エコーキャンセラ3a=イネーブ
ル),Dビット=“0”(A/μ変換器3b=ディセイ
ブル)の組み合わせは存在しないことから、擬似同期信
号に結びつく“00”ビットの発生を防止できる。同様
に、エコーキャンセラ装置3から交換システム4方向の
信号として、[C,Dビット=“01”or“10”]に
アラーム(異常)状態、[C,Dビット=“11”]に
エコーキャンセラ3a及びA/μ変換器3bの正常状態
を表す信号を割り付け、[C,Dビット=“00”]を
未使用とすることで擬似同期信号の発生を防止してい
る。
Next, the details of the A, B and C, D bits allocated for controlling each device will be described. As described above, the A, B bits allocated for the DCME1 control are CCI.
The description is omitted because it complies with the TT recommendation. In FIG. 3, in the signal S1 from the switching system 4 to the echo canceller device 3, C bit “0” is enable of the echo canceller 3a, “1” is disable,
"0" of D bit is disable of A / μ converter 3b,
"1" is associated with the enabled state, and logically there is a combination of C bit = "0" (echo canceller 3a = enable) and D bit = "0" (A / μ converter 3b = disable). Therefore, it is possible to prevent the generation of the "00" bit associated with the pseudo sync signal. Similarly, as a signal from the echo canceller device 3 to the switching system 4, an alarm (abnormal) state is displayed in [C, D bits = "01" or "10"] and an echo canceller is displayed in [C, D bits = "11"]. Signals representing the normal state of 3a and the A / μ converter 3b are assigned and [C, D bits = "00"] are unused to prevent the generation of pseudo sync signals.

【0011】[0011]

【発明の効果】以上説明したように、本発明方式によれ
ば、回線上に接続されるDCMEとエコーキャンセラ、
A/μ変換器を含むエコーキャンセラ装置等の制御用パ
スを共有可能となり、交換システムに接続される各種回
線処理装置の制御信号転送用のデータパスと制御すべき
回線が同一伝送路上にあるため新たにデータパスを設定
する必要がなく、回線処理装置の設置場所に左右されず
に交換システムから回線処理装置の制御が可能となると
ともに、交換システムのハードウェアの構成が簡略化さ
れる等優れた有用性を発揮する。
As described above, according to the method of the present invention, the DCME and the echo canceller connected on the line,
The control path of the echo canceller device including the A / μ converter can be shared, and the data path for control signal transfer of various line processing devices connected to the switching system and the line to be controlled are on the same transmission line. It is not necessary to set a new data path, the line processing device can be controlled from the switching system without being affected by the installation location of the line processing device, and the hardware configuration of the switching system is simplified. Demonstrate usefulness.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明方式の実施例を適用した回線処理装置接
続例である。
FIG. 1 is a connection example of a line processing device to which an embodiment of the system of the present invention is applied.

【図2】同上による制御方式における2メガbits/s伝送
路タイムスロット16相当信号のフレームフォーマット
である。
FIG. 2 is a frame format of a signal corresponding to a 2 megabits / s transmission path time slot 16 in the control method according to the above.

【図3】同上におけるエコーキャンセラ装置制御用に割
り当てたC,Dビットの構成を示す表である。
FIG. 3 is a table showing a configuration of C and D bits allocated for controlling the echo canceller device in the above.

【図4】従来の回線処理装置制御方式の接続構成例であ
る。
FIG. 4 is a connection configuration example of a conventional line processing device control system.

【符号の説明】[Explanation of symbols]

1…DCME 2…伝送同期端局設備 3…エコーキャンセラ装置 3a…エコーキャンセラ 3b…A/μ変換器 4…交換システム 4a…DCME制御部 4b…エコーキャンセラ装置制御部 4c…DCME・エコーキャンセラ装置制御部 Ia〜Id…DCMEと伝送同期端局設備との間の伝送
路 II…伝送同期端局設備とエコーキャンセラ装置との間の
伝送ハイウェイパス III …DCME制御用伝送ハイウェイパス IV…エコーキャンセラ装置制御用パス V…DCMEに入出力される外部との伝送路 VI…DCME及びエコーキャンセラ装置制御用伝送ハイ
ウェイパス
1 ... DCME 2 ... Transmission synchronous terminal equipment 3 ... Echo canceller device 3a ... Echo canceller 3b ... A / .mu. Converter 4 ... Switching system 4a ... DCME control unit 4b ... Echo canceller device control unit 4c ... DCME / echo canceller device control Parts Ia to Id ... Transmission line between DCME and transmission synchronization terminal equipment II ... Transmission highway path III between transmission synchronization terminal equipment and echo canceller device ... Transmission highway path IV for DCME control ... Echo canceller device control Path V ... Transmission path VI / DCM for input / output to / from the outside VI ... Transmission highway path for controlling DCME and echo canceller device

Claims (1)

【特許請求の範囲】 【請求項1】局間回線を収容する交換システムで回線上
のディジタル回線多重化装置,エコーキャンセラ,A/
μ変換器等の種々の回線処理装置を制御する場合におい
て、CCITT勧告Q.50 ANNEX Aに準拠す
る同一伝送路上の特定タイムスロット上のビットを用い
て制御信号を転送し、前記種々の回線処理装置を同一の
伝送路を用いて統一的に制御することを特徴とする回線
処理装置制御方式
Claim: What is claimed is: 1. A switching system accommodating an interoffice line, wherein a digital line multiplexer, an echo canceller, A /
When controlling various line processing devices such as μ converters, CCITT Recommendation Q. A line characterized in that the control signal is transferred using bits on a specific time slot on the same transmission line conforming to 50 ANNEX A, and the various line processing devices are uniformly controlled using the same transmission line. Processor control system
JP16062891A 1991-07-01 1991-07-01 Line processor control method Expired - Fee Related JP2935293B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16062891A JP2935293B2 (en) 1991-07-01 1991-07-01 Line processor control method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16062891A JP2935293B2 (en) 1991-07-01 1991-07-01 Line processor control method

Publications (2)

Publication Number Publication Date
JPH0514984A true JPH0514984A (en) 1993-01-22
JP2935293B2 JP2935293B2 (en) 1999-08-16

Family

ID=15719045

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16062891A Expired - Fee Related JP2935293B2 (en) 1991-07-01 1991-07-01 Line processor control method

Country Status (1)

Country Link
JP (1) JP2935293B2 (en)

Also Published As

Publication number Publication date
JP2935293B2 (en) 1999-08-16

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