JPH05146446A - Ultrasonic picture processor - Google Patents

Abstract

PURPOSE:To improve the visibility and operability by providing a histogram circuit preparing histogram information, retrieval comparison circuit obtaining a gradation value and a gain discrimination circuit controlling the amplification factor of the receiving signal of the ultrasonic diagnostic device. CONSTITUTION:This ultrasonic picture processor is provided with a histogram circuit 200 preparing histogram information while taking the gradation value of the picture to be displayed as the degree of the picture element with the gradation value, a retrieval comparison circuit 300 obtaining the gradation value being the class to which the median value belongs based on the histogram information, and a gain discrimination circuit 400 comparing the gradation value related to the median value with the reference value and controlling the amplification factor of the receiving signal of the ultrasonic diagnostic device cancelling the difference between them. The gain discrimination circuit 400 compares the gradation value related to the median value with the reference value, controlling the amplification factor of the gradation value related to the median value. Thus, the picture gradation can be automatically controlled while setting the optimum control target.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultrasonic image processing apparatus for performing image processing for displaying two-dimensional image information obtained by an ultrasonic diagnostic apparatus.

[0002]

2. Description of the Related Art An ultrasonic diagnostic apparatus has been conventionally known. This device is a device that transmits an ultrasonic wave to the inside of the living body from a probe brought into contact with the living body and obtains an image of the inside of the living body by a reflected wave. The probe usually includes an ultrasonic transducer formed of a piezoelectric material. By arranging the ultrasonic transducers in parallel or in a matrix and exciting the ultrasonic transducers selectively or with a delay, the ultrasonic wave transmission direction can be changed. By thus scanning the ultrasonic wave transmission direction, it is possible to obtain tomographic information of the living body.

The information obtained by the ultrasonic diagnostic apparatus needs to be easily understood by a user of the apparatus, for example, a medical staff such as a doctor. Therefore, a display device such as a CRT is an indispensable constituent member of the ultrasonic diagnostic apparatus. As described above, the display when obtaining the tomographic information of the living body is called the B mode display. Further, when displaying, it is usual to perform certain image processing on the obtained information, and therefore, an ultrasonic image processing apparatus is used.

[0004]

When displaying, a weak signal obtained by the probe is amplified to a required level in each part of the ultrasonic diagnostic apparatus. This level needs to be adjusted appropriately according to the site and depth to be observed. As a means for this, conventionally, for example, a user manually adjusts the gain of the amplifier while looking at the image, but in this case, the brightness of the image is not always optimum. That is, even if adjustment is made in a certain state to be optimal, it will be out of the optimal state in response to subsequent operations or changes in the state of the living body (for example, when the probe is moved to a site having a different fat thickness). I will end up. It is also possible to control the gain by feedback, but in this case,
There must be clear criteria for optimal adjustment. Otherwise, again, the optimum cannot be achieved.

The present invention has been made to solve the above problems, and it is possible to always display an image having an optimum darkness by automatically controlling the gain and to perform this processing. The goal is to be able to execute in real time.

[0006]

The inventor is examining what kind of image is the most visually recognizable image for humans in order to determine the optimum adjustment state standard. Figure 1
Shows a histogram representing a visually easy-to-see image that was revealed as a result of such examination. In the histogram of this figure, the horizontal axis is the gradation value and the vertical axis is the number of pixels having the gradation value. Here, the number of gradations is 2 ⁶ (6 bits), that is, 64, and the number of pixels is 128 × 5.
12 is set. FIG. 1 shows three types of histograms (1) to (3), all of which are close to a Gaussian distribution, and which are on the left and right sides across the 16th gradation. The areas are almost equal.

The present invention has been made paying attention to such a fact. That is, the present invention is an ultrasonic image processing apparatus that amplifies a received signal obtained by an ultrasonic diagnostic apparatus and then displays the image as a two-dimensional image. A histogram forming circuit that creates histogram information using the number of pixels as a frequency, a search and comparison circuit that obtains a gradation value that is a class to which the median value belongs based on the histogram information, and a gradation value related to the median value is compared with a reference value. And a gain determination circuit that controls the reception signal amplification factor of the ultrasonic diagnostic apparatus so as to eliminate the difference between the two.

According to a second aspect of the present invention, there is provided a frame memory for storing the gradation value of the image to be displayed for each pixel, and the histogram forming circuit stores the histogram information using the gradation value as an address and the frequency as data. A histogram reading counter for designating the read addresses from the storage means in ascending or descending order, means for accumulating the frequencies read from the storage means by designating the read addresses and accumulating the frequencies, and And a means for comparing the cumulative total with half the total number of pixels, wherein the gain determination circuit uses the read address when the cumulative total of the frequencies reaches half of the total number of pixels as the gradation value corresponding to the class to which the median value belongs. And a subtracter for obtaining the difference between the gradation value and the reference value related to the latch, and the difference for controlling the reception signal amplification factor. And means for outputting as the creation of the histogram information, the derivation of the tone value corresponding to the class the median value belongs, a comparison between the gradation value and the reference value,
It is characterized by pipeline processing.

[0009]

In the present invention, first, histogram information is created for the image to be displayed. In this histogram information, the gradation value is the class, and the number of pixels having the gradation value is the frequency. Next, based on the histogram information created in this way, the gradation value, which is the class to which the (total number of pixels / 2) th pixel is counted, in order from the pixel with the lowest or highest median value, that is, the gradation value Ask for. The gradation value should be a predetermined value when the display image is an image that is visually easy to see, that is, 16 in the example of FIG. In the present invention, the gain determination circuit compares the gradation value related to the median value with a reference value (for example, 16) and controls the reception signal amplification factor of the ultrasonic diagnostic apparatus so as to eliminate the difference between the two. As a result, the darkness of the image is automatically controlled while setting the optimum control target.

Further, in claim 2, this processing is executed as a pipeline processing, and the image display is performed on a real time basis. Specifically, first, the information on the display image is fetched from the frame memory, and the histogram information created based on this information is temporarily stored in the storage means.
The histogram read counter specifies the read addresses from this storage means in ascending or descending order. In the search / comparison circuit, the frequencies read from this address are accumulated while being latched. Furthermore, the cumulative total of the frequencies is compared with half the total number of pixels. If the result of this comparison indicates that the number of pixels has reached half, it can be considered that the median value has been reached, so the gain determination circuit uses the read address at that time as the gradation value corresponding to the class to which the median value belongs. To latch. The subtractor obtains the difference between the latched grayscale value and the reference value. This difference is output as a control error of the reception signal amplification factor.

With this arrangement, it is not necessary to retain the contents of the storage means after the reading from the storage means to the search / comparison circuit is completed. Therefore, the creation of the histogram information for the next screen can be started. On the other hand, it is possible to operate the gain determination circuit in parallel with the latch operation. Therefore, so-called pipeline processing is realized, and the operation time as a whole is shortened.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 shows the configuration of an ultrasonic image processing apparatus according to an embodiment of the present invention. This embodiment comprises an image holding circuit 100, a histogram forming circuit 200, a search / comparison circuit 300, and a gain judging circuit 400.

The image holding circuit 100 includes a frame memory 1
It is a circuit including. The frame memory 1 is a memory that stores an image to be displayed on a display (not shown) in screen (frame) units. On the frame memory 1, the image density is quantized for each pixel. When the quantization bit number is 6 bits, the number of gradations is 2 ⁶ = 64.

The histogram forming circuit 200 includes a RAM 2,
The increment circuit 3 and the latch circuit 4 are provided.
The RAM 2 has at least 64 memory locations according to the number of gradations, and is addressed by the output data of the frame memory 1 at the time of creating histogram information and by the count value of the histogram read counter 5 described later at the time of reading. .. Increment circuit 3
1 increments the data stored in the RAM 2, and the latch circuit 4 latches this and outputs it to the RAM 2.

The search / comparison circuit 300 includes a histogram read counter 5, an adder circuit 6, a latch circuit 7 and a comparator 9. The histogram read counter 5
A read address is generated by counting in a predetermined cycle when reading from the RAM 2. Adder circuit 6
Adds the frequency read from the RAM 2 to the value latched by the latch circuit 7. The latch circuit 7 latches the addition result of the addition circuit 6. The comparator 9 compares the value latched by the latch circuit 7 with a predetermined value, and outputs a signal when they match. The predetermined value is half the total number of pixels.

The gain judgment circuit 400 is composed of the latch circuit 1.
1, a subtractor 12 and a D / A converter 13. The latch circuit 11 latches the read address when the signal is received from the comparator 9. Subtractor 12
Compares the value latched in the latch circuit 11 with a reference value and obtains the difference. The D / A converter 13 converts this difference into an analog value. This analog value is supplied as an error signal to a reception signal amplification factor adjusting circuit (not shown).

The circuit of this embodiment has the function described above. Next, the operation of this embodiment will be described.

In this embodiment, the number of gradations is 2 ⁶ (6 bits) = 64 and the number of pixels is 128 × 512. The frame memory 1 stores image grayscale data for one frame. When creating a histogram, the RAM 2 is addressed by the data stored in this frame memory 1. That is, when the value stored as the gradation value of the pixel in the frame memory 1 is 16, the operation is such that the 16th address of the RAM 2 is addressed.

The data stored at this address is
It is fetched by the increment circuit 3 and incremented by 1. The result of the increment is the latch circuit 4
Are latched by and stored in the same address of RAM2. For example, if address 16 of RAM 2 is addressed and the content of that address is 10, the result of increment 11
Is stored at address 16.

When this operation is executed for all data on the frame memory 1, histogram information is stored in the RAM 2. That is, the histogram information is developed using the gradation value as an address and the number of pixels having the gradation value as data. However, it is assumed that the contents of the RAM 2 have been reset prior to creating the histogram.

After the histogram information is created in this way, the median value is derived. That is,
The histogram read counter 5 starts counting. Counting may be up-counting or down-counting, but up-counting is assumed here. The result of this counting is used as a read address from the RAM 2, and the read data, that is, the frequency of the histogram is input to the adder circuit 6. Specifically, first, since the count of the histogram read counter 5 starts from 0, the data at address 0 of the RAM 2 (the number of pixels having the gradation value 0) is input to the adder circuit 6. In this embodiment, since the latch circuit 7 is reset in advance, this data is latched in the latch circuit 7 as it is. Next, since the count value of the histogram read counter 5 becomes 1, the data at the first address of the RAM 2 (the number of pixels having the gradation value 1) is input to the adder circuit 6. In this case, the adder circuit 6 adds the value latched by the latch circuit 7 (the number of pixels having the gradation value 0) and the input from the RAM 2 (the number of pixels having the gradation value 1). The latch circuit 7 latches the result of this addition. Hereinafter, the same operation is continued.

The value obtained by such an operation is a value obtained by sequentially accumulating the frequencies of the histogram from the gradation value 0. This accumulated value is latched by the latch circuit 7.
On the other hand, based on the principle described above with reference to FIG. 1, it is necessary to know whether this cumulative value has reached the median value. In the present embodiment, this is detected by the comparator 9. That is, by comparing with the value of half of the total number of pixels, it is detected that the cumulative value of the value latched by the latch circuit 7 has reached half the area of the histogram.

The comparator 9 outputs a signal and gives it to the latch circuit 11 when it is recognized that the number of the signals reaches half as a result of the comparison.
The latch circuit 11 latches the present count value of the histogram read counter 5. This count value is a value indicating how many addresses in the RAM 2 the median value has been reached by accumulating the contents. 1 (1)-
In the case of the histogram shown in any of (3), this value is expected to be 16. The subtractor 12 uses the value actually latched and the reference value = 1.
6 is obtained and is supplied to the reception signal amplification factor adjusting circuit via the D / A converter 13.

As a result, the display image is always shown in FIG.
The image has a property similar to that of (3).
That is, the image is visually easy for humans to see. Moreover, this adjustment is performed automatically, which makes the operation of the user easier.

Further, in this embodiment, a series of complicated processes are performed on a real time basis. This is because the present embodiment performs pipeline processing. For example, the histogram formation circuit 200 and the gain determination circuit 400 can operate independently, and a plurality of operations will be executed in parallel at a certain time. This speeds up the process.

Although the case of 6-bit quantization has been described, it may be 8-bit quantization. In this case, since the number of gradations is 2 ⁸ = 256, the reference value is 1
It becomes 64 instead of 6.

[0028]

As described above, according to the present invention,
Since the histogram information is created and the received signal amplification factor is automatically controlled based on the median value, it is possible to set the optimal control target and adjust the image density constantly and automatically, improving the visual ease of viewing. The operability can be improved.

Further, according to the second aspect, since the pipeline processing is performed, the processing can be performed on a real-time basis, and the display with improved visibility can be quickly performed.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention, (1), (2)
And (3) are histograms showing types of gradation value distribution in an easily viewable image.

FIG. 2 is a block diagram showing a configuration of an ultrasonic image processing apparatus according to an embodiment of the present invention.

[Explanation of symbols]

 1 frame memory 2 RAM 3 increment circuit 4, 7, 11 latch circuit 5 histogram readout counter 6 adder circuit 9 comparator 12 subtractor 13 D / A converter 100 image holding circuit 200 histogram conversion circuit 300 search comparison circuit 400 gain judgment circuit

Claims (2)

[Claims] 1. An ultrasonic image processing apparatus for amplifying a received signal obtained by an ultrasonic diagnostic apparatus and displaying it as a two-dimensional image, wherein a gradation value of an image to be displayed is classified and a pixel having the gradation value. A histogram forming circuit that creates histogram information using the number as a frequency, a search and comparison circuit that obtains a gradation value that is a class to which the median value belongs based on the histogram information, and compares the gradation value related to the median value with a reference value, An ultrasonic image processing apparatus, comprising: a gain determination circuit that controls a reception signal amplification factor of the ultrasonic diagnostic apparatus so as to eliminate the difference between the two. 2. The ultrasonic image processing apparatus according to claim 1, further comprising: a frame memory that stores, for each pixel, a gradation value of an image to be displayed, wherein the histogram forming circuit stores the gradation value as an address and the frequency as data. And a histogram read counter for designating read addresses from the storage means in ascending or descending order by the search / comparison circuit.
The gain judgment circuit is provided with a means for accumulating the frequencies read from the storage means by designating the read address while latching the frequencies and a means for comparing the cumulative total of the frequencies with half the total number of pixels. A means for latching the read address when half the number of all pixels is reached as a gradation value corresponding to the class to which the median value belongs, a subtracter for obtaining the difference between the gradation value related to the latch and the reference value, Means for outputting the difference as a control target of the received signal amplification factor, and creating a histogram information, deriving a gradation value corresponding to the class to which the median value belongs, and comparing the gradation value with a reference value. An ultrasonic image processing device characterized by performing line processing.