JPH05145886A - Recording and reproducing device for television signal - Google Patents

Abstract

PURPOSE:To provide the recording and reproducing device for a high vision signal in which a television system conversion device is incorporated. CONSTITUTION:This recording and reproducing device which converts a video signal of a 1st television system into recording signals of plural channels through digital signal processing, records the recording signals of the channels on a recording medium, and reproduces the original video signal of the 1st television system through digital signal processing from the reproduced signals of plural channels from the recording medium. This device is provided with a means 40 which controls a data read of a frame memory used at the time of the digital signal processing in reproduction. Further, the device is provided with a means which converts the number of scanning lines of video signal data read out of the frame memory from the 1st television system to a 2nd television system which is less in the number of scanning lines.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recording / reproducing apparatus for a television signal of, for example, a high-definition system (HDTV system).

[0002]

2. Description of the Related Art A VTR (HD-V) for recording and reproducing high-definition (high-definition television) signals in a wide band and a high frequency band.
(Hereinafter referred to as TR), in order to reduce the frequency of the recording signal and narrow the frequency band for recording and reproduction,
A method of recording a signal for a unit time, for example, one frame by dividing it into a plurality of segments and a plurality of channels is used.

That is, the high-definition signal is a signal having 1125 horizontal scanning lines per 30 Hz per frame, but in the HD-VTR, the high-definition signal includes a luminance signal Y, a blue color difference signal PB and a red signal. Is input as a component signal of the color difference signal PR. And
The input luminance signal and color difference signal are
The digital signal is D-converted into a digital signal, which is subjected to digital signal processing such as time axis processing and color signal line sequential processing.

Then, the signals are divided into two channels, A and B, and a synchronization signal SYNC, a burst signal SB, etc., a color signal C, and a luminance signal Y are time-divided for each channel, as shown in FIG. TDM (TIME
DIVISION MATRIX) signal is converted into a continuous recording signal having a unit period H ^* and converted back to an analog signal.
The TDM waveform of FIG. 18 is a waveform after D / A conversion. Then, this analog signal is FM-modulated and recorded on the magnetic tape by the rotary head.

The TDM waveform is a unit signal of the recording signal of the high-definition signal, the input high-definition signal of the HD-VTR is divided into two channels as described above, and the color signals are line-sequential. As a result, the luminance signal and the color signal for one line have a period H that is almost twice as long.
It is time-division multiplexed within the period ^* .

As shown in FIG. 19, the one-frame high-definition signal converted into the above TDM signal forms a total of eight tracks by alternating A channel tracks TA and B channel tracks TB. Recorded on magnetic tape. It should be noted that one segment is recorded by a pair of the A channel track TA and the B channel track TB, and 4 segments SEG1, SE are recorded in one frame.
G2, SEG3, SEG4 are recorded.

By the way, it has been proposed that a standard television system which is now widely used, for example, a television receiver of the NTSC system can also reproduce a high-definition video signal. A system converter for converting a video signal into an NTSC system video signal has been proposed. So HD
-Reproduce the high-definition signal recorded by VTR, and
Viewing on a C type monitor receiver is HD-V
Input the playback output of TR to the system converter,
This is possible by obtaining the video signal of the system.

[0008]

However, the format converter has a frame memory and is very expensive. In addition, a system converter must be connected to the HD-VTR, which makes the system complicated.

In view of this point, an object of the present invention is to provide a recording / reproducing apparatus which is inexpensive and can simplify the system configuration.

[0010]

In order to solve the above-mentioned problems, the television signal recording / reproducing apparatus according to the present invention, when the reference numerals of the embodiments described later are made to correspond to each other, a video signal of the first television system is generated. The signals are converted into recording signals of a plurality of channels by digital signal processing, the recording signals of a plurality of channels are recorded on a recording medium, and the reproduction signals of the plurality of channels from the recording medium are processed by digital signal processing to the original first signal. In a recording / reproducing device for reproducing a video signal of a television system, a frame memory 38M used for digital signal processing at the time of reproducing.
Means 40 for controlling the reading of data from the first television system and the number of scanning lines of the video signal data read from the frame memory 38M.
It is characterized in that scanning line number converting means 51Y and 51C for converting for the second television system having a small number of scanning lines are provided.

[0011]

In the present invention having the above-mentioned structure, the reproduced recording signal is written in the frame memory 38M during reproduction. And this frame memory 3
The original 1st television system video signal is obtained from the data from 8M.

Further, when the video signal of the second television system is obtained as the reproduction output of the recording / reproducing apparatus, the read control for the frame memory 38M is changed to the second television system and the frame is also changed. The data read from the memory 38M is supplied to the scanning line number changing means 51Y and 51C for adjusting the scanning line number for the second television system. As a result, the video signal of the second television system can be directly obtained from the recording / reproducing apparatus.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a recording / reproducing apparatus according to the present invention will be described below as a recording / reproducing apparatus for a television signal of a high-definition system, and also for a television signal of an NTSC system.
An example of a device that can be taken out as a reproduction output will be described with reference to the drawings.

[Description of Rotary Head Device] FIG. 6 shows an example of a rotary head device used in the recording / reproducing apparatus of this example.

That is, an A channel head 1A having a first azimuth angle and a B channel head 1B having a second azimuth angle different from the first azimuth angle are
1 at the same rotation angle position of the rotary drum 3 in the direction of its rotation axis
It is attached by being offset by the track width. Similarly, the A channel head 2A having the first azimuth angle and the B channel head 2B having the second azimuth angle rotate the rotary drum 3 at a rotation angle position different by 180 ° from the heads 1A and 1B. It is attached by being offset by one track width in the axial direction.

The magnetic tape 4 is obliquely wound around the drum 3 over the angular range of 180 ° + α, and the rotary heads 1A, 1B, 2A, 2B are rotated at a rotational speed of 60 Hz. In the case of this example, the diameter of the drum 3 is, for example, 62 mm, the tape speed is 34.97 mm / s, and the track pitch is, for example, 15.11 mm.
It is said to be μm.

With the rotary head device having the above-mentioned structure, the rotary heads 1A and 1B and the rotary heads 2A and 2B are alternately arranged on the magnetic tape 4 at about 180 °.
In the tape contact section corresponding to the rotation angle, as shown in FIG. 19, eight oblique recording tracks are formed per frame and a high-definition signal is recorded.

[Explanation of Tape Pattern] That is, in one rotation, the rotary heads 1A and 1B make contact with the tape 4 in the first half of the rotation section of about 180 °.
And 1B, A channel tracks TA1 and B
The channel track TB1 is formed at the same time, and the rotary heads 2A and 2B contact the tape 4 in the latter half of about 180
In the rotation section, the rotary heads 2A and 2B form the A channel track TA2 and the B channel track TB2, and this is repeated alternately.

In this case, two rotary heads 1A and 1
B, or one segment is composed of two tracks formed simultaneously by the rotary heads 2A and 2B.
A video signal corresponding to 1/2 field and a signal obtained by PCM-converting an audio signal corresponding to the 1/2 field period related to the video signal are recorded in the segments with separate recording areas. And 4 tracks TA1, TB1, TA
2, TB2 for 1 field, 4 segment SEG1, SEG2,
A video signal and an audio signal of a high-definition signal for one frame are recorded by SEG3 and SEG4.

In this case, as described above, the video signal T is in a state where the luminance signal, the line-sequential signal of the color difference signal, and other additional signals are time division multiplexed within the unit period H ^* .
It is converted into a DM signal.

In the recording area of the video signal of each track, for example, the first 3 to 4H ^* minute area is used as a preamble area of the video signal. In this preamble area, a CW signal (PLL synchronization continuous wave signal) is provided. ), A segment synchronization signal V, a reference level signal L for applying AGC during reproduction, a ramp signal R for linearity correction, and the like are recorded.

[Description of Recording System] FIG. 7 is a block diagram of an embodiment of the recording system of the recording / reproducing apparatus of this example.

That is, the luminance signal Y of the high definition video signal is supplied to the A / D converter 13Y through the input terminal 11Y and the low pass filter 12Y, and is A / D converted at the sampling frequency f _YCK = 44.55 MHz. Are converted to digital signals. This digital signal is supplied to the vertical non-linear emphasis circuit 14 and subjected to vertical pre-emphasis.
It is supplied to the TDM encoder 15.

The blue color difference signal PB and the red color difference signal PR are supplied to the A / D converters 13B and 13R through the input terminals 11B and 11R, and the low pass filters 12B and 12R, respectively. A / D conversion is performed at a sampling frequency f _CCK = 11.1375 MHz which is ¼ of the sampling frequency of the video signal, and each is converted into a digital signal. And
Each digital color difference signal is supplied to the vertical non-linear emphasis circuit 17 via the vertical filter 16 and subjected to vertical pre-emphasis, and then supplied to the TDM encoder 15.

In this TDM encoder 15, a TDM signal is formed by a time axis process, a line sequential process of chrominance signals, etc. by a clock having a frequency f _TCK phase-locked with a sampling clock of a luminance signal, for example f _TCK = 30.753 MHz. To do. In this case, the luminance signal Y of the horizontal cycle H of the original high-definition signal is the sampling frequency f.
_The luminance data sampled by _YCK and converted into a digital signal is divided into, for example, an odd-numbered horizontal section signal and an even-numbered horizontal section signal, and the digital data of the color difference signals PB and PR is, for example, Blue-color difference signal data is odd-numbered luminance signal data, red color-difference signal data is even-numbered luminance signal data, and so on.

Output TD from this TDM encoder 15
The M data is supplied to a digital signal processing circuit 38 of a reproducing system, which will be described later, via the switch circuit EE, and is also supplied to the digital signal processing device 18 including a frame memory composed of, for example, four video memories.

In this digital signal processing device 18, 1H
^* TDM data units so that the order on the tape pattern, is read from the frame memory in the order that they are changed to the original order. Then, at the time of this reading, TDM
The data is divided into two channels A and B.

The data of the respective channels A and B from the digital signal processing circuit 18 are supplied to the horizontal non-linear emphasis circuits 19A and 19B, respectively, and subjected to horizontal pre-emphasis. The output signals of the horizontal non-linear emphasis circuits 19A and 19B are supplied to the adder circuits 20A and 20B, and in these adder circuits 20A and 20B, the sync signal from the sync signal generation circuit 21 (different from the sync signal in the video signal). SYNC, burst signal SB, etc. are added to the signal of each channel.

The outputs of the adder circuits 20A and 205B are D
D / A supplied to the A / A converters 22A and 22B.
The TD including the sync signal SYNC, the burst signal SB, etc., the color signal C, the luminance signal Y, etc. as shown in FIG. 18 is converted from the D / A converters 22A and 22B.
A signal of M waveform is obtained.

This signal is supplied to the low pass filter 2 respectively.
TDM emphasis circuit 24A through 3A and 23B
And 24B to be subjected to pre-emphasis processing, and then supplied to the FM modulation circuits 25A and 25B to be subjected to FM.
Is modulated. The A channel FM modulated video signal from the FM modulation circuit 25A is supplied to the video input terminal a of the switch circuit 26A, and the FM modulation circuit 25B is also supplied.
The B-channel FM-modulated video signal from is supplied to the video input terminal a of the switch circuit 26B.

On the other hand, the first and second input terminals 28L are connected to each other.
The audio signal of the channel is input. Also, input terminal 2
Audio signals of the third and fourth channels are input to 8R. These two-channel audio signals are supplied to the audio digital processor 27 to be PCM audio data, distributed to A and B2 channels, and supplied to the audio input terminals b of the switch circuits 26A and 26B.

Then, the output signals of the switch circuits 26A and 26B are supplied to the A channel heads 1A and 2A and the B channel heads 1B and 2B via the recording amplifiers 29A and 29B, respectively, and the heads mentioned above print on the tape. The recorded track pattern is formed and recorded.

[Description of Playback System] Next, an embodiment of the playback system of the recording / playback apparatus of this example will be described.

1 and 2 are block diagrams of an embodiment of the reproducing system of the present invention. As shown in FIGS. 1 and 2, the reproduction signal of the A channel from the A channel rotary heads 1A and 2A is supplied to the reproduction amplifier 31A, and similarly, the reproduction signal of the B channel from the B channel rotary heads 1B and 2B. Is supplied to the reproduction amplifier 31B.

In this case, the reproduction amplifier 31A obtains the reproduction video signal of the A channel from the video signal recording area of the tracks TA1 and TA2 and the reproduction PCM audio data of the A channel from the PCM audio recording area. From 31B, B channel reproduced video signals from the video signal recording areas of tracks TB1 and TB2 and B channel reproduced PCM audio data from the PCM audio recording areas of the same tracks TB1 and TB2 are obtained.

The playback PCM audio data of the A channel and the B channel from the playback amplifiers 31A and 31B are supplied to the audio digital processor 62 through the audio playback equalizer circuit 61 and restored to the original analog audio signal. It is led to the output terminals 63L and 63R.

Further, the reproduced video signals of the A channel and the B channel from the reproduction amplifiers 31A and 31B are F through the reproduction equalizer circuits 32A and 32B, respectively.
After being supplied to the M demodulation circuits 33A and 33B for FM demodulation, they are supplied to the TDM de-emphasis circuits 34A and 34B for de-emphasis processing.

The de-emphasis circuits 34A and 34
The output signal of B is supplied to the A / D converters 36A and 36B via the low-pass filters 35A and 35B, respectively, and after being converted into a digital signal, is supplied to the horizontal non-linear de-emphasis circuits 37A and 37B for horizontal Direction de-emphasis processing is performed. This horizontal non-linear de-emphasis circuit 37A and 37
The output signal of B is supplied to the digital signal processing circuit 38 including a frame memory including, for example, four video memories.

Further, the TD of the recording system is set through the switch EE.
The TDM signal from the M encoder 15 is supplied to the digital signal processing circuit 38. This is for monitoring the recording signal.

In addition, A / D converters 36A and 36B
Is supplied to the PLL circuits 39A and 39B,
A write clock synchronized with the CW signal in the preamble area of each track is obtained from these PLL circuits 39A and 39B. These write clocks are supplied to the address controller 40, respectively. The address controller 40 is for controlling the write and read addresses of the frame memory of the digital signal processing circuit 38. Then, the output data of the horizontal non-linear de-emphasis circuits 37A and 37B are written in the frame memory under the control of the write address controller driven by the above-mentioned write clock.

The digital signal processing circuit 38 performs a de-shuffling process for returning the order of the data written in the frame memory to the original order.

Then, the address controller 40 has
Select signals SE1, SE2, S from the select signal generating circuit 41 according to the television system and the screen display system.
E3 is supplied, whereby the read address for the frame memory is switched and controlled. The select signal generating circuit 41 is supplied with a signal according to a key input from a select key of a television system and a select key of a screen display system, which are not shown,
As a result, output select signals SE1, SE2, SE3 and switching signals SW1, SW2 described later are formed.

FIG. 3 is a block diagram showing an example of the configuration of the address controller 40. As shown in FIG. 3, the address controller 40 has a write address controller 401.
01, PLL circuit 3 of A channel and B channel
The write clock from 9A and 39B is supplied.
Then, the frame memory 3 of the digital signal processing circuit 38
8M is address-controlled by the write address controller 401, and the A channel and B channel video data from the horizontal non-linear de-emphasis circuits 37A and 37B are written.

In the case of this example, not only the high-definition video signal is obtained as an output signal, but also the NTSC video signal is obtained from the high-definition video signal. , As a read address controller,
Read address controller 4 for D (high definition)
06 is provided, and two read address controllers 407 and 408 for NTSC are provided.

A plurality of read address controllers are provided for NTSC because the HDTV signals are sent to NT.
When displaying on an SC type monitor receiver, the difference in aspect ratio between them (16: 9, N
In the TSC method, a screen display method in consideration of 4: 3) can be adopted, so that it is possible to cope with the difference in the screen display methods, and this example is called a so-called side panel method. It is designed to be compatible with a screen display system and a screen display system called a letterbox system.

That is, FIG. 4 is a diagram for explaining the side panel system. The area surrounded by the frame line 71 is the display screen area of the NTSC system monitor receiver, and the area surrounded by the frame line 72 is the display screen area of the high-definition signal. Is. In the case of the side panel method, the vertical area of the high-definition display screen is the same as that of the NTSC method, and the left and right sides of the high-definition display screen area shown by hatching in the figure are of the NTSC method. It does not appear on the monitor receiver display screen.

FIG. 5 is a diagram for explaining the letterbox system. An area surrounded by a frame line 71 is a display screen area of an NTSC system monitor receiver, and an area surrounded by a frame line 72 is a high vision system display screen. Area. In this letterbox method, the entire high-definition display screen fits within the display screen of the NTSC monitor receiver. As shown by the shaded areas in the figure, the upper and lower sides of the display screen of the NTSC monitor receiver There is a non-display area at.

Here, the number of effective lines per frame of the high-definition signal is 1035, and that of the NTSC system is 483. Therefore, when converting a high-definition signal to an NTSC signal, it is necessary to thin out the number of lines. Then, in order to prevent so-called aliasing distortion due to the thinning-out process, a vertical filter is used as described later in this example.

In the case of the side panel system, 483 lines, which is the number of effective lines in the NTSC system, are required, so the number of lines may be set to about 1/2 of the high definition signal. 1
In the case of setting to / 2, 966 out of the effective lines of the high-definition signal are read from the frame memory, the processing for removing the aliasing distortion is performed by the vertical filter, and then thinned to 1/2. At this time, in the horizontal direction, only the area required for display needs to be read.

In this case, the reading speed needs to be about twice as high as that when reading the high-definition signal as the reproduction output. The side panel read address controller 407 supplies a read control signal for obtaining the side panel type display screen type NTSC signal to the frame memory 38M via the OR gate 409.

On the other hand, in the case of the letterbox system, the number of lines required for display is 10 in the high definition system.
It may be 35, for example, 345, which is 1/3. In this case, since all the effective lines of the high-definition signal are required, the reading speed needs to be about three times as high as when reading the high-definition signal as the reproduction output. The letterbox read address controller 408 supplies a read control signal for obtaining the above-mentioned letterbox type display screen type NTSC signal to the frame memory 38M via the OR gate 409.

Each read speed depends on the frequency of the read clock signal. In this example, the reference clock from the reference clock generation circuit 402 is HD.
Read clock forming circuit 403, side panel read clock forming circuit 404, and letterbox read clock forming circuit 405.

The output clock of the HD read clock forming circuit 403 is supplied to the HD read address controller 406. Further, the side panel read clock forming circuit 404 obtains a clock having a frequency about twice as high as the HD read clock, and this clock is supplied to the side panel read address controller 407. Further, from the letterbox read clock forming circuit 405, about 3 times the HD read clock is output.
A clock having a doubled frequency is obtained and supplied to the letterbox read address controller 408.

When the high definition system is selected by the select switch, only the HD read address controller 406 is enabled by the select signal SE1 from the select signal generating circuit 41.
Further, when the NTSC side panel system is selected, only the side panel read address controller 407 is enabled by the select signal SE2 from the select signal generating circuit 41. Furthermore, NTS
When the C letterbox method is selected, the letterbox read address controller 40 is activated by the select signal SE3 from the select signal generation circuit 41.
Only 8 are enabled.

The output signal of the digital signal processing circuit 38 read from the frame memory 38M is supplied to the TDM decoder 42. In this TDM decoder 42, the TD
Processing (including time axis processing) for converting the M signal into the luminance signal and the color difference signals of blue and red is performed. And this T
The luminance signal and the color difference signal from the DM decoder 42 are supplied to the dropout correction circuit 43, and when a dropout is detected in the signal, dropout correction processing is performed.

The luminance signal data from the dropout correction circuit 43 is supplied to the switch circuit 45Y after being subjected to vertical de-emphasis processing by the vertical non-linear de-emphasis circuit 44Y. The color difference signal data from the dropout correction circuit 43 is
The vertical non-linear de-emphasis circuit 44C performs vertical de-emphasis processing, and then supplies the de-emphasis processing to the switch circuit 45C.

These switch circuits 45Y and 45C are
The signal is switched by the switching signal SW1 from the select signal generation circuit 41, and is switched to the terminal HD side when a high-definition system signal is obtained as a reproduction output.
When the signal of the C system is obtained, it is switched to the terminal NT side.

When a high-definition system signal is obtained as the reproduction output, the luminance signal data from the vertical non-linear de-emphasis circuit 44Y is supplied to the D / A converter 47Y via the switch circuit 45Y and the analog signal is supplied. Then, the reproduction luminance signal Y is obtained at the output terminal 49Y through the low pass filter 48Y. In addition, the color difference signal data from the vertical non-linear de-emphasis 44C is passed through the switch circuit 45C to the vertical filter 4
6 is supplied. Then, the blue color difference signal data and the red color difference signal data are obtained from the vertical filter 46, supplied to the D / A converters 47B and 47R, respectively, and returned to analog signals, and the low pass filters 48B and 48B.
Through R, output color difference signals PB and PR of blue and red are obtained at output terminals 49B and 49R.

Further, when an NTSC system signal is obtained as the reproduction output, the luminance signal data from the vertical non-linear de-emphasis circuit 44Y is supplied to the switch circuit 45Y.
Is supplied to the Y down converter 51Y via. Further, the color difference signal data from the vertical non-linear de-emphasis circuit 44C is supplied to the C down converter 51C via the switch circuit 45C. The down converters 51Y and 51C include the select signal forming circuit 4
The switching signal SW2 from 1 is supplied, and the down-conversion system for converting the number of lines from the high-definition system to the NTSC system is switched between the side panel system and the letterbox system.

FIG. 8 shows an example of a circuit configuration selected by the Y down converter circuit 51Y in the case of the side panel system. That is, the luminance signal data Y1 (FIG. 10A) of the high-definition signal that has passed through the input terminal 101 is the input terminal a of the switch circuit 102 and the switch circuit 103.
Is supplied to the other input terminal b of the above and is also supplied to the delay circuit 104 of 1H ^* . Output Y2 of this delay circuit 104
(FIG. 10B) is further supplied to the 1H ^* delay circuit 105. The output Y3 (FIG. 10C) of this delay circuit 105 is
It is supplied to the other input end b of the switch circuit 102 and one input end a of the switch circuit 103. The switch circuits 102 and 103 are alternately switched to one input terminal a and the other input terminal b for each field by the switching signal FL.

The output of the switch circuit 102 is weighted 3/8 times by the weighting circuit 106 and then supplied to the adding circuit 109. The output of the delay circuit 104 is weighted by ½ by the weighting circuit 107 and then supplied to the adding circuit 109. Further, the output of the switch circuit 108 is 1/8 by the weighting circuit 108.
After being weighted twice, it is supplied to the adder circuit 109.

Output YM of this adder circuit 109 (FIG. 10D)
Is supplied to the time base expansion circuit 110 having a line memory. The write enable signal WEN1 (FIG. 10F) from the terminal 111 is supplied to the line memory of the time axis expansion circuit 110, and the line memory outputs 1H ^* every 2H ^{* .}
Only writable. Then, during the writable period (the high level period of the signal WEN1 in the example of FIG. 10), the write clock WCK1 from the terminal 112 (see FIG.
0E), the output of the adder circuit 109 is written in the line memory, whereby 1/2 line thinning is performed (FIG. 10G).

Then, by the read clock RCK1 (FIG. 10H) from the terminal 113, the time is extended approximately twice,
Luminance signal data Yn (Fig. 10I) is read out, and NTSC
The read output signal is output to the output terminal 114 so as to match the horizontal cycle of the system.

According to the circuit of FIG. 8, 1/2 thinning-out as shown in FIG. 9 is performed. That is, in the m field, the above-described weighting is applied to each three adjacent lines of the high-definition signal indicated by the solid line on the left side in FIG. When applied, an m-field line of the NTSC system signal is obtained at the spatial position shown by the solid line in the center of FIG. Similarly, in the m + 1 field, vertical filter processing is performed by weighting each of the three lines of the high-definition signal indicated by the broken line on the left side in FIG. Lines are thinned to obtain a line of the m + 1 field of the NTSC system signal at a spatial position shown by a broken line in the center of FIG.

FIG. 11 shows C in the case of the side panel system.
It is an example of a circuit configuration selected in the down converter 51C. In this case, the signal input to the C down converter 51C is a line-sequential signal in which blue and red color difference signals are alternately obtained every 1H ^* . Also in this color difference signal, similarly to the luminance signal, as shown in FIG. 12, the blue color difference signal obtains one line from three lines, and the red color difference signal obtains one line from two lines. By obtaining it, so-called aliasing distortion can be removed. That is, in this example, the HDTV signals of adjacent 5 lines are used.

Therefore, in this example, the input terminal 1
Color difference signal data C1 (FIG. 13A) through 21 is 1H ^*
Are sequentially supplied to the delay circuits 122, 123, 124, 125. Therefore, from the delay circuit 122, the signal C2 (FIG. 13) obtained by delaying the input color difference signal data by 1H ^* is input.
B) is obtained, a signal C3 (FIG. 13C) obtained by delaying the input color difference signal data by 2H ^* is obtained from the delay circuit 123, and the input color difference signal data is 3H from the delay circuit 124.
A signal C4 (FIG. 13D) delayed by ^* is obtained, and a signal C5 (FIG. 13E) obtained by delaying the input color difference signal data by 4H ^* is obtained from the delay circuit 125.

The color difference signal data C1 from the input terminal 121 is multiplied by ¼ by the weighting circuit 126 and then supplied to the adding circuit 131B, and the delay circuit 12 is also provided.
The output color difference signal data C3 of 3 is multiplied by 1/2 by the weighting circuit 128 and then supplied to the addition circuit 131B, and the output color difference signal data C5 of the delay circuit 125 is multiplied by 1/4 by the weighting circuit 130. After that, the adder circuit 131
Supplied to B.

As a result, 1H is output from the adder circuit 131B.
^* Additional output data CM1 (Fig. 13F) that obtains the addition output of only the blue color difference signal data of three lines is obtained every
This is supplied to the time axis expansion circuit 132B having a line memory. The line memory of the time axis expansion circuit 132B has a write enable signal WE from the terminal 133B.
N2 (FIG. 13G) is supplied, and the line memory is writable by 1H ^{* for} every 2H ^* . Then, in the writable period (high level period of the signal WEN2 in the example of FIG. 13), the write clock WC from the terminal 134B
The output of the adder circuit 131B is written in the line memory by K2, and 1/2 line thinning is performed by this, and blue color difference signal data CB (FIG. 13H) is obtained.

Then, by the read clock RCK2 from the terminal 135B, the color difference signal data CBn of blue is read out by being time-expanded to about twice (FIG. 13I), and made to match the horizontal period of the NTSC system. The read output signal is output to the output terminal 136B.

The output color difference signal data C2 of the delay circuit 122 is supplied to the addition circuit 131R via the weighting circuit 127, and the output color difference signal data C4 of the delay circuit 124 is supplied to the addition circuit 131R via the weighting circuit 129. Supplied.

From the adder circuit 131R, adder output data CM2 (FIG. 13J) is obtained which gives an adder output of only the blue color difference signal data of three lines every 1H ^* , which is a time axis expansion circuit having a line memory. It is supplied to 132R. The line memory of the time axis expansion circuit 132R has a write enable signal WEN2 from the terminal 133R.
(Fig. 13G) is supplied and the line memory is set to 1 every 2H ^*.
Only H ^{* is} writable. Then, in the writable period, the output of the adder circuit 131R is written to the line memory by the write clock WCK2 from the terminal 134R, whereby 1/2 line thinning is performed and red color difference signal data CR (FIG. 13K) is obtained. can get.

Then, by the read clock RCK2 from the terminal 135R, the color difference signal data CRn of red is read out by being time-expanded to about twice (FIG. 13L), and is made to match the horizontal period of the NTSC system. The read output signal is output to the output terminal 136R.

FIG. 14 shows an example of a circuit configuration selected by the Y down converter circuit 51Y in the case of the letter box system. In this case, as shown in FIG.
By obtaining the luminance signal data for one line of the NTSC system from the luminance signal data of three adjacent lines, so-called aliasing distortion can be removed.

That is, the luminance signal data Y1 of the high-definition signal through the input terminal 141 is the 1H ^* delay circuit 14
2, 143 are sequentially supplied. Therefore, the delay circuit 142 obtains the signal Y2 in which the input luminance signal data is delayed by 1H ^* , and the delay circuit 143 obtains the signal Y3 in which the input luminance signal data is delayed by 2H ^* .

Then, the luminance signal data Y1 from the input terminal 141 is supplied to the adder circuit 147 after being multiplied by ¼ by the weighting circuit 144, and also the delay circuit 142.
The output luminance signal data Y2 of 1 is set to 1 by the weighting circuit 145.
After being multiplied by / 2, it is supplied to the adding circuit 147, and the output luminance signal data Y3 of the delay circuit 143 is also multiplied by ¼ by the weighting circuit 146 and then supplied to the adding circuit 147.

The output YM of the adder circuit 147 is supplied to the time axis expansion circuit 148 having a line memory. The line memory of the time axis expansion circuit 148 includes a terminal 149.
The write enable signal WEN3 is supplied to the line memory, and the line memory becomes writable by 1H ^* every 3H ^* . Then, during the writable period, the terminal 15
The output of the adder circuit 147 is written in the line memory by the write clock WCK3 from 0, whereby the 1/3 line thinning is performed.

Then, by the read clock RCK3 from the terminal 151, the luminance signal data Yn is read out by being time-extended to about 3 times, and the read signal is output so as to match the horizontal period of the NTSC system. It is led to the terminal 152.

According to the circuit of FIG. 14, 1/3 line thinning is performed as shown in FIG. That is, the above-described weighting is applied to each of the three adjacent lines of the high-definition signal, the vertical filtering process is performed, and the ⅓ line thinning is performed, as shown by the solid line in the center of FIG. An m-field line of an NTSC luminance signal can be obtained at a spatial position. Further, similarly, in the m + 1 field, FIG.
In FIG. 15, the three lines of the high-definition signal indicated by the broken lines on the left side are weighted as shown in the figure, vertical filtering is performed, and further ⅓ line thinning is performed. Lines of the m + 1 field of the NTSC luminance signal are obtained at the spatial positions as shown.

The 1H ^* delay circuits 142 and 143 are provided.
Can be shared with the side panel type delay circuits 104 and 105.

FIG. 16 shows the case of the letter box method.
It is an example of a circuit configuration selected in the C down converter 51C. In this case, for the blue and red color difference signals, 1/3 line thinning processing is performed. However, as shown in FIG. 17, when the blue and red color difference signals form one line from three lines. By alternately switching between the case of forming one line from two lines and the case of forming one line for each NTSC horizontal cycle, the color difference signal data of each color is continuously obtained.

In the example of FIG. 16, the input terminal 161
To 1H ^* delay circuits 162 to 165, weighting circuits 166 to 170, and addition circuits 171 and 172, the circuit configuration from the input terminal 121 of the side panel C down converter circuit 51C to the addition circuit 131R.
And 131B can be shared exactly the same as the circuit configuration.

Also, the time axis expansion circuits 173 and 174.
Can also be shared with the time axis expansion circuits 132R and 132B of the side panel C down converter circuit 51C of FIG. 11, the write enable signal for each of the line memories is the signal WEN3, and the write operation is performed. The clock is the clock WCK3, and the read clock is the clock RCK3. Therefore, 1
The data is written in the line memory by thinning out / 3 lines, and the time axis is tripled and read out.

The output of the time axis expansion circuit 173 is supplied to one input terminal a of the switch circuit 175 and the other input terminal b of the switch circuit 176. Further, the output of the time axis expansion circuit 174 is supplied to the other input terminal b of the switch circuit 175 and is also supplied to one input terminal a of the switch circuit 176. Then, these switch circuits 175 and 176 are connected to the switching signal SW.
By H, one input terminal a and the other input terminal b are switched for each horizontal period of the NTSC system. And
Red color difference signal data CRn is obtained from the switch circuit 175 and is output to the output terminal 177. Blue color difference signal data CBn is obtained from the switch circuit 176 and is output to the output terminal 178.

As described above, the line of the color difference signal data of the m field of the NTSC system is obtained at the spatial position shown by the solid line in the center of FIG. 17, and the line of the m + 1 field of the NTSC system is shown at the spatial position shown by the broken line. A line of color difference signal data is obtained.

As described above, the Y down converter 51
The luminance signal data Yn obtained from Y is converted into an analog signal by the D / A converter 52Y, and the NTSC luminance signal is HD → NT through the low-pass filter 53Y.
It is supplied to the SC matrix circuit 54.

Further, the blue and red color difference signal data CBn and CRn from the C down converter circuit 51C are supplied to the D / A converters 52B and 52R, respectively, and converted back to analog signals, and the low pass filters 53B and 53R.
The blue and red color difference signals PB and PR are HD → NT via
It is supplied to the SC matrix circuit 54. Then, the output of the matrix circuit 54 is supplied to the NTSC encoder 55, from which a video signal of an NTSC television signal is obtained, which is led to the output terminal 56.

As described above, the switch 45 is used during reproduction.
By switching between Y and 45C, a high-definition video signal reproduction output can be obtained and this can be changed to NTS.
A video signal converted into the C system can be obtained.

By turning on the switch EE, the input signal to be recorded can be monitored by the monitor receiver before recording. At this time, switch 45Y
The recording input signal to be monitored can be output as a high-definition video signal or as a video signal converted to the NTSC system by switching between 45C and 45C, so that any monitor receiver can monitor. be able to.

In the above example, the case of converting from the high-definition system to the NTSC system has been described, but the present invention is also applicable to the case of converting from the high-definition system to the PAL system or the SECAM system.

[0090]

As described above, according to the present invention, a circuit for converting a high-definition video signal into, for example, the NTSC system is provided in the recording / reproducing apparatus, so that the conventional high-definition system → NTSC system. There is no need to prepare a conversion adapter in addition to the recording / reproducing device.

Further, according to the present invention, since the address for the frame memory used when reproducing the high-definition signal is also used for conversion into the signal of the NTSC system, the structure is simplified. At the same time, it is cheaper than the case where a method conversion adapter is separately prepared.

Further, according to the present invention, for example, the high-definition system is converted to the NTSC system, and the conversion result NT is obtained.
When displaying the SC system signal on the monitor receiver, two types of image display systems, a side pulse system and a letter box system, can be switched and selected.

[Brief description of drawings]

FIG. 1 is a block diagram of a part of a reproducing system of an embodiment of a recording / reproducing apparatus according to the present invention.

FIG. 2 is a block diagram of the rest of the reproducing system of the embodiment of the recording / reproducing apparatus according to the present invention.

FIG. 3 is a block of an example of a main part of a reproduction system.

FIG. 4 is a diagram for explaining a side panel system of an image display system.

FIG. 5 is a diagram for explaining a letterbox method of an image display method.

FIG. 6 is a diagram showing a rotary head device used in an embodiment of a recording / reproducing device according to the present invention.

FIG. 7 is a block diagram of a recording system of an embodiment of a recording / reproducing apparatus according to the present invention.

FIG. 8 is a circuit diagram of an example of a reproduction system Y down converter 51Y.

9 is a diagram used for explaining the conversion operation of FIG. 8; FIG.

10 is a time chart for explaining the conversion operation of FIG.

FIG. 11 is a circuit diagram of an example of a reproduction system C down converter 51C.

FIG. 12 is a diagram used to explain the conversion operation of FIG. 11;

13 is a time chart for explaining the conversion operation of FIG.

FIG. 14 is a circuit diagram of another example of the reproduction system Y down converter 51Y.

FIG. 15 is a diagram used for explaining the conversion operation of FIG. 14;

FIG. 16 is a circuit diagram of another example of the reproduction system C down converter 51C.

FIG. 17 is a diagram used to explain the conversion operation of FIG. 16;

FIG. 18 is a diagram for explaining a TDM waveform.

FIG. 19 is a diagram for explaining a recording track pattern formed by a high-definition signal recording / reproducing apparatus.

[Explanation of symbols]

 1A, 2A A channel rotary head 1B, 2B B channel rotary head 13Y, 13B, 13R A / D converter 22A, 22B D / A converter 36A, 36B A / D converter 45Y, 45C Switch circuit 15 TDM encoder 18 Digital signal Processing circuit 38 Digital signal processing circuit 40 Address controller 41 Select signal generation circuit 42 TDM decoder 38M frame memory 51Y Y down converter 51C C down converter

Claims (3)

[Claims] 1. A video signal of the first television system is converted into recording signals of a plurality of channels by digital signal processing, the recording signals of a plurality of channels are recorded on a recording medium, and a plurality of channels from the recording medium are recorded. In the recording / reproducing apparatus in which the original video signal of the first television system is reproduced from the reproduced signal of 1. by the digital signal processing, the reading of data from the frame memory used in the digital signal processing during the reproduction is controlled. And a means for converting the number of scanning lines of the video signal data read from the frame memory from that of the first television system to that of the second television system having a smaller number of scanning lines. Signal recording / reproducing device. 2. The screen of the second television system,
The aspect ratio is different from that of the screen of the first television system, the video signal of the first television system is converted into the video signal of the second television system, and this is converted into the second television. When displaying on a display for a television system, it is possible to display in a plurality of screen forms, and the control of reading the frame memory is switched depending on the difference between the first and second television systems. The television signal recording / reproducing apparatus according to claim 1, wherein the television signal recording / reproducing apparatus is adapted to be switched depending on a plurality of screen types of the second television system. 3. A means for directly supplying and writing the digital signal of the recording signal of the video signal of the first television system to the frame memory of the reproduction signal system, and reading from the frame memory The video signal of the first television system selectively from the recorded data,
2. The television signal recording / reproducing apparatus according to claim 1, wherein the second television system video signal is obtained.