JPH05145750A - Picture character separating circuit of color image processor - Google Patents

Abstract

PURPOSE:To provide the picture character separating circuit of a color image processor for improving a discrimination performance by a compact blocking means, and also, to facilitate a timing design. CONSTITUTION:The circuit is provided with a data input switching means 2 for executing switching control to a mode for executing an input of data at every line and a mode for executing its input every other line, a blocking means 1 for blocking the data inputted in accordance with the control of the switching means 2, and an area discriminating means 3 for discriminating an area by the blocked data. Also, the block size is set to width power of 2, and the area discriminating means 3 has a timing adjusting means 4 consisting of a line buffer, and controls a readout timing of a line buffer so that a timing for outputting an area discriminating signal is synchronized with a line signal. In such a way, a block whose size is substantially larger than size of the blocking means can be adopted in accordance with necessity, and an averaging processing of block data can be executed by only a bit shift. Also, an internal delay can be adjusted simply.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pictographic character separation circuit of an image processing apparatus for processing a color image signal by dividing a plurality of pixels into blocks to identify a character or halftone area and switching parameters according to the area identification signal. ..

[0002]

2. Description of the Related Art In a color image processing apparatus such as a color copying machine, Y (yellow), M (magenta), C (cyan),
A four-color toner developing device of K (black) is used, and these images are superposed to reproduce a full-color image. Therefore, scanning is repeated four times according to the developing process of each toner, and the full-color image data obtained by reading the original is processed each time.

FIG. 10 is a diagram showing a configuration example of a conventional color image processing device and a configuration example of an image area identification circuit.

Generally, in a color image processing apparatus, an original is optically read by using a line sensor, and B (blue) and G are read.
When the image data is taken in by the color separation signals of (green) and R (red), the image data is converted into E as shown in FIG.
After adjusting the gray balance by the ND conversion 31, the color masking (color correction) 32 converts the color separation signal BGR into the color material signal YMC. Then, the UCR 33 performs black plate (K) generation and undercolor removal, and the hue separation type non-linear filter section removes moire and halftone dots and edge enhancement, and TRC (tone adjustment) 40, SG
Through the (screen generator) 41, the color material signal X expressed in multiple gradations of the development color is turned into on / off binary data, and the laser light is controlled by this binary data to expose the charged photoconductor. An image of each color is formed.

In the color separation type non-linear filter unit, the UCR
In 33, the image data X of the development color is selected and input according to the development process from the YMCK signal generated by performing black plate generation and undercolor removal processing, and branched into two systems. A smoothing filter 34 is connected to one of them, and a γ conversion circuit 36, an edge detection filter 37, and an edge enhancement LUT 35 are connected to the other. The former system performs smoothing processing for removing moire and halftone dots on the halftone image, and the latter system performs edge enhancement processing on the character image. The adder 39 synthesizes these outputs, and the synthesized signal is output as a signal after the nonlinear filter processing. In this case, in the edge processing, the hue of the input image is detected by the hue detection circuit 35,
It is determined whether the development color at that time is a required color. Here, if the input image is a black area, Y, M, C
No edge enhancement of the chromatic color signal is performed, and only K is controlled to be enhanced according to the edge amount.

By introducing the non-linear filter processing as described above, binary images such as characters and line drawings of different types and binary images such as characters and line drawings for originals such as photographs and halftone dot prints are Non-linear filter processing to enhance the sharpness by emphasizing edges and smoothing halftone images such as photographs and halftone dot prints to remove moire and halftone dots to enhance image smoothness and graininess. It is carried out.

However, in the case of a binary image such as a character or a line drawing and a halftone image such as a photograph or a halftone dot printed matter, if it is easy to specify each original or area in advance, it is possible to specify each original or area. By specifying the image type for each area, it is possible to select the optimum parameters for each area and improve the reproducibility. However, in the case of these mixed images, it can be used as a binary image or a halftone image. Also, parameters that can be reproduced as such will be selected. In this case, the optimum processing is not performed on the binary image or the halftone image, so that it is difficult to obtain an image that is satisfactory for both.

For example, in a binary image, the edge emphasis is weak and blurred, so that the characters are not clear, and in the case of black characters,
There is a problem that turbidity occurs at edges and small letters. On the other hand, with respect to the halftone image, since the vicinity of the edge detection frequency is emphasized, the halftone image loses smoothness and becomes a rough image with strange moire and edges emphasized. Therefore, it is necessary to identify three types of image areas of black characters, color characters, and halftones, and switch the parameters of the filter unit, and several identification processing methods of this type have been proposed.

For example, the configuration shown in FIG.
No. 2940) introduces a run length identification method. The hue detection unit 41 uses 8 pixels for each pixel.
The comparator 42 detects one of the hues of colors (Y, M, C, K, W, B, G, and R), and the comparator 42 uses YMC.
It is to detect whether or not the largest one is equal to or more than the threshold value th _max . Since the hue detecting unit 41 also detects low-density noise and the like, in this case, the run length described later becomes short, and there is a problem in that it is erroneously recognized as a character area. Therefore, in order to make a pixel having a density of at least a certain level or more a character candidate, a comparison determination with a threshold th _max is performed and noise is removed.
It is 2.

The blocking unit 43 has several pixels, for example, 4 × 4.
Each pixel is divided into blocks of up to 8 × 8, and the block determination unit 44 performs 7-color determination. In the 7-color determination, the maximum frequency color in the block is determined for 7 colors (Y, M, C, K, B, G, R) excluding W, and this is set as the block color. For example, the frequency of each color is counted with 4 × 4 pixels as one block, and K = 6 and M =
If 2, R = 1, C = 1, and W = 6, the color excluding W / the maximum color K among black pixels is adopted as the block color.

The main scan direction color run count section 46 is
The block color determination unit 44 receives 1 bit representing W (0) or black (1) other than that, and counts the run length of the color / black block in the main scanning direction. It is determined whether or not the count value (run length) of each block is shorter than the threshold value th _run . Here, if the run length of the color / black block is shorter than the threshold value th _run , it becomes a character candidate.

When viewed in terms of run length, the dot length in the pixel unit is short like the character region and it is difficult to separate from the character, but in the block unit the run length of the dot region is long, In the case of a character area, the block run length becomes shorter because the distance between characters is longer than the pitch of halftone dots. In this way, the block run length enables distinction between a character and a halftone dot area.

The sub-scanning direction edge detection unit 45 detects whether or not there is an edge within a range of several blocks in the sub-scanning direction, and if there is an edge, it is a character candidate. This is because the horizontal line used in the character area also has a long run length, and thus the run length in the main scanning direction is not a candidate for a character, and therefore, in such a case as well, it is to be detected as a candidate for a character. ..

The OR gate 48 and the AND gate 49 have character candidates in either the main scanning direction or the sub scanning direction based on the above detection results, and the max flag of the block is 1.
If so, this block is determined to be a character area, and the block color signal determined by the block color determination unit 44 is output. The max flag is set to Y in the comparator 42.
This is a signal indicating that the maximum number of MCs is 1 or more in the block, which is determined to be the threshold th _max or more.

The above example focuses on the short run length around the character portion. That is, the character part is composed of a block of characters and a block of the background, and the density changes sharply because it is in the background of the background, whereas the image part is in the image background and the density is gentle. .. Therefore, when the run length is observed, the run length is short in the character region and the run length is long in the halftone region. Moreover, it was difficult to distinguish between a halftone dot area and a character area on a pixel-by-pixel basis, but in the case of halftone dots, the run length becomes longer by blocking, so it is necessary to recognize in the halftone area instead of the character area. You can In other words, due to the block formation, halftone dot patches having a high frequency also tend to occur as color blocks with long run lengths,
It can be captured as a halftone area. Further, if the main scan direction color run count unit 46 and the comparator 47 only detect character candidates, a line with a long run length in the main scan direction will be mistakenly recognized. In some cases, the recognition accuracy is improved by using the character candidates.

In addition, the configuration shown in FIG.
No. 136071), a maximum value and a minimum value are detected from a plurality of pixels in block units, a character area is identified based on whether or not a difference between them is larger than a predetermined value, and area determination of surrounding blocks is further performed. Error correction is performed based on the result, and the area identification circuit is roughly divided into primary identification and secondary identification. The primary identification is the 8 × 8 blocking circuit 6
1 is used to identify a character area by forming a block of 8 × 8 pixels, and therefore, the maximum value detection circuit 62 and the minimum value detection circuit 63 are used to detect the maximum value and the minimum value from the 8 × 8 pixels of the block, respectively. Is detected, and the difference between them is calculated by the arithmetic circuit 64. Then, in the comparator 65, the arithmetic circuit 64
Output, that is, the difference between the maximum value and the minimum value is compared with the threshold value th, and when the difference is larger than the threshold value th, an identification signal of the character area, for example, a logic “1” is output. In the secondary identification, the error of the identification area of the block is further corrected by the primary identification in the 3 × 3 block.

For example, when the target block is identified as a character region by the primary identification, and most of the surrounding blocks are not the character region, the identification content of the target block is corrected to the non-character region. Similarly, when the target block is identified as a non-character region by the primary identification and most of the surrounding blocks are character regions, the identification content of the target block is corrected to the character region.

FIG. 11 is a diagram showing a configuration example of the hue detection circuit. The hue detection circuit has Y, M, and C as shown in FIG.
A maximum value circuit 71, a minimum value circuit 72, which obtains the maximum value and the minimum value of, a subtraction circuit 73 which obtains the difference between the maximum value and the minimum value,
Subtraction circuits 74 to 7 for obtaining the difference between Y, M and C and the minimum value
6 and comparators 77 to 81. The comparator 77 outputs the output of the subtraction circuit 73 (max-mi
n) and the threshold value th1, the comparator 78 outputs the minimum value (min) and the threshold value th2, the comparator 79 outputs the subtraction circuit 74 (Y-min) and the threshold value th3, and the comparator 80 outputs the subtraction circuit 75 (M). -Min) and threshold t
h4, the comparator 81 outputs the output (C−
min) and the threshold value th5, and if each value is greater than the threshold values th1 to th5, the logical value "1" is obtained.
The signals r, m, c ', m', and y'are output. Then, from this output, the judgment hue is derived under the judgment condition shown in FIG. 9B, and it is judged whether the development color is the necessary color "1" or the unnecessary color "0". As the judgment hue, W (white), Y, M, C, B, G, which is used as a color of a normal character,
The determination ROM 82 is for performing the hue determination of the table shown in FIG. 9B by using the outputs of the comparators 77 to 81 for the eight colors R and K.

In addition to the above, the average value and the standard deviation in a predetermined pixel block are used (for example, JP-A-63-205).
No. 783) or a method using binary output converted by a plurality of dither conversions having different phases (for example, Japanese Patent Laid-Open No. 63-1937).
No. 70), the maximum value and the minimum value in the block are obtained for each of the R, G, and B color separation signals, and at least 1
When the difference between two color components is a predetermined value or more, it is determined as a character area (for example, Japanese Patent Publication No. 63-51
Various systems have been proposed so far.

[0020]

However, even in the above-mentioned conventional various area identification methods, the identification performance is improved by surely performing the block determination, but in reality, the speedup of the apparatus is achieved. In order to obtain a color copy with high quality and high image quality, it is necessary to operate the document reading at a high speed and process the read image data at a high speed. There is a problem in that the noise causes variations in area recognition in the development process, and defects such as interruptions of black characters appear.

That is, in color copying, since a full-color image is reproduced by superposing toner images of Y, M, C, and K by four scans as described above, the difference between the maximum and minimum values and the run Even if area determination is performed in block units using each feature amount such as length, average value, standard deviation, etc., the same area determination result is obtained through four development processes of Y, M, C, and K. If it is not obtained, the image quality is rather deteriorated.

For example, if the black character area is determined in the M and C developing processes, but the black character area is not determined in the Y and K developing processes, the black character is interrupted in the block and output as Y. Will be done. That is, since M and C are the determination of the black character area,
Since K is also a determination other than the black character area, the output is suppressed, and only Y is output. In particular, if processing is performed such that the YMC is reproduced by reproducing only K in the black character identification area and the K signal is reset in the color character identification area,
If the area identification is wrong, the color characters may change to black characters, or color change due to color loss may occur.

Moreover, if YMC is reset in the case of a black character by performing area identification, the background color portion becomes blank, but if K is reset in the case of a color character, in the case of blue, not only MC but usually Due to YK, blue reproducibility is extremely reduced. Further, since the determination is made in blocks and the output is performed, the situation in which black characters are changed to colored characters becomes more conspicuous and the blocks are visible, as compared with the output in pixel units. Since such a defect also appears in the area of color characters and halftones, there is a problem that the image quality is significantly deteriorated.

Further, in the conventional method, the hardware configuration is complicated, and conversely, if it is simple, the identification performance is poor, and there is nothing to be satisfied. In particular, it is difficult to match the hardware for black character / color character identification to correspond to a color image, and it is unavoidable that the system is separated from the area identification.

It is an object of the present invention to provide a pictographic character separation circuit for a color image processing apparatus, which has a compact blocking means and whose discrimination performance is improved. Another object of the present invention is to facilitate timing design.

[0026]

To this end, the present invention is directed to an image processing apparatus for processing a color image signal by dividing a plurality of pixels into blocks to identify regions of characters and halftones and switching parameters according to the region identification signal. A data fetching switching means for controlling switching between a mode for fetching data every line and a mode for fetching every other line, a blocking means for blocking the fetched data under the control of the switching means, and a region by the blocked data It is characterized in that it is provided with an area identifying means for performing identification. Further, the block size is a power of 2, and the area identifying means has a timing adjusting means composed of a line buffer, and controls the read timing of the line buffer so that the timing of outputting the area identifying signal is synchronized with the line signal. It is characterized by

[0027]

In the pictographic character separation circuit of the color image processing apparatus of the present invention, the mode for taking in the data every other line can be switched by the data taking-in switching means, so that it is substantially larger than the size of the blocking means if necessary. Larger size blocks can be adopted. Further, since the block size is a power of 2, the block data averaging process can be performed only by bit shifting. Further, since the read timing of the line buffer is controlled so that the timing of outputting the area identification signal is synchronized with the line signal, the internal delay can be easily adjusted.

[0028]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing an embodiment of an image area identification circuit of an image processing apparatus of the present invention.

In FIG. 1, input signals L ^* , a ^* , b ^*.
Is an 8-bit signal expressed as a system value, in which the L ^* axis represents lightness, and the a ^* axis and b ^* orthogonal to the lightness ^.
The two-dimensional plane of the axis represents saturation and hue. The data acquisition switching means 2 receives the input signals L ^* , a ^* , b ^*.
The block forming means 1 is a means for controlling the switching between the mode for fetching the data for area identification obtained from each line and the mode for fetching the data every other line.
(Line) × 8 (pixels), 4 × 16, etc., and is divided into blocks with a power of 2. Area identification means 3
Is to identify information from the data in the block and perform arithmetic processing to identify areas such as pictograms / background / characters, black characters / colored characters / halftones, etc.
The line buffer is used to synchronize the timing of the finally output area identification signal with the line signal by controlling the read timing using the FIFO.

By controlling the data acquisition, block size, and output timing as described above, the structure of the block means can be made compact without deteriorating the identification performance, and the data averaging processing in the area identification means can be performed. This simplifies the operation and facilitates the adjustment of the transmission timing of the area identification signal. FIG. 1B shows the above configuration in more detail, which will be described below.

In FIG. 1B, the nonlinear quantizer 11
Is for compressing the 8-bit signal L ^* of each pixel into 4 bits, and the quantizer 12 sets the 8-bit signal L ^* of each pixel to high level / intermediate level / low level at thresholds th1 and th2. And outputs the 2-bit signal divided into levels, and the hue discriminator 13 outputs the 8-bit signal L of each pixel.
^It outputs a 2-bit hue signal that identifies color, black or white from ^* , a ^* , and b ^* .

The block FIFO 14 holds data of 4 lines in the sub-scanning direction and 8 pixels in the main scanning direction and stores 4 ×.
8 blocks are formed, and one line is thinned from each of the 8 input lines to hold 4 lines, thereby forming a block corresponding to a size of 8 × 8. The data of one pixel held in the block FIFO 14 is 8 bits consisting of a compressed 4-bit signal L ^* , a 2-bit level division signal and a 2-bit hue signal, and each 4-bit signal L ^* is an average value. Calculation circuit 16
The 2-bit level division signal is distributed to the counters 17 and 18, and the 2-bit hue signal is distributed to the block hue discriminator 19.

The average value calculating circuit 16 adds the signals L ^* of the pixels in the block to calculate the average value Pa in the block. The counter 17 counts the high level pixel number Ph from the level division signal, and the counter 18 counts the intermediate level pixel number Pm. In the quantizer 12, the low level threshold is th1, the high level threshold is th2, and when the signal L ^* is between the thresholds th1 and th2, only the lower bit of the two bits is set to “1”, When exceeding the threshold th2, if only the upper bits are set to "1", the counter 17 counts the upper bits and the counter 18 counts the lower bits.

The non-linear quantizers 20 to 22 are for compressing the data of the average value calculating circuit 16 and the counters 17 and 18, respectively.
The comparator 24 generates a character / halftone determination signal.
The LUT 23 is a Pa-in the three-dimensional space shown in FIG.
The threshold value of Pm in a block which is a character area on the Ph plane (left side plane in the drawing) is read out, and the comparator 24
If this threshold value is larger, the solid line block is entered in the three-dimensional space shown in FIG. 7, and the character region determination signal is output. The adder inserted between the LUT 23 and the comparator 24 is connected to the LUT2 by the bias TH _bias.
3 is to adjust the bias of the threshold value read out from No. 3, and to adjust the character area.

The comparator 15 and the flag detector 25 detect whether or not the block is a background block. The 4-bit signal L ^* compressed by the comparator 15 is compared with the threshold value TH _av to detect the flag detector 25. It is for detecting whether or not there is a pixel exceeding the threshold value TH _av in the block. Therefore, here, when all the pixels in the block are smaller than the threshold value TH _av , it is determined to be the background. In other words, if there is at least one pixel that exceeds the threshold TH _av , it is not a character / halftone but a background. Error correction circuit 26
Is for inputting a character / halftone determination signal and a background detection signal and performing correction in larger blocks by comparing with the determination signals of surrounding blocks, for example, and outputting a character / halftone determination signal. To do.

The block hue discriminator 19 is a block F
The hue signal of each pixel that has been blocked by the IFO 14 is used to discriminate a hue of color or black and white on a block basis, for example, by a majority decision, and the delay circuit 28 delays the color / black and white block hue signal to correct an error. This is to be synchronized with the character / halftone determination signal of the circuit 26. The final judgment circuit 27 finally outputs a color character / black character / halftone T / I (text image) area judgment signal from the character / halftone judgment signal and the color / monochrome block hue signal. is there.

In the area identification in the block unit as described above, when the block size is 4 × 4, the number of lines becomes 4, so that the cost can be reduced but the identification performance is deteriorated. A block size of a certain size is required to improve the identification performance, and for example, if the block size is 8 × 8, the identification performance is considerably improved. However, since the number of lines in the sub-scanning direction increases, the number of line buffers increases and the hardware cost increases.
Therefore, in the present invention, the block size of 4 × 8 is basically adopted as described above, and the block size of 8 × 8 is artificially adopted by thinning out every other line to form a block, The block size is low in cost so that a satisfactory identification performance can be obtained.

If the block size N is selected to be 2 ^N , the average value within the block can be obtained only by N-bit shift of the total sum within the block. Therefore, if the block size is 4 × 8, 4 × 8 = 32 becomes 2 ⁵ , so the average value a = T / 32 can be calculated from the block sum T by simply shifting to the right by 5 bits. Intra-block averaging can be performed with only a simple hardware configuration.

FIG. 2 is a diagram showing an embodiment and waveforms of a blocking circuit applied in the present invention. 31 to 33 are FIFOs for one line, 34 is a flip-flop, 35 is an inverter circuit, 36 and 37. Is an AND circuit.

The flip-flop 34 is configured to operate as a frequency dividing circuit for the line synchronization signal LS by returning the inverted signal of the negative output to the input terminal and inputting the line synchronization signal LS as a clock. In this circuit, the page synchronizing signal P is controlled by the selection signal SEL, which controls whether the line synchronizing signal LS is divided or output as it is.
When both S and the selection signal SEL are high level, the AND circuit 36
When the AND condition of is satisfied, the frequency dividing circuit operates. That is, the selection signal SEL is the thinning signal of FIG. 1, and when it is set to the low level, the block size of 4 × 8 is selected, and when it is set to the high level, the block size of 8 × 8 is selected.

FIG. 2B shows the output waveform when the selection signal SEL is set to the high level, and FIG. 2C shows the output waveform when the selection signal SEL is kept at the low level. .. As apparent from FIG. 2B, when the selection signal SEL is set to the high level and the page synchronization signal PS becomes the high level, the output signal is inverted and divided at the falling timing of the line synchronization signal LS. The write control signal RSTW for the FIFOs 31 to 33 is provided every other line through the AND circuit 37. Therefore, FI
Pseudo 8 × 8 block size data is extracted from the FOs 31 to 33 by every other four lines.
However, when the selection signal SEL remains low level, the flip-flop 34 does not operate even if the page synchronization signal PS becomes high level as shown in FIG. The signal LS is output as it is, and data of 4 × 8 block size is taken out from the continuous lines of the FIFOs 31 to 33.

As described above, in order to identify a region, when 4 (lines) × 8 (pixels) are divided into blocks, data is taken in once from every line to every 2 lines so that 8 × is simulated. Since data of 8 block sizes can be fetched, this block formation can be switched according to the contents of the original or image processing, and more detailed area identification separation can be performed. Further, an adder may be provided before the FIFO, and the data of the previous line may be added so that the data is fetched once for every two lines by the data for two lines.

If the internal delay of the LSI is large due to the image processing, the timing study becomes complicated. Therefore, as shown in FIG. 3A, in the image processing LSI, an LSI in which data is temporarily stored in the FIFO is
If the final output data can be read at a timing that can be synchronized with the external main scanning sync signal, apparently there will be no internal delay in the main scanning direction, and complicated timing design in the main scanning direction at the time of board design Disappear.

FIG. 3 is a diagram for explaining the internal delay of the LSI and its correction processing. Assuming that the image processing delay is T _d as shown in FIG. 3B, the data once stored in the FIFO is read earlier than the line signal synchronized with the image data by the image processing delay T _d. You can do this. That is, as shown in FIG. 3B, the delay amount T _dc at which the finally output data is read from the falling edge of the line signal and the rising edge of the next line signal is set in the register in advance, Control the read timing.

FIG. 4 is a diagram showing an example of the configuration of the block color judgment & synthesis circuit. 4, the counters 41 and 42 and the block color determination circuit 43 configure the block hue discriminator 19 of FIG. 1, and count the color pixels among the pixels blocked by the blocking FIFO 14. Counter 41, Counter 4 counts black pixels
It is 2.

The hue discriminator 13 shown in FIG. 1 generates a 2-bit discrimination signal by using the first bit as the pixel color discrimination signal of the black pixel and the second bit as the pixel color discrimination signal of the color pixel. At 42, each bit is counted. The block color determination circuit 43 is composed of a comparator that compares the values of the counters 41 and 42 in the block, and generates a block color determination signal of “H” if there are many color pixels and “L” if there are many black pixels. .. On the other hand, the counter 44 counts the color blocks in one page, and the document determination circuit 45 compares the value of the counter 44 with the threshold value held in the register to determine whether the page is a color document or a monochrome document. It is a judgment.

The FIFO 46, the delay circuit 47, and the FIFO 48 adjust the output timing of the final area identification signal so as to be synchronized with the line synchronization signal.
The ternary BPM macro correction circuit 49 further compares the pattern / background / character determination signal with a predetermined size for the existence patterns of the pattern block and the character block, and performs macro correction by the block pattern matching method.

The synthesizing circuit 50 is provided with a macro-corrected pattern /
The background / character determination signal is combined with the color / monochrome block color determination signal. In the case of a picture / background, the pattern is used regardless of the block color determination signal, and in the case of a character, the block color is colored. If it is, a color character signal is generated, and if the block color is black and white, a black character signal is generated. In addition, when the area is identified and the pattern / black character / colored character is separated, it can be used as it is in the case of four-color full color, but in the case of three-color full-color, the black character is reproduced in YMC as well as the color character. / Distinguishing colored letters is not required. Therefore,
A block determined to be a character other than the four-color full color may be processed as a color character.

FIG. 5 is a diagram showing a modification of the image area identification circuit, FIG. 6 is a diagram for explaining the distribution of color characters / halftone images, and FIG. 7 is a diagram for explaining an example of the distribution state of character areas. FIG. 8 is a diagram for explaining parameter optimization conditions.

In a document in which a binary image such as a line drawing or a character and a halftone image such as a photograph or a halftone dot are mixed, the characteristic amounts of the character and the halftone area are sampled in a blocked area. However, they adopt a feature quantity limited to one such as a run length or a difference between the maximum value and the minimum value. On the other hand, according to the present invention, a predetermined number of pixels are divided into blocks, the average value Pa in the block, the number of high level pixels in the block Ph, and the number of intermediate level pixels in the block Pm are sampled, and their three-dimensional distribution state FIG. 5 shows an example of the basic configuration for determining the area from
Is.

In the example shown in FIG. 5A, first, the 8-bit average value Pa in the block, the 6-bit in-block high-level pixel number Ph, and the 6-bit in-block intermediate-level pixel number P.
m is 3 bits, 4 bits, and 4 in quantizers 1 to 3, respectively.
After quantizing into bits, the threshold value TH is read from the average value Pa in the block and the number of high level pixels in the block Ph by the 7-bit LUT 4, and the threshold value is compared by the comparator 5 with the number of intermediate level pixels in the block Pm. / To obtain a halftone area determination signal.

On the other hand, in the embodiment shown in (b), 1 is obtained by using the quantized intra-block average value Pa, intra-block high level pixel number Ph, and intra-block intermediate level pixel number Pm.
A 1-bit LUT 6 is used to obtain a character / halftone area determination signal. Further, in the embodiment shown in (c), the average value Pa within a block and the number of high-level pixels within a block remain as they are without quantization. By using Ph and the number Pm of intermediate level pixels in the block, a 20-bit LUT 7 is used to obtain a character / halftone area determination signal.

Considering a document in which characters and halftones are mixed, as shown in FIG. 6A, a high-level threshold th1 is set.
And a low level threshold th2 are set, the character sharply rises from a low level background such as A,
There are many high-level pixels that exceed the threshold th1 and low-level pixels that do not reach the threshold th2, and few intermediate-level pixels between the thresholds th1 and th2. That is, there are relatively more low-level backgrounds than high-level character parts. On the other hand, halftones are evenly distributed in each level as in B, but when viewed in a region, they are distributed in low level and intermediate level, in intermediate level, and in intermediate level and high level. If it is distributed, it will be distributed at a high level. Therefore, when viewed in terms of the average value (in-block average value Pa) and frequency, the characters are distributed to the lower average value and the halftone is distributed to the higher average value as shown in (b). .. Therefore, the respective feature quantities are as follows.

In the case of the character area, since there are more backgrounds than the high level of the character portion, the average value Pa in the block is low, there are at least one high level pixel, and at least one low level pixel. There are more than pixels. If this condition is not satisfied, for example, if all of the blocks are high-level pixels, the halftone area will be obtained. Therefore, when the above-mentioned three feature quantities are viewed three-dimensionally, the distribution state of the character area is as shown in FIG. That is, it can be seen that the range of characters can be considerably limited by combining the three types of characteristic values.

Now, assuming that the total number of all pixels in the block is Pt, the character area must satisfy at least the following conditions.

Ph + Pm ≦ Pt−1 1 ≦ Ph ≦ Pt−1 That is, when viewed from the plane consisting of Ph and Pm, the character area is distributed in the black background area and the halftone area is distributed in the white background area. To do. Therefore, the character area becomes the first area when and is satisfied.

Further, the actual identification parameter is determined by statistically analyzing each image data and taking the above conditions into consideration. The configuration for realizing this is shown in FIG. 5 described above. (C) stores the identification result in the three-dimensional LUT in advance, and Pa, Ph, and Pm are 8, 6, and 6 respectively. The configuration is such that 20 bits obtained by combining the bit results are input as the address of the LUT. On the other hand, in (b), since the capacity of the LUT is reduced, Pa, Ph, P
A quantizer is inserted in m and each data word length is compressed to reduce the capacity of the LUT. That is, LSI
In order to realize this, it is necessary to make the memory as small as possible internally, and in this case, reduction of up to 11 bits of 3, 4, 4 is realized. Of course, this quantization cannot be simply applied, but by making the distribution state of Pa, Ph, and Pm and the quantization non-linear, it can be confirmed that even this level of compression does not hinder the discrimination performance. It was And
In (a), the hardware scale in (b) is further reduced by paying attention to the characteristics of Pm, and the configuration uses a two-dimensional LUT and one comparator. This means that the distribution state of Pm in the character area is always Pm when looking at FIG. 7 and FIG.
It is noted that = 0 is set as the minimum value and Pm ≦ Pt−Ph−1 is set as the maximum value. From this, it can be seen that the determination method of the character area when the value of Pm is smaller than the threshold value of the maximum value of Pm which is predetermined by Pa and Ph and the halftone area when the value of Pm is large can be realized. As a result, the hardware feasibility can be improved without deteriorating the identification performance.

Next, a configuration example of the image processing apparatus to which the present invention is applied will be shown. FIG. 9 is a diagram showing a configuration example of a signal processing system of the image processing apparatus.

In FIG. 9, the image input unit 100 includes, for example, three CCs B, G and R arranged at right angles to the sub-scanning direction.
A reduction type sensor including a D line sensor is provided, and an image is read by scanning in the main scanning direction in synchronization with a timing signal from the timing generation circuit 12 while moving in the sub-scanning direction at a speed according to the expansion / contraction ratio. IIT, which is analog image data and is converted into gradation-represented 8-bit digital image data, for example. The shading correction circuit 11 performs shading correction on the image data for variations between pixels due to various factors, and the gap correction circuit 13 performs gap correction between the line sensors. The gap correction is FIFO14
Is to delay the image data read by the amount corresponding to the gap of the CCD line sensor so that the B, G, and R image data at the same position can be obtained at the same time. An ENL (Equivalent Neutral Lightness) conversion circuit 15 performs gray balance processing of image data using a parameter according to a document type, and a negative / positive inversion signal from an editing processing unit 400 described later. This makes it possible to invert the way gray is taken for each pixel and invert the negative / positive, for example, to invert the negative / positive only in a certain designated area.

B, G, processed by the ENL conversion circuit 15
The R image data is converted into signals L ^* , a ^* , b ^* in the uniform color space, for example, by the matrix circuit 16a. In the uniform color space signals L ^* , a ^* , and b ^* , L ^* represents lightness on the coordinate axes orthogonal to each other, and a ^* and b ^* are chromaticity planes (hue,
Represents the saturation). Such a uniform color space signal L ^* ,
The memory system 20 is converted into a ^* and b ^*.
It is possible to easily interface with the outside such as a computer through 0, and to facilitate color conversion, edit processing, and detection of image information. The selector 17 is the matrix conversion circuit 1
The output of 6a or the image data from the memory system 200 which is an interface with the outside is selectively taken out, or both image data are taken in at the same time to perform the texture synthesizing process and the watermark synthesizing process. Therefore, the selector 17 has a function of performing the setting of the combining ratio, the calculation process, and the combining process for the combined image.

The background removal circuit 18 creates a histogram of the document density by, for example, pre-scanning to detect the background density, and skips pixels below the background density to improve the copy quality for a fogged document such as a newspaper. It is for. The document detection circuit 19 detects and stores the document size by detecting the boundary between the back surface of the black platen and the document and determining the circumscribed rectangle. In the background removal circuit 18 and the original detection circuit 19, the lightness information of the signals L ^* , a ^* , and b ^{* in} the uniform color space is signal L ^*.
Is used.

The edit processing section 400 sets an area command for performing edit processing and switching of parameters etc. for each area, and generates an area control signal based on the area command to perform color editing and color editing on the image data. Conversion, marker color detection, and other processing are performed. Then, the processed image data is input to the matrix conversion circuit 16a and the pictographic character separation circuit (TIS circuit) 20.

In the matrix conversion circuit 16a, L ^* , a ^* , b ^* to Y, and
After being converted into M and C toner colors, the picture character separation circuit 20 divides a plurality of pixels into blocks to identify areas of color character / black character / picture (character / halftone). In the under color removal circuit 21, Y converted by the matrix conversion circuit 16b,
The black (K) generation is performed from the M and C image data according to the mono-color / full-color signal, and the equal amounts of Y, M, and C are removed, and the process color image data is output. A judgment is made to generate a hue signal (Hue). When the pictogram separation circuit 20 performs the identification processing, the area identification signal is delayed by, for example, 12 lines due to the block formation. Therefore, a timing is taken to synchronize the hue signal and the image data with the delay. FIFO2
2a and 22b.

The reduction / expansion circuit 23b performs the reduction / enlargement processing on the image data in accordance with the designated reduction / enlargement ratio. In the sub-scanning direction, the image input unit 100 changes the scanning speed in accordance with the reduction / enlargement ratio to reduce the size. Since the image data is expanded, the image data is thinned out or interpolated in the main scanning direction. The expansion / contraction circuit 23a is for expanding / contracting the area command so that the execution area of the area control information does not shift in correspondence with the expansion / contraction processing on the image data. The area control information subjected to the reduction / expansion processing is the area decoder 24.
Are decoded by and processed by each processing block. The area decoder 24 uses an area command, an area identification signal,
The switching signal of the parameter 25 of the filter, the coefficient of the multiplier 26, and the parameter of the TRC circuit 27 is generated from the hue signal and distributed.

The filter 25 removes the halftone moiré and emphasizes the edges of the characters in the image data reduced or enlarged by the reduction circuit 23b according to the spatial frequency. The TRC circuit 27 is for adjusting the density according to the characteristics of the IOT using the conversion table,
29 is TRC by the signal of the development process and area identification
It is a decoder that switches the parameters of the conversion table of the circuit 27. The multiplier 26 performs ax + b calculation on the image data x using the coefficients a and b, and the coefficient is switched between through in the case of halftone and high γ in the case of character. By appropriately selecting the coefficient and conversion table for each color component used in combination with the TRC circuit 27, data reset, color adjustment, and density adjustment for color characters, black characters, and patterns are performed. Further, the parameters of the filter 25 can be standardized, and the edge emphasis of the character can be adjusted by the coefficients a and b. The image data adjusted by these is stored in a memory system or RO
In the screen generation unit 28 of S300, dots are expanded and output as a halftone dot image.

The editing processing section 400 performs color conversion, color editing, generation of a region control signal, etc., and receives image data L ^* , a ^* , b ^* from the selector 17. Then, the LUT 415a converts the chromaticity information from a and b in the orthogonal coordinate system into C and H in the polar coordinate system so that the marker color and other colors can be easily detected, color edited, and converted. The color conversion & palette 413 has, for example, 32 kinds of colors used in color conversion and color editing, and the delay circuit 411.
The image data L, C, and H are subjected to marker color detection, color editing, color conversion, and other processing in accordance with area commands input through a. Then, only the image data of the area where the color conversion or the like is performed is performed by the color conversion & palette 41
After being processed by the LUT 415b and converted back from C, H to a, b, the image data of the other areas is directly output from the selector 416, and the matrix conversion circuit 16 described above is used.
sent to b.

The marker color (3 colors) detected from the image data by the color conversion & palette 413 and the 4-bit signal of the closed area are sent to the density conversion / area generation circuit 405. Density conversion
In the area generation circuit 405, the FIFOs 410a, 410
In the 4 × 4 window using b and 410c, the density conversion from 400 spi to 100 spi is performed by performing the binarization process of setting “1” when the number of black pixels is equal to or larger than the predetermined number in 16 pixels. The marker signal (closed loop or marker dot) generated in this way is written in the plane memory 403 from the density conversion / region generation circuit 405 through the DRAM controller 402.

As for the marker / dot signal, the FIF is set so that small dust or the like is not erroneously detected as a marker.
The coordinate value generation circuit 407 detects the marker dot and generates the coordinate value and stores it in the RAM 406 by delaying by 3 lines by O408 to form a 3 × 3 window. For the marker dot, the plain memory 40
3 is stored, but this process is performed to prevent erroneous detection.

The plane memory 403 is a memory for storing area commands for performing color conversion, color editing, and other area editing. For example, the area is designated from the edit pad and the area command is written in the area. be able to. That is, the area command of the area designated by the edit pad is transferred to the graphic controller 401 through the CPU bus and written from the graphic controller 401 to the plane memory 403 through the DRAM controller 402. The plane memory 403 is composed of four sides and has 16 numbers from 0 to 15.
Area commands of various types can be set.

The 4-bit area command stored in the plane memory 403 is read in synchronism with the output of the image data, and is subjected to the color conversion & palette editing process, or the process shown in FIG.
Image data processing system, ENL conversion circuit 15, matrix conversion circuit 16, selector 17, undercolor removal circuit 21,
Further, it is used for switching parameters such as the filter 25, the multiplier 26, the TRC circuit 27, and the screen generation unit 28 via the area decoder 24. When this area command is read out from the plane memory 403 and used for color conversion & palette 413 editing processing, parameter switching in the image data processing system, etc., density conversion from 100 spi to 400 spi is necessary. The processing is performed by the density conversion area generation circuit 405. In the density conversion area generation circuit 405, 3 × 3 blocks are formed by using the FIFOs 409a and 409b, and data interpolation is performed from the pattern so that a boundary of a closed loop curve or an editing area does not become jagged, and 100 spi to 400 spi The density conversion to The delay circuits 411a, 411b, 1MFIFO 412 and the like are for adjusting the timing between the area command and the image data.

[0071]

As described above, according to the present invention,
Since it is possible to switch to a mode in which data is captured every other line by the data capture switching unit, it is possible to employ a block having a size substantially larger than the size of the blocking unit, and improve the identification performance. be able to. Further, since the block size is a power of 2, the block data averaging process can be performed only by bit shifting, and the hardware and software configurations for the arithmetic process can be simplified. Further, since the read timing of the line buffer is controlled so that the timing of outputting the area identification signal is synchronized with the line signal, the internal delay can be easily adjusted and the difficult timing design of the circuit becomes unnecessary.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of an image area identification circuit of an image processing apparatus of the present invention.

FIG. 2 is a diagram showing an example and waveforms of a blocking circuit applied in the present invention.

FIG. 3 is a diagram for explaining an internal delay of an LSI and its correction processing.

FIG. 4 is a diagram showing a configuration example of a block color determination & synthesis circuit.

FIG. 5 is a diagram showing a modified example of the image area identification circuit.

FIG. 6 is a diagram for explaining the distribution of color characters / halftone images.

FIG. 7 is a diagram for explaining an example of a distribution state of character areas.

FIG. 8 is a diagram for explaining parameter optimization conditions.

FIG. 9 is a diagram illustrating a configuration example of a signal processing system of the image processing apparatus.

FIG. 10 is a diagram illustrating a configuration example of a conventional color image processing device and a configuration example of an image area identification circuit.

FIG. 11 is a diagram illustrating a configuration example of a hue detection circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Blocking means, 2 ... Data acquisition switching means, 3 ... Area identification means, 4 ... Timing adjusting means

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] November 11, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1A is a diagram showing an embodiment of an image area identification circuit of an image processing apparatus of the present invention.

FIG. 1B is a diagram showing an embodiment of an image area identification circuit of the image processing apparatus of the present invention.

FIG. 2 is a diagram showing an example and waveforms of a blocking circuit applied in the present invention.

FIG. 3 is a diagram for explaining an internal delay of an LSI and its correction processing.

FIG. 4 is a diagram showing a configuration example of a block color determination & synthesis circuit.

FIG. 5 is a diagram showing a modified example of the image area identification circuit.

FIG. 6 is a diagram for explaining the distribution of color characters / halftone images.

FIG. 7 is a diagram for explaining an example of a distribution state of character areas.

FIG. 8 is a diagram for explaining parameter optimization conditions.

FIG. 9A is a diagram showing a configuration example of a signal processing system of the image processing apparatus.

FIG. 9B is a diagram showing a configuration example of a signal processing system of the image processing apparatus.

FIG. 10 is a diagram showing a configuration example of a conventional color image processing device and a configuration example of an image area identification circuit.

FIG. 11 is a diagram illustrating a configuration example of a hue detection circuit.

[Explanation of Codes] 1 ... Blocking Means, 2 ... Data Acquisition Switching Means, 3 ... Area Identifying Means, 4 ... Timing Adjusting Means

[Procedure Amendment 2]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Figure 7]

[Figure 8]

[Fig. 1B]

[Fig. 2]

[Figure 3]

[Figure 6]

[Figure 4]

[Figure 5]

[Figure 9a]

[Fig. 9B]

[Figure 10]

FIG. 11

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification number Internal reference number FI Technical indication location H04N 1/46 9068-5C (72) Inventor Yoshiyuki Sorimachi 2274 Hongo, Ebina-shi, Kanagawa Fujizero Tsukusu stock Company Ebina Office (72) Inventor Keitoku Awata 1275 Iwatsuki, Iwatsuki City, Saitama Prefecture Fuji Zero Tux Co., Ltd. Iwatsuki Office

Claims (3)

[Claims] 1. An image processing apparatus for processing a color image signal by switching a parameter according to an area identification signal by identifying an area of a character or a halftone by dividing a plurality of pixels into blocks, and a mode in which data is taken in every line. Data acquisition switching means for controlling switching to a mode performed every other line, blocking means for blocking the data taken in under the control of the switching means, and area identification means for performing area identification by the blocked data are provided. A pictographic character separation circuit for a color image processing device. 2. The pictographic character separation circuit of the color image processing apparatus according to claim 1, wherein the block size is a power of 2. 3. The area identifying means has a timing adjusting means composed of a line buffer, and controls the read timing of the line buffer so that the timing of outputting the area identifying signal is synchronized with the line signal. 2. A pictographic character separation circuit of the color image processing device according to item 1.