JPH05145388A - Transfer gate switch circuit - Google Patents

Abstract

PURPOSE:To realize a transmission signal by suppressing a parasitic capacitance caused in a FET as a switching element and crosstalk due to a gate control line so as to improve the isolation between the input and the output or between noninverting and inverting phases. CONSTITUTION:With FETs 21, 22 set off by a control signal CS, a crosstalk component appearing at an output terminal OUT through a parasitic capacitance C3 caused between a drain and a source of the FET 21 and a parasitic capacitance C6 caused between common gate control lines of the FETs 21, 22 and the gate and source of the FET 22 is suppressed by resistors 31, 32. On the other hand, a crosstalk component appearing at a connecting point A through parasitic capacitors C3, C4 caused between the drain and gate and the gate and source of the FET 21 is bypassed to a fixed voltage VBB through the FET 6. Moreover, through the constitution above, the isolation between the input and output is considerably improved. Thus, the high speed transmission signal is realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transfer gate switch circuit which is used as a switch cell of, for example, a matrix switch circuit and is particularly suitable for integration into an integrated circuit.

[0002]

2. Description of the Related Art Conventionally, transfer gate switch circuits are often used as switch cells in matrix switch circuits. FIG. 7 shows a basic configuration of a transfer gate switch circuit using a conventional transfer gate circuit.

In FIG. 7, FET1 is an open source buffer whose drain is connected to a fixed potential (GND in the figure), and whose gate is connected to a signal input terminal IN,
The source is connected to the drain of FET2 which serves as a switching element. The FET 2 turns on / off the drain input from the source according to the control signal CS supplied to the gate through the resistor 3, and the source is connected to the signal output end OUT and the terminating resistor (T) 4 Is connected to the bias potential VT.

That is, the switch circuit having the above structure is
After the signal input is voltage / current converted by the ET1, the current signal is turned on / off by the FET2, and the current / voltage is converted and output by the terminating resistor 4.

By the way, in the matrix switch circuit,
Along with the integration into an integrated circuit, a wider band is being advanced, and accordingly, a transfer gate switch circuit as a switch cell is also required to improve isolation while suppressing the number of elements as much as possible.

Here, the input / output simulation waveform of a gigabit / second class high frequency signal in the switch circuit having the configuration of FIG. 7 is as shown in FIG. still,
In FIG. 8, a is an input signal waveform with a rise time of 100 [psec], b is a source output waveform of FET1, and c is F.
The output signal waveform when ET2 is turned off is shown, and the arrows in the figure indicate that the ranges of a and b are on the left and the range of c is on the right.

As is apparent from FIG. 8, even when the FET 2 is in the off state, a differential waveform is generated in the output at the transition point of the input waveform. The isolation between input and output at this time is -21.
[DB], which is insufficient as a switch cell. The main cause is that the input signal has a high frequency, so that the parasitic capacitances C1 and C2 generated between the drain and gate of the FET2 and between the gate and the source of the FET2 cannot be ignored, and these parasitic capacitances serve as bypass paths to leak signals. It is thought that there is something to do.

As a method of improving the isolation between the input and output, generally, as shown in FIG.
21 and 22 are connected in series to form a switch element section. This configuration is intended to suppress the crosstalk component by the impedance of each FET 21, 22. However, when actually looking at the input / output simulation waveform under the same conditions as in the case of FIG. 8, as shown in FIG. 10, the isolation between the input and output is -21 [d
B], and the problem of signal leakage due to the above parasitic capacitance is not essentially improved. It is considered that this is because the parasitic capacitances C3, C4, C5, and C6 generated between the drains and gates of the FETs 21 and 22 and between the gates and the sources serve as bypass paths to leak signals. In FIG. 10, d shows the source output waveform of the FET 21, and e shows the source output waveform of the FET 22.

Therefore, conventionally, as shown in FIG.
The drain of the FET 6 is connected to the connection point A between the source of the FET 21 and the drain of the FET 22, the source is connected to the fixed potential VBB, and the control signal CS- which is the inverted control signal CS is applied to the gate through the resistor 7. By supplying the power, the FET 6 is turned on when the FETs 21 and 22 are off, and the crosstalk component generated at the connection point A of the FETs 21 and 22 is bypassed to the fixed potential VBB.

FIG. 12 shows an input / output simulation result under the same conditions as in the case of FIG. 8 in the circuit configuration by this method. Note that, in FIG. 12, the FET 6 is in an on state, and in the figure, f indicates the source output waveform of the FET 21 (waveform at the connection point A), and g indicates the source output waveform of the FET 22. According to this configuration, as is apparent from FIG. 12, the isolation between the input and the output is improved to -29 [dB].

However, in the configuration of FIG.
Looking at the potential change at the connection point A of ET21,22,
As shown by f in FIG. 12, it is reduced to a very small value of −43 [dB], and the isolation between the input and output is −29 [dB] even though the FET 6 is effectively operating.
It is considered that the problem is that the problem of signal leakage due to the parasitic capacitance of C3 and C6 in FIG. 11 has not been improved yet.

By the way, it is known that a differential transmission line is effective for the transmission of a high frequency signal, but a transfer gate switch circuit used for such a differential transmission line is basically shown in FIG. Is configured as follows. That is, this circuit is provided with two switch circuits shown in FIG. 7 in parallel. However, the first and second switch circuits S
Gates of the switching FETs 1 and S2 are commonly connected, and a control signal C is connected to the connection point B via the resistor 3.
S is supplied. First switch circuit S1
The input / output terminal of is a positive phase input / output terminal (+) of the differential signal, and the input / output terminal of the second switch circuit S2 is a negative phase input / output terminal (−).

In the above structure, each switch circuit S1,
FIG. 14 shows an input / output simulation result when the FET2 of S2 is turned on. In FIG. 14, h is the input signal waveform of the first switch circuit S1, and i is the FE of S1.
The source output waveform of T1 and j the output signal waveform of S1.

As is clear from FIG. 14, the source output i of the FET1 follows the waveform of the input signal h, while the waveform of the output j of the first switch circuit S1 is greatly deteriorated. The main cause of this is the parasitic capacitance C1 generated between the drain and gate of the FET2 on the second switch circuit S2 side.
Signal leakage of the output of the FET1 occurs through the common gate line of the FET2 of the switch circuits S1 and S2, S
Parasitic capacitance C2 generated between the gate and source of FET2 of 1
It is thought that this is because it appears at the output terminal OUT (+) through.

[0015]

As described above, in the conventional transfer gate switch circuit, as the transmission signal becomes faster (higher frequency), the area between the control electrode and the controlled electrode of the FET, which becomes the switching element, is controlled. The crosstalk between the controlled electrodes when the FET is turned off increases due to the parasitic capacitance generated in the FET, but there is no effective means for suppressing this crosstalk and dramatically improving the isolation between the input and output. .. Even when the transfer gate switch circuits are applied in parallel in the forward and reverse phases of the differential transmission path, if the FETs that are the switching elements of the respective phases are turned on by a common control signal, the transmission signal With the increase in the speed, the common line of the parasitic capacitance and the control signal generated in the FET of each phase cannot be neglected, the crosstalk increases, and the isolation between the positive and negative phases deteriorates.

The present invention has been made to solve the above-mentioned problems, and suppresses the parasitic capacitance generated in the FET as a switching element and the crosstalk due to the gate control line thereof to suppress the crosstalk between the input and output or between the positive and negative phases. It is an object of the present invention to provide a transfer gate switch circuit that dramatically improves isolation and thereby makes it possible to increase the speed of a transmission signal.

[0017]

In order to achieve the above object, a transfer gate switch circuit according to the present invention comprises a first FET in which one controlled electrode serves as a signal input terminal.
Element and a second FET element in which one controlled electrode is connected to the other controlled electrode of the first FET element and the other controlled electrode serves as a signal output terminal, and one controlled electrode is A third FET connected to the common connection point of the first and second FET elements and having the other controlled electrode connected to the first fixed potential
An element and one of the first, second and third FE
A first, a second, and a third resistance element connected to each control electrode of the T element, and a first to a control electrode of the first and second FET elements via the first and second resistance elements. Control signal for controlling the ON / OFF of the controlled electrodes of the first and second FET elements at the same time, and the third switching element via the third resistance element. FE
Second switching control means for performing on / off control between the controlled electrodes of the third FET element by supplying a second control signal that is opposite to the first control signal to the control electrode of the T element; It is configured to include.

When used in a differential transmission line, two transfer gate switch circuits having the above configuration are provided in parallel, and the first and second control signals are shared between these switch circuits, and one of them is used. The signal input end of the switch circuit is the positive phase signal input end, the signal output end is the normal phase signal output end, the signal input end of the other switch circuit is the negative phase signal input end, and the signal output end is the negative phase signal output end. Performs switching control of differential signals.

[0019]

In the transfer gate switch circuit having the above structure, the first and second FETs are controlled by the first control signal.
When the element is turned off, the crosstalk component flowing in the common control line of each element is provided in the gate of each element.
The crosstalk component generated at the controlled electrode connection point of the first and second FET elements is suppressed by the second resistance, and in this state, the third FET element is turned on by the second control signal. Is bypassed to a fixed potential, which improves isolation between the input and output.

Further, two switch circuits having the above configuration are arranged in parallel, the first and second control signals are commonly used, one switch circuit is for a positive phase signal, and the other switch circuit is for a negative phase signal. If they are provided in the differential transmission path, a resistance is always provided at the gate inputs of the first and second FET elements of each switch circuit, so that crosstalk components from the other channels are suppressed, and the forward and reverse directions are thereby suppressed. The isolation between phases is improved.

[0021]

Embodiments of the present invention will be described below with reference to FIGS. However, in FIG. 1 and FIG. 3, the same parts as those in FIG. 11 and FIG.
Here, the different parts will be mainly described.

FIG. 1 shows a configuration in which the present invention is applied to a transfer gate switch circuit of one system. The circuit shown in FIG. 11 is further improved to replace the resistor 3 with each gate of the FETs 21 and 22. Resistor 3 in the control line
It is characterized in that 1, 32 are interposed.

According to this structure, when the FETs 21 and 22 are off by the control signal CS, the parasitic capacitance C3 generated between the drain and gate of the FET 21 and each FET 2
The output terminal OU through the common gate control line of 1 and 22 and the parasitic capacitance C6 generated between the gate and source of the FET 22.
The crosstalk component appearing at T is suppressed by the resistors 31 and 32 interposed in each gate control line.

On the other hand, between the drain and gate of the FET 21,
Parasitic capacitances C3 and C4 generated between the gate and the source, respectively
The crosstalk component appearing at the connection point A through
As described with reference to the circuit shown in FIG. 3, since the FET 6 is turned on by the reverse phase control signal CS-, this FE
It comes to be bypassed to the fixed potential VBB through T6.

In the circuit configuration according to this method, FIG.
FIG. 2 shows the input / output simulation results under the same conditions as in the above case. In FIG. 2, it is assumed that the FET 6 is in an ON state, f'indicates the source output waveform of the FET 21 (waveform at the connection point A), and g'indicates the source output waveform of the FET 22. According to this configuration, as is apparent from FIG. 2, the isolation between the input and the output is improved to -57 [dB].

Therefore, the switch circuit having the above structure can suppress the parasitic capacitance generated in the FETs 21 and 22 and the crosstalk due to the gate control line thereof.
As a result, the isolation between the input and output can be dramatically improved and the speed of the transmission signal can be increased.

In the above embodiment, the case where the present invention is applied to the improvement of the input / output isolation when the switch element portion is in the OFF state in the switch circuit of one system has been described. It is also applicable to the switch circuit of the differential transmission line shown in FIG. The configuration is shown in FIG.

In FIG. 3, the gates of the switching FETs 2 of the first and second switch circuits S1 and S2 are commonly connected via a resistor 33, and this connection point B '.
Is supplied with a control signal CS.

In the above structure, each switch circuit S1,
FIG. 4 shows an input / output simulation result when the FET2 of S2 is turned on. In FIG. 4, h is the input signal waveform of the first switch circuit S1, and i'is the FET of S1.
1 shows the source output waveform, and j'shows the output signal waveform of S1.

As is clear from FIG. 4, the source output i'of the FET1 follows the waveform of the input signal h, and the waveform of the output j'of the first switch circuit S1 is also the source output i'of the FET1. That is, it follows the waveform of the input signal h. This is due to the parasitic capacitance C1 generated between the drain and gate of the FET2 on the side of the second switch circuit S2 and FE.
This is because, even if the crosstalk of the output of T1 occurs, the crosstalk component is suppressed by the resistor 33 in the common gate line of the FET2 of each of the switch circuits S1 and S2.

Therefore, in the differential transmission line having the above structure, even when the FET2 of the switch circuit S1 is in the ON state, the crosstalk component from the opposite phase side hardly appears at the output terminal OUT (+), and similarly, the switch FE of circuit S2
Even when T2 is in the ON state, almost no crosstalk component from the opposite phase side appears at the output terminal OUT (-), and thereby the isolation between the positive and negative phases can be dramatically improved, and the transmission signal Higher speed can be realized.

By the way, in the differential transmission line having the above structure, crosstalk occurs in the switch circuits S1 and S2 of each system due to the parasitic capacitances C1 and C2 of the FET2.
The isolation between input and output is not improved. Therefore, as shown in FIG. 5, the individual switch circuits S1 and S2 are
The respective configurations are as shown in FIG. The control signals CS and CS- are common to each phase, and each is FET2.
1, 2, 6 are supplied via gate resistors 31, 32, 7.

That is, the resistors 31 and 32 of the switch circuits S1 and S2 respectively suppress the parasitic capacitance of the FETs 21 and 22 and the crosstalk component due to the common control line, and at the same time, prevent the crosstalk components leaking from other channels into the FETs 21 and 22. Also suppress. Therefore, in the differential transmission line configured as described above, isolation between the input and output and between the positive and negative phases can be improved at the same time. FIG. 6 shows the configuration of a matrix switch circuit having the transfer gate switch circuit as a cell in the differential transmission line.

The matrix switch circuit 6 is a differential transmission system and has four input channels and four output channels (4
X4). In consideration of transmission delay between channels in internal processing, D latch flip-flops (D / FF) 81 to 84, 9 are provided at the input stage and the output stage, respectively.
1 to 94 are provided to synchronize the channels.

The positive and negative phase output terminals of the input stages D / FF 81 to 84 are respectively connected to one ends of the input bus lines 101 and 104 by a pair of differential transmission lines, and the other of the input bus lines 101 to 104. The end is a terminating resistor (T) 111
~ 114. On the other hand, the output stages D / FF 91 to 9
An output bus line formed by a pair of differential transmission lines is connected to each of the positive and negative phase input terminals of the reference numeral 4. Each output bus line 1
Each of the differential transmission lines 21 to 124 has a terminating resistor (T) 1
It is grounded via 31-134.

Input bus lines 101 to 1 of each channel
Reference numerals 04 denote transfer gate switch circuits S11 to S14, S21 to S24, ...
S41 to S44 are connected in parallel. Each of the switch circuits S11, S12, ... Has the configuration shown in FIG. 5, and has forward and reverse phase control signals CS11, CS11-, CS12, respectively.
Switching is controlled by CS12-, and its differential output is output bus lines 121 to 124 of the corresponding channels.
Be derived to.

That is, the matrix switch circuit having the above-described configuration is the switch circuit S1 arranged in a matrix.
1, S12, ...
S11-, CS12, CS12 -... Selectively turned on /
By performing the off control, the input bus line of any channel can be connected to any output bus line. At this time, in each of the switch circuits S11, S12, ... Since the isolation between the input and output and the isolation between the positive and negative phases are sufficiently taken, it is possible to expect a sufficiently high speed of the transmission signal. Needless to say, the present invention can be similarly implemented even if various modifications are made without departing from the scope of the present invention.

[0038]

As described above, according to the present invention, the parasitic capacitance generated in the FET as the switching element and the crosstalk due to the gate control line thereof are suppressed, and the isolation between the input and output or between the positive and negative phases jumps. Therefore, it is possible to provide a transfer gate switch circuit which is improved in speed and can realize a high speed transmission signal.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a transfer gate switch circuit according to the present invention.

FIG. 2 is a waveform diagram illustrating input-output isolation in the switch circuit according to the embodiment of FIG.

FIG. 3 is a circuit diagram showing a configuration for interposing a transfer gate switch circuit according to the present invention in a differential transmission line.

FIG. 4 is a waveform diagram illustrating the isolation between input and output in the switch circuit of the embodiment of FIG.

FIG. 5 is a configuration diagram showing a configuration of a switch circuit in the case of combining the embodiments of FIGS.

FIG. 6 is a block circuit diagram showing a configuration of a matrix switch circuit including the switch circuit of FIG. 5 as a cell.

FIG. 7 is a circuit diagram showing a basic configuration of a transfer gate switch circuit using a conventional transfer gate circuit.

8 is a waveform diagram illustrating the isolation between input and output in the switch circuit of FIG.

9 is a circuit diagram showing an improved configuration of the transfer gate switch circuit of FIG.

FIG. 10 is a waveform diagram illustrating input-output isolation in the switch circuit of FIG.

FIG. 11 is a circuit diagram showing a configuration in which the transfer gate switch circuit of FIG. 9 is further improved.

12 is a waveform diagram illustrating the input-output isolation in the switch circuit of FIG.

13 is a circuit diagram showing a configuration when the transfer gate switch circuit of FIG. 7 is used in a differential transmission line.

14 is a waveform diagram illustrating the isolation between the positive and negative phases of the switch circuit in the differential transmission line of FIG.

[Explanation of symbols]

1 ... Buffer FET, 2, 21, 22, 6 ... Switching FET, 3, 31, 32, 33, 7 ... Gate resistance, 4 ... Termination resistance (T), 81-84, 91-94 ... D
Latch flip-flops 101 to 104 ... Input bus lines, 111 to 114, 131 to 134 ... Terminating resistors, 1
21-124 ... Output bus lines, C1-C6 ... Parasitic capacitance, CS, CS -... Control signal, VT ... Bias potential, V
BB ... Fixed potential, S1, S2, S11 to S14, S21 to
S24, ..., S41 to S44 ... Transfer gate switch circuits.

Claims (3)

[Claims] 1. A first FET element having one controlled electrode serving as a signal input terminal, and one controlled electrode connected to the other controlled electrode of the first FET element, and the other controlled electrode. Is connected to a common connection point of the first and second FET elements and the second FET element whose signal output terminal is, and the other controlled electrode is connected to the first fixed potential. A third FET element and one end of each of the first, second, and
First, second, and third resistance elements connected to respective control electrodes of the third FET element, and control electrodes of the first and second FET elements via the first and second resistance elements A first switching control means for simultaneously controlling ON / OFF between the controlled electrodes of the first and second FET elements by supplying a first control signal to the first and second FET elements, and the third resistance element. By supplying a second control signal that is opposite to the first control signal to the control electrode of the third FET element, the third F element is supplied.
A transfer gate switch circuit comprising: a second switching control means for controlling ON / OFF between controlled electrodes of an ET element. 2. One of the controlled electrodes is connected to a signal input terminal of the first FET element, the other controlled electrode is connected to a second fixed potential, and the control electrode serves as a signal input terminal. The fourth FET element, and a terminating circuit having one end connected to a signal output end of the second FET element and the other end connected to a third fixed potential. Transfer gate switch circuit. 3. The transfer gate switch circuit according to claim 2 is provided in parallel, the first and second control signals are shared between these switch circuits, and the signal input terminal of one of the switch circuits is positive. The phase signal input terminal and the signal output terminal are the positive phase signal output terminals, the signal input terminal of the other switch circuit is the negative phase signal input terminal, and the signal output terminal is the negative phase signal output terminal.
A transfer gate switch circuit characterized by performing switching control of a differential signal.