JPH05145351A - Differential amplifier circuit - Google Patents

Abstract

PURPOSE:To reduce a parasitic capacitance fed to an output terminal by selecting substantially a parasitic capacitor between a collector and a base of a transistor(TR) fed to the output terminal to be that for one base ground TR pair. CONSTITUTION:Differential TR pairs 141-14m+n are divided into plural groups 211-21m and output terminals of all the differential TR pairs 141-14m+n in each of the groups 211-21m are connected in common to input terminals of base ground TR pairs 151-15m respectively. Then output terminals of the TR pairs 151-15m are connected to an input terminal of a base ground TR 16. Thus, the parasitic capacitance between the collector and the base of the TR fed to the output terminal 19 is selected substantially to be the parasitic capacitance between the collector and the base of one TR of the TR pair 16, and the parasitic capacitance between the collector and the base of the TR fed to the output terminal 20 is selected substantially to be the parasitic capacitance between the collector and the base of the other TR of the TR pair 16. As a result, the parasitic capacitance fed to the terminals 19, 20 is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read head in a magnetic disk device having a plurality of magnetic disks as a storage medium and a plurality of read heads corresponding to the plurality of magnetic disks. The present invention relates to a differential amplifier circuit used when amplifying a signal output from a device.

[0002]

2. Description of the Related Art Conventionally, as a differential amplifier circuit of this type, one having a circuit diagram shown in FIG. 8 is known.

This differential amplifier circuit is built in an IC for a magnetic disk device. In the figure, 1 ₁ to ₁₈ are input signals output from read heads of 1 to 8 channels, respectively. a signal input section that is, 2 ₁ ~
2 ₈ and 3 _{1 to} 3 ₈ are signal input terminals.

Further, 4 ₁ to 4 ₈ are differential transistor pairs for performing a differential amplification operation, and 5 _{1 to} 5 ₈ and 6 _{1 to} 6 ₈ are NPN transistors. Further, 7 _{1-7 8} is turned ON or OFF a current path of the differential transistor pair 41 _{to 8} on the basis of the control signal C ₁ -C ₈ applied to its base, a differential transistor pair 41 _{to 8} is an NPN transistor that controls activation and deactivation.

[0005] 8 constant current source is provided in common to the differential transistor pair 4 _{1-4 8,} 9 VCC power supply line supplying a power supply voltage VCC, 10 are NPN transistors 5 ₁
5 ₈ and a load resistor provided in common, 11 NPN
Load resistors 12 and 13 provided in common for the transistors 6 _{1 to} 6 ₈ are output terminals.

In this differential amplifier circuit, any _one of the NPN transistors 7 _{1 to} 7 ₈ is turned on by the control signals C _{1 to} C _8.
Differential transistor pair 4 ₁
Activates only one either to 4 _8, is that to obtain an amplified signal obtained by amplifying the target amplified signal is input to the differential transistor pairs this activation output terminals 12 and 13.

[0007]

However, in such a conventional differential amplifier circuit, all the collector-substrate parasitic capacitances of the NPN transistors 5 _{1 to} 5 ₈ are added to the output terminal 12 as parasitic capacitances. the terminal 13, as a parasitic capacitance, the parasitic capacitance between the collector and the substrate of the NPN transistor ₆₁ through ₈ will be applied all.

For this reason, such a conventional differential amplifier circuit has a problem that it is not possible to obtain a wide band frequency characteristic and it is not possible to increase the transfer rate of the data read from the magnetic disk.

Further, in recent years, in the magnetic disk device, it is required to increase the number of built-in magnetic disks to increase the number of channels for accessing the magnetic disks and increase the storage capacity.

In order to meet this demand, in the conventional differential amplifier circuit, when the number of differential transistor pairs is increased, the parasitic capacitance applied to the output terminals 12 and 13 is increased, and the frequency characteristic is deteriorated. There was a problem that it would end up.

In view of the above points, the present invention makes it possible to reduce the parasitic capacitance applied to the output terminal from which the amplified signal is output, obtain a wide band frequency characteristic, and increase the data transfer rate. Even if the number of differential transistor pairs to which the amplified signal is input is increased, the parasitic capacitance applied to the output terminal is not increased, good frequency characteristics are obtained, and it is possible to handle multiple channels of the input signal. An object is to provide a dynamic amplification circuit.

[0012]

FIG. 1 is a diagram for explaining the principle of a differential amplifier circuit according to the present invention, in which 14 ₁ , 14 ₂ ...
・ 14 _{m + n} is a differential transistor pair (differential Tr pair), 1
Reference numerals 5 ₁ , 15 ₂ ... 15 _m , 16 are grounded base transistor pairs (grounded ground Tr pairs), 17 is a power line, 18 is a load circuit, and 19 and 20 are output terminals.

Here, the differential transistor pair 14 ₁ , 14 ₂
... 14 _{m + n} are input signals to be amplified from different signal output sources, and activate one differential transistor pair by selection. In the present invention,
It is divided into a plurality of groups 21 ₁ , 21 ₂ ... 21 _m .

In addition, the base-grounded transistor pair 15 ₁ ,
15 ₂ ... 15 _m are for each group 21 ₁ , 2
1 ₂ ... 21 _m Each group 21 ₁ 21 ₂
..One for each 21 _m .

Therefore, each group 21 ₁ , 21 ₂ ... 2
All differential transistor pairs 14 _{1 to} 14 _n within 1 _m , 14
_n + 1 _{~14 2n,} ···, the output end of the _{14 m + 1 ~14 m + n} ,
Grounded transistor pair 15 ₁ , 15 _2, ...
・ Commonly connected to 15 _m input terminals.

The grounded base transistor pair 16 is
It is provided for the base-grounded transistor pair 15 ₁ , 15 _2, ... 15 _m . Therefore, the output terminals of the grounded base transistor pair 15 ₁ , 15 ₂ ... 15 _m are commonly connected to the input terminal of the grounded base transistor pair 16.

That is, the differential amplifier circuit according to the present invention selectively activates any one of the differential transistor pairs 14 ₁ , 14 ₂ ... 14 _{m + n} , and inputs to the activated differential transistor pair. is that obtained in any one, and base transistor pair 16 through the output terminal 19, 20 of the amplified signal tandem-connected base-grounded transistor pair 15 ₁ to 15 _m obtained by amplifying the target amplified signal.

[0018]

In the present invention, the output terminals 19 and 20 have 1
Only the base-grounded transistor pair 16 is connected, and the base-grounded transistor pair 16 is not directly connected to the differential transistor pair 14 ₁ , 14 _2, ... 14 _{m + n} .

That is, in the present invention, the differential transistor pairs 14 ₁ , 14 ₂ ... 14 _{m + n} are grouped into a plurality of groups 2.
1 ₁ , 21 ₂ ... 21 _m divided into groups 21 ₁ , 2
One base-grounded transistor pair 15 ₁ , 15 ₂ ... 15 _m is provided for each 1 ₂ ... 21 _m , and each group 21 ₁ , 2
All differential transistor pairs 14 ₁ within 1 ₂ ... 21 _{m
~14 n, 14 n + 1 ~14} 2n, ···, 14 m + 1 ~14 m + n
The output terminals of the pair of grounded-base transistors 15
₁ , 15 ₂ ... 15 _m are commonly connected to the input terminals, and the base-grounded transistors 15 ₁ , 15 ₂ ...
The output terminal of 15 _m is connected to the input terminal of the base-grounded transistor 16.

Therefore, in the present invention, the collector-substrate parasitic capacitance of the transistor applied to the output terminal 19 is substantially the collector-substrate parasitic capacitance of one of the transistors forming the grounded base transistor pair 16, and the output The collector-substrate parasitic capacitance of the transistor applied to the terminal 20 can be substantially the collector-substrate parasitic capacitance of the other transistor forming the base-grounded transistor pair 16.

As a result, according to the present invention, it is possible to reduce the parasitic capacitance applied to the output terminals 19 and 20 from which the amplified signal is output, obtain a wide band frequency characteristic, and increase the data transfer rate. Even if the number of differential transistor pairs 14 _{1 to} 14 _{m + n} to which the signal to be amplified is input is increased, the parasitic capacitance applied to the output terminals 19 and 20 is not increased, and good frequency characteristics are obtained, and the input signal It can support multiple channels.

The present invention can be constructed not only by using bipolar transistors but also by using MOS transistors. In this case, a gate-grounded transistor pair may be provided instead of the base-grounded transistor pair.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first embodiment of the present invention will be described below with reference to FIGS.
Examples to third examples will be described. The first to third embodiments improve the conventional differential amplifier circuit shown in FIG. Therefore, in FIGS. 2 to 4, 6 and 7, parts corresponding to those in FIG. 8 are designated by the same reference numerals, and duplicate description thereof will be omitted.

First Embodiment FIG. 2 to FIG. 5 FIG. 2 is a circuit diagram showing a first embodiment of the present invention. In the figure,
22 ₁ , 22 ₂ , and 23 are grounded-base transistor pairs, and 24 ₁ , 24 ₂ , 25 ₁ , 25 ₂ , 26, and 27 are NPN.
It is a transistor.

The NPN transistors 24 ₁ , 24 ₂ ,
The bases of 25 ₁ and 25 ₂ are AC-grounded via a bias power supply 29, and NPN transistors 26 and 27 are connected.
Has its base AC-grounded via a bias power supply 30.

The bias voltage VA supplied from the bias power supply 29 to the bases of the NPN transistors 24 ₁ , 24 ₂ , 25 ₁ and 25 ₂ and the bias voltage VB supplied from the bias power supply 30 to the bases of the NPN transistors 26 and 27.
And the power supply voltage VCC, VCC>VB> V
It is supposed to be A.

Here, the differential transistor pairs 4 ₁ to 4 ₈ are
Group 28 comprised of a differential transistor pair 4 _{1-4 4}
Group 2 consisting of ₁ and differential transistor pair 4 ₅ to 4 ₈
It is divided into 8 ₂ .

In the group 28 ₁ , NP
The N transistors 5 _{1 to} 5 ₄ have their collectors commonly connected to the emitter of the NPN transistor 24 ₁ , and the NPN transistors 6 _{1 to} 6 ₄ have their collectors commonly connected to the emitter of the NPN transistor 25 ₁ .

In the group 28 ₂ , the NPN
The collectors of the transistors 5 _{5 to} 5 ₈ are commonly connected to the emitter of the NPN transistor 24 ₂ , and the collectors of the NPN transistors 6 _{5 to} 6 ₈ are commonly connected to the emitter of the NPN transistor 25 ₂ .

In addition, the base-grounded transistor pair 22 ₁ ,
22 ₂ includes NPN transistors 24 ₁ and 24
₂ has its collector commonly connected to the emitter of the NPN transistor 26, and has NPN transistors 25 ₁ and 25
₂ has its collector commonly connected to the emitter of the NPN transistor 27.

In the grounded base transistor pair 23, the collector of the NPN transistor 26 is connected to the load resistor 10 and the output terminal 12, and the collector of the NPN transistor 27 is connected to the load resistor 11 and the output terminal 13. ing. Otherwise, the configuration is similar to that of the conventional differential amplifier circuit shown in FIG.

In the differential amplifier circuit according to the first embodiment, any _{one of the} NPN transistors 7 _{1 to} 7 ₈ is turned on and all the other NPN transistors are turned off by the control signals C _{1 to} C ₈ , and the differential transistor pair 4 is used. Only one of ₁ to 4 ₈ is activated, and an amplified signal obtained by amplifying the signal input to the activated differential transistor pair is grounded base transistor pair 22 ₁ ,
It is obtained at the output terminals 12 and 13 through any one of 22 ₂ and the grounded base transistor pair 23.

Here, for example, as shown in FIG. 3, considering the case where the grounded base transistor pair 22 ₁ and 22 ₂ are not provided, the collector-substrate parasitic capacitance of the NPN transistor added to the output terminal 12 is (On the circuit), only the collector-substrate parasitic capacitance of the NPN transistor 26 is present, and the collector-substrate parasitic capacitance of the NPN transistor added to the output terminal 13 is external (on the circuit) the collector-substrate parasitic capacitance. Since it is only the capacity, it seems that wideband frequency characteristics can be obtained at first glance.

However, in reality, the NPN transistor 2
If there are many NPN transistors connected to the emitters of 6 and 27, for example, as shown in FIG. 3, eight NPN transistors 5 _{1 to} 5 ₈ and 6 _{1 to} 6 ₈ are provided at the emitters of the NPN transistors 26 and 27, respectively. Are connected, they are affected by the collector-substrate parasitic capacitances of these NPN transistors 5 _{1 to} 5 ₈ and 6 _{1 to} 6 ₈ and have a wider frequency characteristic than the conventional differential amplifier circuit shown in FIG. Although it can be obtained, it has been experimentally confirmed that it is not possible to obtain the sufficient broadband frequency characteristics that are currently required.

Considering, for example, the case where the grounded base transistor pair 23 is not provided as shown in FIG. 4, only four NPN transistors 5 _{1 to} 5 ₄ are connected to the emitter of the NPN transistor 24 _1. However, only four NPN transistors 6 _{1 to} 6 ₄ are connected to the emitter of the NPN transistor 25 ₁ .

Further, also the emitter of the NPN transistor 24 _2, not being only 4 amino NPN transistors ₅ 5-5 ₈ connected to the emitter of the NPN transistor 25 _2, only four NPN transistors 6 ₅ ~ Only 6 ₈ are connected.

As a result, in this case, the collector-substrate parasitic capacitance of the NPN transistor applied to the output terminal 12 is
It is not affected by the collector-substrate parasitic capacitance of the NPN transistors 5 _{1 to} 5 ₈ and is substantially only the collector-substrate parasitic capacitance of the _two NPN transistors 24 ₁ and 24 ₂ .

[0038] The collector-substrate parasitic capacitance of the NPN transistor applied to the output terminal 13 is also not affected by the collector-substrate parasitic capacitance of the NPN transistor ₆₁ through _8, substantially two NPN transistors 25 ₁ , 25 ₂
It is only the parasitic capacitance between the collector and the substrate.

Therefore, according to the differential amplifier circuit shown in FIG. 4, there is no doubt that a wider band frequency characteristic can be obtained than the conventional differential amplifier circuit shown in FIG. 8, but it is added to the output terminals 12 and 13. Compared with the case where the collector-substrate parasitic capacitance of the NPN transistor is substantially the collector-substrate parasitic capacitance of one NPN transistor as in the case of the first embodiment described later,
The frequency characteristic cannot be wideband.

Here, in this first embodiment, FIG.
As shown in, the output terminal 12 has a collector connected to N
The emitter of the PN transistor 26 has only two N
Only the PN transistors 24 ₁ and 24 ₂ are connected,
Moreover, these two NPN transistors 24 ₁ and 24 ₂
There are four NPN transistors 5 _{1 to} 5 ₄ and 5 respectively.
_{5-5 8} not only are connected.

Further, only two NPN transistors 25 ₁ and 25 ₂ are connected to the emitter of the NPN transistor 27 whose collector is connected to the output terminal 13, and these two NPN transistors 25 _{1 are also connected.} ,
25 ₂ has four NPN transistors 6 _{1 to} 6 respectively.
Only ₄ and 6 _{5 to} 6 ₈ are connected.

[0042] Consequently, according to the first embodiment, the parasitic capacitance between the collector and the substrate of the NPN transistor applied to the output terminal 12 is not only the collector-substrate parasitic capacitance of the NPN transistor 5 ₁ to 5 _8, NPN Transistor 24
Not affected by the collector-substrate parasitic capacitance of ₁ and 24 ₂ ,
In essence, the collector of one NPN transistor 26
It is only the parasitic capacitance between substrates.

[0043] The collector-substrate parasitic capacitance of the NPN transistor applied to the output terminal 13 not only parasitic capacitance between the collector and the substrate of the NPN transistor ₆₁ through _8,
It is not affected by the collector-substrate parasitic capacitance of the NPN transistors 25 ₁ and 25 ₂ , and is substantially only the collector-substrate parasitic capacitance of one NPN transistor 27.

Therefore, according to the first embodiment, the parasitic capacitance applied to the output terminals 12 and 13 is reduced, and not only the conventional differential amplifier circuit shown in FIG. 8 but also the differential amplifier circuits shown in FIGS. to obtain a wide band frequency characteristic than the circuit, it is possible to increase the transfer rate of the data read from the magnetic disk, even when increasing the differential transistor pair ₄₁ to _8, it applied to the output terminals 12 and 13 parasitic Good frequency characteristics can be obtained without increasing the capacity, and it is possible to deal with multi-channel input signals.

By the way, FIG. 5 is a frequency characteristic diagram,
The solid line 31 is the case of the differential amplifier circuit of the first embodiment, and the chain double-dashed line 32 is the broken line 33 of the conventional differential amplifier circuit shown in FIG.
Shows the case of the differential amplifier circuit of FIG. 3, and the alternate long and short dash line 34 shows the case of the differential amplifier circuit of FIG.

Second Embodiment FIG. 6 FIG. 6 is a circuit diagram showing a second embodiment of the present invention. In this second embodiment, the emitters of NPN transistors 5 _{1 to} 5 ₈ are connected to the anodes of diodes 35 _{1 to} 35 ₈ , respectively,
The cathodes of these diodes 35 _{1 to} 35 ₈ are respectively connected to N
While connected to the collector of the PN transistor 7 _{1-7 8,} connecting the emitter of the NPN transistor ₆₁ through ₈ to the anode of each diode 36 _{1-36 8,} NPN cathode of the diode 36 _{1-36 8} respectively transistors It is connected to the collectors 7 _{1 to} 7 ₈ and is otherwise configured similarly to the first embodiment. This second
Also in the embodiment, it is possible to obtain the same effect as that of the first embodiment.

Third Embodiment ... FIG. 7 FIG. 7 is a circuit diagram showing a third embodiment of the present invention. In the third embodiment, the emitters of the NPN transistors 5 _{1 to} 5 ₈ are connected to the collectors of the NPN transistors 7 _{1 to} 7 ₈ via resistors 37 _{1 to} 37 ₈ respectively, and the emitters of the NPN transistors 6 _{1 to} 6 ₈ are connected. Are connected to the collectors of the NPN transistors 7 _{1 to} 7 ₈ via resistors 38 _{1 to} 38 ₈ , respectively, and the others are configured similarly to the first embodiment. Also in the third embodiment, it is possible to obtain the same effect as that of the first embodiment.

[0048]

According to the present invention, the collector-substrate parasitic capacitance of a transistor applied to an output terminal from which an amplified signal is output is substantially reduced by the collector-substrate substrate of a transistor forming one base-grounded transistor pair. Since it can be used as the inter-parasitic capacitance or the drain-substrate parasitic capacitance of the transistor that constitutes one gate-grounded transistor pair, the parasitic capacitance applied to the output terminal can be reduced and wideband frequency characteristics can be obtained to improve the data transfer rate. In addition to increasing the number of differential transistor pairs, it is possible to obtain good frequency characteristics without increasing the parasitic capacitance applied to the output terminals even when the number of differential transistor pairs is increased, and it is possible to cope with multi-channel input signals. ..

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a circuit diagram showing a first embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of a differential amplifier circuit to be compared with the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing another example of the differential amplifier circuit to be compared with the first embodiment of the present invention.

FIG. 5 is a diagram showing frequency characteristics according to the first embodiment of the present invention.

FIG. 6 is a circuit diagram showing a second embodiment of the present invention.

FIG. 7 is a circuit diagram showing a third embodiment of the present invention.

FIG. 8 is a circuit diagram showing an example of a conventional differential amplifier circuit.

[Explanation of symbols]

14 _{1 to} 14 _{m + n} Differential transistor pair 15 ₁ to 15 _m , 16 Base grounded transistor pair 17 Power supply line 18 Load circuit 19, 20 Output terminal

Claims (1)

[Claims] 1. A plurality of differential transistor pairs (14 ₁ , 1) in which signals to be amplified from different signal output sources are input and one differential transistor pair is activated by selection.
4 ₂ ··· 14 _{m + n)} a plurality of groups (21 _1, 21 _2,
.. 21 _m ) and one first grounded-base transistor pair (15 ₁ , 15 ₂ ... For each group (21 ₁ , 21 ₂ ... 21 _m ).
15 _m ) or one first grounded-gate transistor pair, and all the differential transistor pairs (14 _{1 to} 14 _n , 14 _{n + 1} ) in each group (21 ₁ , 21 ₂ ... 21 _m ) are provided. ~ 1
The output terminals of 4 _2n , ..., 14 _{m + 1 to} 14 _{m + n} ) are provided for each group (21 ₁ , 21 ₂ ... 21 _m ) respectively, and the first base-grounded transistor pair ( 15 ₁ , 1
5 ₂ ... 15 _m ) or a plurality of the first gate common transistors connected to the input terminals of the first pair of grounded transistors and provided for each group (21 ₁ , 21 ₂ ... 21 _m ). Base-grounded transistor pair (15
₁ , 15 ₂ ... 15 _m ) or a plurality of the first grounded-ground transistor pairs, one second grounded-base transistor pair (16) or one second grounded-gate transistor pair And a plurality of the first grounded-ground transistor pairs (15 ₁ , 15 ₂ ... 15 _m ) or a plurality of the first grounded-gate transistor pairs are connected to one second grounded-ground transistor. A pair (16) or one of the plurality of differential transistor pairs (14 ₁ , 14 ₂ ... 1) commonly connected to the input terminals of the second grounded-gate transistor pair
4 _{m + n} ) is selectively activated, and an amplified signal obtained by amplifying a signal to be amplified input to the activated differential transistor pair is supplied to the second grounded base transistor pair (1
6) Alternatively, the differential amplifier circuit is configured to be obtained at the output side of the second pair of grounded gate transistors.