JPH05145349A - Power amplifier - Google Patents

Power amplifier

Info

Publication number
JPH05145349A
JPH05145349A JP3303582A JP30358291A JPH05145349A JP H05145349 A JPH05145349 A JP H05145349A JP 3303582 A JP3303582 A JP 3303582A JP 30358291 A JP30358291 A JP 30358291A JP H05145349 A JPH05145349 A JP H05145349A
Authority
JP
Japan
Prior art keywords
stage circuit
circuit
power
voltage
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3303582A
Other languages
Japanese (ja)
Inventor
Shinichi Murai
伸一 村井
Kazuhiro Matsumoto
一宏 松本
Masahiro Hirayama
雅裕 平山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Fujitsu Quantum Devices Ltd
Original Assignee
Fujitsu Ltd
Fujitsu Quantum Devices Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Fujitsu Quantum Devices Ltd filed Critical Fujitsu Ltd
Priority to JP3303582A priority Critical patent/JPH05145349A/en
Publication of JPH05145349A publication Critical patent/JPH05145349A/en
Withdrawn legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

PURPOSE:To secure the transmission power and to reduce the power consumption without increasing number of components. CONSTITUTION:An amplitude of a signal outputted from a pre-stage circuit is adjusted by a power supply voltage given to the pre-stage circuit and an operating point of a post-stage circuit amplifying and outputting the signal is adjusted by a bias voltage given to a gate of the post stage circuit. When the amplitude of the output of the pre-stage circuit is increased by a power supply voltage given to the pre-stage circuit, the bias given to the gate of the post-stage circuit is controlled to be shallow, on the other hand, when the power voltage given the pre-stage circuit decreases the amplitude of the output of the pre-stage circuit, the bias given to the gate of the post-stage circuit is controlled to de deep.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、持ち運びに便利な形状
を有する例えば携帯用電話機等の小型無線送受信機に適
用する電力増幅器に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier applied to a small radio transmitter / receiver having a shape convenient for carrying, such as a portable telephone.

【0002】[0002]

【従来の技術】近時、屋外、屋内を問わずいかなる場所
からでも通話(またはファクシミリ等の情報伝達)が可
能な例えば携帯用電話機の普及が著しいが、こうした小
型、軽量の無線装置には大容量バッテリを装着できない
ために、できるだけバッテリ消費の少ない回路構成が求
められる。
2. Description of the Related Art Recently, for example, portable telephones, which are capable of talking (or transmitting information such as facsimile) from any place whether indoors or outdoors, have become very popular. Since a capacity battery cannot be installed, a circuit configuration that consumes as little battery as possible is required.

【0003】一般に、無線装置の電力消費は電力増幅段
でもっとも多いので、通話距離(携帯用電話機の場合は
基地局からの距離)が短い場合には電力増幅段の電源電
圧を下げて送信電力を低くする対策や、電力増幅段の動
作点を常に深めにしてアイドル電流(キャリアのみの送
信時に流れる回路電流)を減少させる対策がとられる。
Generally, the power consumption of a wireless device is the highest in the power amplification stage. Therefore, when the communication distance (distance from the base station in the case of a mobile phone) is short, the power supply voltage of the power amplification stage is lowered to reduce the transmission power. Is taken, and the operating point of the power amplification stage is always deepened to reduce the idle current (circuit current flowing when transmitting only the carrier).

【0004】[0004]

【発明が解決しようとする課題】しかしながら、動作点
を常に深めに設定すると、消電力性の点で好ましい反
面、送信電力が低下する欠点があり、増幅段を多段構成
にしなければならないから、部品点数の増加に伴ってコ
ストが上昇し、あるいは部品点数の増加による回路特性
のバラツキを要因として歩留りが悪化し、さらには回路
規模が大きくなって小型化に逆行するといった諸問題点
があった。
However, if the operating point is always set deeper, it is preferable in terms of power consumption, but on the other hand, there is a drawback that the transmission power is lowered, and the amplification stage must be configured in multiple stages. There have been various problems that the cost increases as the number of points increases, or the yield deteriorates due to the variation in the circuit characteristics due to the increase in the number of parts, and further the circuit scale becomes large and goes against size reduction.

【0005】そこで、本発明は、部品点数を増大するこ
となく、送信電力の確保と低消費電力化を図ることを目
的とする。
Therefore, an object of the present invention is to secure transmission power and reduce power consumption without increasing the number of parts.

【0006】[0006]

【課題を解決するための手段】本発明は、上記目的を達
成するためその原理図を図1に示すように、前段回路か
ら出力される信号の振幅を該前段回路に与える電源電圧
で調節し、且つ、前記信号を増幅して出力する後段回路
の動作点を、該後段回路のゲートに与えるバイアス電圧
によって調節する電力増幅器において、前段回路に与え
られる電源電圧が該前段回路の出力の振幅を増大させる
ときは、後段回路のゲートに与えるバイアスを浅く制御
し、一方、前段回路に与えられる電源電圧が該前段回路
の出力の振幅を減少させるときは、後段回路のゲートに
与えるバイアスを深く制御することを特徴とする。
In order to achieve the above object, the present invention adjusts the amplitude of a signal output from a pre-stage circuit by a power supply voltage applied to the pre-stage circuit as shown in the principle diagram of FIG. In a power amplifier that adjusts the operating point of the latter-stage circuit that amplifies and outputs the signal by the bias voltage applied to the gate of the latter-stage circuit, the power supply voltage given to the former-stage circuit changes the amplitude of the output of the former-stage circuit. When increasing, the bias applied to the gate of the latter circuit is controlled to be shallow, while when the power supply voltage applied to the former circuit decreases the amplitude of the output of the former circuit, the bias applied to the gate of the latter circuit is deeply controlled. It is characterized by doing.

【0007】[0007]

【作用】本発明では、前段回路に与えられる電源電圧が
調節されて送信電力が変化すると、この送信電力の変化
に応じて後段回路のバイアス電圧(すなわち後段回路の
動作点)が変更操作される。したがって、近距離通信
(小電力送信)の際に動作点を深くすれば、電力消費を
低下でき、一方、遠距離通信(大電力送信)の際に動作
点を浅くすれば、十分な送信電力を確保できる。
In the present invention, when the power supply voltage applied to the preceding circuit is adjusted and the transmission power changes, the bias voltage of the succeeding circuit (that is, the operating point of the succeeding circuit) is changed according to the change of the transmitting power. .. Therefore, power consumption can be reduced by deepening the operating point during short-distance communication (low power transmission), while sufficient transmission power can be achieved by decreasing the operating point during long-distance communication (high power transmission). Can be secured.

【0008】[0008]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。図2、図3は本発明に係る電力増幅器の第1実施
例を示す図である。図2において、10は前段回路、2
0は後段回路である。前段回路10は、定電圧Vg10
グランド間に2個の抵抗11、12を直列接続し、その
抵抗12の両端に現れる電圧と、カップリングコンデン
サ13を介して入力する信号とを合成してGaAsFE
T14のゲート電極に与えると共に、GaAsFET1
4のドレイン電極に電源電圧Vd10を与え、また、Ga
AsFET14のソース電極にグランド電位を与えて構
成する。
Embodiments of the present invention will be described below with reference to the drawings. 2 and 3 are diagrams showing a first embodiment of the power amplifier according to the present invention. In FIG. 2, 10 is a front-end circuit, 2
Reference numeral 0 is a post-stage circuit. The pre-stage circuit 10 connects two resistors 11 and 12 in series between the constant voltage Vg 10 and the ground, and combines the voltage appearing across the resistor 12 and the signal input via the coupling capacitor 13. GaAsFE
It is given to the gate electrode of T14 and GaAsFET1
Power supply voltage Vd 10 is applied to the drain electrode of
It is configured by applying a ground potential to the source electrode of the AsFET 14.

【0009】後段回路20は、定電圧Vg20(=Vg10
であってもよい)とグランド間に2個の抵抗21、22
を直列接続し、その抵抗22の両端に現れる電圧V
22(発明の要旨に記載のバイアス電圧に相当)と、カッ
プリングコンデンサ23を介して入力する前段回路10
からの信号とを合成してGaAsFET24のゲート電
極に与えると共に、GaAsFET24のドレイン電極
に電源電圧Vd20を与え、また、GaAsFET24の
ソース電極にグランド電位を与えて構成する。
The latter circuit 20 has a constant voltage Vg 20 (= Vg 10
2) between the two resistors 21 and 22
Connected in series, the voltage V appearing across the resistor 22
22 (corresponding to the bias voltage described in the gist of the invention) and the pre-stage circuit 10 for inputting through the coupling capacitor 23.
The signal from the above is combined and applied to the gate electrode of the GaAsFET 24, the power supply voltage Vd 20 is applied to the drain electrode of the GaAsFET 24, and the ground potential is applied to the source electrode of the GaAsFET 24.

【0010】ここで、前段回路10と後段回路20の間
を交流的に接続するカップリングコンデンサ23には、
抵抗(発明の要旨に記載の抵抗素子に相当)40が並列
接続されており、前段回路10の電源電圧Vd10から抵
抗40及び後段回路20の抵抗22を通ってグランドに
至る閉回路が形成される。この閉回路を流れる電流ia
の向きは、後段回路20の直列抵抗回路網(抵抗21、
抵抗22)に流れる電流ibの向きと丁度、反対であ
る。
Here, the coupling capacitor 23, which connects the pre-stage circuit 10 and the post-stage circuit 20 in an alternating current, includes:
A resistor (corresponding to a resistor element described in the gist of the invention) 40 is connected in parallel to form a closed circuit from the power supply voltage Vd 10 of the front stage circuit 10 to the ground through the resistor 40 and the resistor 22 of the rear stage circuit 20. It Current ia flowing in this closed circuit
Direction of the series resistance circuit network (resistor 21,
It is just opposite to the direction of the current ib flowing through the resistor 22).

【0011】このような構成において、後段回路20の
GaAsFET24の動作点は、抵抗22の両端電圧V
22に追随して変化する。例えばV22を正方向に変化させ
ると動作点が浅くなって大きな送信出力が得られ、ある
いは負方向に変化させると動作点が深くなってアイドル
電流が少なくなる。前段回路10や後段回路20を含む
電力増幅段全体の出力調整は、前段回路10に与えられ
る電源電圧Vd10の調節によって行われる。例えば、遠
距離通信の場合にはVd10が大きくなり、近距離通信の
場合にはVd10が小さくなる。なお、こうした出力調節
は一般に、受信電力レベルに基づいて自動的に行われ
る。
In such a configuration, the operating point of the GaAsFET 24 of the latter stage circuit 20 is the voltage V across the resistor 22.
Change following 22 . For example, if V 22 is changed in the positive direction, the operating point becomes shallow and a large transmission output is obtained, or if it is changed in the negative direction, the operating point becomes deep and the idle current decreases. The output adjustment of the entire power amplification stage including the pre-stage circuit 10 and the post-stage circuit 20 is performed by adjusting the power supply voltage Vd 10 applied to the pre-stage circuit 10. For example, in the case of long-distance communication, Vd 10 becomes large, and in the case of short-distance communication, Vd 10 becomes small. It should be noted that such power adjustment is generally made automatically based on the received power level.

【0012】本実施例では、カップリングコンデンサ2
3に抵抗40を並列接続したので、前段回路10の電源
電圧Vd10の変化に応答して後段回路20のバイアス電
圧を増減操作することができる。これは、Vd10の変化
に伴って後段回路20の抵抗22に流れ込む電流iaが
変化し、抵抗22の両端電圧V22(すなわちバイアス電
圧)が変化するからである。
In this embodiment, the coupling capacitor 2
Since the resistor 40 is connected to 3 in parallel, the bias voltage of the rear circuit 20 can be increased or decreased in response to a change in the power supply voltage Vd 10 of the front circuit 10. This is because the current ia flowing into the resistor 22 of the subsequent circuit 20 changes with the change of Vd 10 , and the voltage V 22 across the resistor 22 (that is, the bias voltage) changes.

【0013】したがって、遠距離通信の際には、後段回
路20の動作点を浅くして十分な送信出力を得ることが
できると共に、近距離通信の際には、後段回路20の動
作点を深くしてアイドル電流を減少でき、消電力化を図
ることができる。図3は、送信電力と消費電力の関係を
示すグラフである。横軸が送信電力(Pmaxは最大電
力、Pminは最小電力)、縦軸が消費電力である。従
来例の特性線Aと本実施例の特性線Bを見比べると、P
maxでは両者とも同程度の消費電力であるが、送信電
力が小さくなるにつれて大きな差を生じている。これ
は、従来例が固定バイアスであるため、単一の動作点し
か設定できず、Pmaxを考慮してそれほど深い動作点
にすることができないからである。これに対して、本実
施例は送信電力に対応してバイアスが変化するので、動
作点を適宜適切に設定でき、送信電力が小さくなるほど
動作点を深くして電力消費を抑えることができる。この
ような消費電力特性は、携帯用電話機の使用形態と相ま
ってバッテリ寿命の延長化に寄与する。すなわち、携帯
用電話機を最高出力で使用する機会はそれほど多くな
く、低・中出力域の電力消費を改善することにより、電
話機使用中のバッテリ消費を抑えることができる。
Therefore, during long-distance communication, the operating point of the post-stage circuit 20 can be shallowed to obtain a sufficient transmission output, and during short-range communication, the operating point of the post-stage circuit 20 can be deepened. As a result, idle current can be reduced and power consumption can be reduced. FIG. 3 is a graph showing the relationship between transmission power and power consumption. The horizontal axis represents transmission power (Pmax is maximum power, Pmin is minimum power), and the vertical axis is power consumption. Comparing the characteristic line A of the conventional example with the characteristic line B of the present embodiment, P
At max, both power consumptions are about the same, but a large difference occurs as the transmission power becomes smaller. This is because the conventional example has a fixed bias, so that only a single operating point can be set and the operating point cannot be set so deep considering Pmax. On the other hand, in the present embodiment, since the bias changes according to the transmission power, the operating point can be appropriately set appropriately, and the operating point can be deepened and the power consumption can be suppressed as the transmission power decreases. Such power consumption characteristics contribute to the extension of battery life in combination with the usage pattern of the mobile phone. That is, there are not many occasions when the mobile phone is used at the maximum output, and the battery consumption during use of the phone can be suppressed by improving the power consumption in the low / medium output range.

【0014】なお、本発明は、上記実施例に限定される
ものではなく、様々な実施態様が考えられることは勿論
である。図4は本発明に係る電力増幅器の第2実施例を
示す図であり、第1実施例の抵抗40の代わりにツェナ
ーダイオード50を使用した例である。すなわち、カソ
ード側が前段回路10、アノード側が後段回路20とな
るようにカップリングコンデンサ23に並列接続された
ツェナーダイオード50には、Vd10とV22の電位差が
加えられており、その電位差がツェナー電圧以上であれ
ば後段回路20の抵抗22にツェナー電流icが流れ込
み、ツェナー電圧以下であればicが遮断される。した
がって、Vd10が大きい場合にはicによってV 22が正
方向に変化し、またV10が小さい場合にはicが遮断さ
れてV22が直ちに負方向に変化するような作用が得られ
る。ここで、ic遮断時のV22は、ibの大きさと抵抗
22の積で与えられる。
The present invention is limited to the above embodiment.
Of course, various embodiments can be considered.
Is. FIG. 4 shows a second embodiment of the power amplifier according to the present invention.
It is a figure shown, and zener is replaced with resistance 40 of a 1st example.
This is an example of using the diode 50. That is, Kaso
The cathode side is the front stage circuit 10, and the anode side is the rear stage circuit 20.
Connected in parallel to the coupling capacitor 23
Zener diode 50 has VdTenAnd Vtwenty twoThe potential difference between
If the potential difference is greater than the Zener voltage,
For example, the Zener current ic flows into the resistor 22 of the subsequent circuit 20.
However, if the voltage is less than the Zener voltage, ic is cut off. did
Therefore, VdTenIf is large, V depends on ic twenty twoIs positive
Direction, and VTenIc is cut off if is small
Vtwenty twoIs immediately changed to the negative direction.
It Here, V when ic is cut offtwenty twoIs the size and resistance of ib
It is given by the product of 22.

【0015】本実施例は、上記第1実施例の効果の他
に、ツェナー電圧によって決まるレベルをVd10が下回
ったときに動作点を一気に深くすることができるので、
例えば時分割多重方式の携帯用無線装置に好適なものと
することができる。すなわち、自己の無線装置に割り当
てられた時間内では、ツェナー電流を流して動作点を適
宜適切に調節できるとともに、割当時間外ではツェナー
電流を遮断することにより、動作点を最大に深くして消
費電力を殆どゼロに近づけることができる。
In addition to the effect of the first embodiment, the present embodiment can make the operating point deep at once when Vd 10 falls below the level determined by the Zener voltage.
For example, it may be suitable for a time division multiplexing portable radio apparatus. In other words, within the time allotted to its own wireless device, the operating point can be adjusted appropriately by flowing the Zener current, and by cutting off the Zener current outside the allotted time, the operating point is deepened to the maximum and consumed. The power can be brought close to zero.

【0016】図5は本発明に係る電力増幅器の第3実施
例を示す図であり、前段回路10の電源電圧Vd10と後
段回路20のバイアス用定電圧Vg20との間に2個の抵
抗60、61を直列接続し、抵抗60、61の接続点と
バイポーラトランジスタ(発明の要旨に記載の能動素子
に相当)62のベース電極とを接続すると共に、このト
ランジスタ62のコレクタ電極にVg20を与え、エミッ
タ電極とGaAsFET24のゲート電極を抵抗63を
介して接続したものである。
FIG. 5 is a diagram showing a third embodiment of the power amplifier according to the present invention. Two resistors are provided between the power supply voltage Vd 10 of the front stage circuit 10 and the constant bias voltage Vg 20 of the rear stage circuit 20. 60 and 61 are connected in series, the connection point of the resistors 60 and 61 is connected to the base electrode of a bipolar transistor (corresponding to the active element described in the gist of the invention) 62, and Vg 20 is applied to the collector electrode of the transistor 62. The emitter electrode and the gate electrode of the GaAs FET 24 are connected via the resistor 63.

【0017】このような構成によれば、Vd10とVg20
の電位差に相当する電圧が抵抗60、61の接続点に現
れ、この電圧によってトランジスタ62のコレクタ電流
idが制御される。したがって、トランジスタ62の増
幅作用により、Vd10の変化よりも大きな動作点変化を
得ることができ、特に出力調節幅の大きな無線装置に好
適なものとすることができる。
According to this structure, Vd 10 and Vg 20
A voltage corresponding to the potential difference of appears at the connection point of the resistors 60 and 61, and the collector current id of the transistor 62 is controlled by this voltage. Therefore, due to the amplifying action of the transistor 62, it is possible to obtain a change in the operating point larger than the change in Vd 10 , and it is particularly suitable for a wireless device having a large output adjustment range.

【0018】[0018]

【発明の効果】本発明によれば、前段回路に与える電源
電圧の変化に応じて後段回路に与えるバイアス電圧を増
減操作するように構成したので、部品点数を増大するこ
となく、送信電力の確保と低消費電力化を図ることがで
きる。
According to the present invention, since the bias voltage applied to the subsequent circuit is increased or decreased according to the change in the power supply voltage applied to the upstream circuit, the transmission power can be secured without increasing the number of parts. And low power consumption can be achieved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の原理図である。FIG. 1 is a principle diagram of the present invention.

【図2】第1実施例の構成図である。FIG. 2 is a configuration diagram of a first embodiment.

【図3】第1実施例の送信電力と消費電力の関係を示す
グラフである。
FIG. 3 is a graph showing a relationship between transmission power and power consumption according to the first embodiment.

【図4】第2実施例の構成図である。FIG. 4 is a configuration diagram of a second embodiment.

【図5】第3実施例の構成図である。FIG. 5 is a configuration diagram of a third embodiment.

【符号の説明】 Vd10:電源電圧 V22:バイアス電圧 10:前段回路 20:後段回路 40:抵抗(抵抗素子) 50:ツェナーダイオード 62:バイポーラトランジスタ(能動素子)[Explanation of Codes] Vd 10 : Power supply voltage V 22 : Bias voltage 10: Pre-stage circuit 20: Post-stage circuit 40: Resistor (resistive element) 50: Zener diode 62: Bipolar transistor (active element)

───────────────────────────────────────────────────── フロントページの続き (72)発明者 松本 一宏 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 平山 雅裕 山梨県中巨摩郡昭和町大字紙漉阿原1000番 地 富士通カンタムデバイス株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kazuhiro Matsumoto 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Masahiro Hirayama, Showa-cho, Nakakoma-gun, Yamanashi 1000-slot, Awahara, Fujitsu Quantum Device Co., Ltd.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】前段回路から出力される信号の振幅を該前
段回路に与える電源電圧で調節し、且つ、前記信号を増
幅して出力する後段回路の動作点を、該後段回路のゲー
トに与えるバイアス電圧によって調節する電力増幅器に
おいて、 前段回路に与えられる電源電圧が該前段回路の出力の振
幅を増大させるときは、後段回路のゲートに与えるバイ
アスを浅く制御し、 一方、前段回路に与えられる電源電圧が該前段回路の出
力の振幅を減少させるときは、後段回路のゲートに与え
るバイアスを深く制御することを特徴とする電力増幅
器。
1. An amplitude of a signal output from a front stage circuit is adjusted by a power supply voltage applied to the front stage circuit, and an operating point of a rear stage circuit for amplifying and outputting the signal is applied to a gate of the rear stage circuit. In a power amplifier that is regulated by a bias voltage, when the power supply voltage applied to the preceding circuit increases the amplitude of the output of the preceding circuit, the bias applied to the gate of the following circuit is controlled to be shallow, while the power applied to the preceding circuit is controlled. A power amplifier characterized in that when the voltage reduces the amplitude of the output of the preceding circuit, the bias applied to the gate of the following circuit is deeply controlled.
【請求項2】前段回路の出力と後段回路の入力との間を
連結するカップリングコンデンサに並列接続した抵抗素
子を備えることを特徴とする請求項1記載の電力増幅
器。
2. The power amplifier according to claim 1, further comprising a resistance element connected in parallel to a coupling capacitor that connects the output of the front stage circuit and the input of the rear stage circuit.
【請求項3】前段回路の出力と後段回路の入力との間を
連結するカップリングコンデンサに並列接続したツェナ
ーダイオードを備えることを特徴とする請求項1記載の
電力増幅器。
3. The power amplifier according to claim 1, further comprising a Zener diode connected in parallel to a coupling capacitor that connects the output of the front stage circuit and the input of the rear stage circuit.
【請求項4】前段回路の電源電圧と所定の定電圧との差
電圧に相当する電圧を増幅して後段回路のバイアス電圧
とする能動素子を備えることを特徴とする請求項1記載
の電力増幅器。
4. The power amplifier according to claim 1, further comprising an active element that amplifies a voltage corresponding to a difference voltage between a power supply voltage of the front stage circuit and a predetermined constant voltage to be a bias voltage of the rear stage circuit. .
JP3303582A 1991-11-19 1991-11-19 Power amplifier Withdrawn JPH05145349A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3303582A JPH05145349A (en) 1991-11-19 1991-11-19 Power amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3303582A JPH05145349A (en) 1991-11-19 1991-11-19 Power amplifier

Publications (1)

Publication Number Publication Date
JPH05145349A true JPH05145349A (en) 1993-06-11

Family

ID=17922741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3303582A Withdrawn JPH05145349A (en) 1991-11-19 1991-11-19 Power amplifier

Country Status (1)

Country Link
JP (1) JPH05145349A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5909643A (en) * 1995-11-24 1999-06-01 Matsushita Electric Industrial Co., Ltd. Transmitter power varying device having a bypass line for a power amplifier
WO2000002306A1 (en) * 1998-07-06 2000-01-13 Nec Corporation Power amplifier
US6188283B1 (en) 1998-04-16 2001-02-13 Matsushita Electric Industrial Co., Ltd. Amplifier and semiconductor device therefor
US6750718B2 (en) 2002-07-03 2004-06-15 Mitsubishi Denki Kabushiki Kaisha Radio-frequency amplifier
WO2010060892A1 (en) * 2008-11-25 2010-06-03 Audioasics A/S Dynamically biased amplifier

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5909643A (en) * 1995-11-24 1999-06-01 Matsushita Electric Industrial Co., Ltd. Transmitter power varying device having a bypass line for a power amplifier
US6188283B1 (en) 1998-04-16 2001-02-13 Matsushita Electric Industrial Co., Ltd. Amplifier and semiconductor device therefor
WO2000002306A1 (en) * 1998-07-06 2000-01-13 Nec Corporation Power amplifier
US6466095B1 (en) 1998-07-06 2002-10-15 Nec Corporation Power amplifier
US6750718B2 (en) 2002-07-03 2004-06-15 Mitsubishi Denki Kabushiki Kaisha Radio-frequency amplifier
WO2010060892A1 (en) * 2008-11-25 2010-06-03 Audioasics A/S Dynamically biased amplifier
US8958576B2 (en) 2008-11-25 2015-02-17 Invensense, Inc. Dynamically biased amplifier

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Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19990204