JPH05144959A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05144959A JPH05144959A JP3302087A JP30208791A JPH05144959A JP H05144959 A JPH05144959 A JP H05144959A JP 3302087 A JP3302087 A JP 3302087A JP 30208791 A JP30208791 A JP 30208791A JP H05144959 A JPH05144959 A JP H05144959A
- Authority
- JP
- Japan
- Prior art keywords
- cap
- package
- opening
- semiconductor chip
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置に係り、特に
キャップにより封止すべき面積の大きい半導体装置に関
する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a large area to be sealed with a cap.
【０００２】近年、半導体素子の大型化に伴いキャビテ
ィサイズも大きくなり、これを封止するキャップも大き
くなっている。In recent years, as the size of semiconductor elements has increased, the size of the cavity has increased, and the cap for sealing the cavity has also increased.
【０００３】したがって、キャップが変形しやすくなる
ため、変形しにくいキャップが要求されている。Therefore, since the cap is easily deformed, a cap which is not easily deformed is required.
【０００４】[0004]
【従来の技術】図１０は従来の一例の断面図を示す。同
図中、１は半導体チップを示す。半導体チップ１はパッ
ケージ５に形成された接触子５ａ（例えばテープリー
ド）に接続される。パッケージ５には接触子（例えばテ
ープリード）５ａの反対面に端子５ｂが形成されてお
り、接触子５ａは端子５ｂと電気的に接続される。半導
体チップ１は接触子５ａ及び端子５ｂを介して外部と接
続される。2. Description of the Related Art FIG. 10 shows a sectional view of an example of the prior art. In the figure, 1 indicates a semiconductor chip. The semiconductor chip 1 is connected to the contacts 5a (for example, tape leads) formed on the package 5. A terminal 5b is formed on the surface of the package 5 opposite to the contactor (for example, tape lead) 5a, and the contactor 5a is electrically connected to the terminal 5b. The semiconductor chip 1 is connected to the outside via the contacts 5a and the terminals 5b.
【０００５】ヒートシンク２はキャップ３にろう材４に
よりキャップ３の開口部３ａを覆うように固着される。
このとき、半導体チップ１はヒートシンク２に固着され
る。キャップ３はコバール（Ｆｅ−Ｎｉ−Ｃｏ合金）等
よりなる金属よりなり、プレス加工により縁部３ｃを有
する底付容器状に絞り変形させ収納部７を形成した構造
を有する。その底面３ｂには半導体チップ１とヒートシ
ンク２とを固着するための開口部３ａが形成される。キ
ャップ３は、縁部３ｃをパッケージ５にろう材６により
固着される。The heat sink 2 is fixed to the cap 3 with a brazing material 4 so as to cover the opening 3a of the cap 3.
At this time, the semiconductor chip 1 is fixed to the heat sink 2. The cap 3 is made of a metal such as Kovar (Fe—Ni—Co alloy) and has a structure in which the storage portion 7 is formed by pressing and deforming it into a bottomed container shape having an edge portion 3c. An opening 3a for fixing the semiconductor chip 1 and the heat sink 2 is formed on the bottom surface 3b. The cap 3 has an edge 3c fixed to the package 5 by a brazing material 6.
【０００６】従来の半導体装置に用いられていたキャッ
プ３は底面３ｂが平板状に構成されていた。The bottom surface 3b of the cap 3 used in the conventional semiconductor device has a flat plate shape.
【０００７】[0007]
【発明が解決しようとする課題】しかるに、従来の半導
体装置はキャップ３の底面３ｂが平板状に形成されてい
たため、収納部底面３ｂの面積が大きくなると底面３ｂ
に垂直方向の力に対して変形しやすくなる。このキャッ
プ３の変形によりキャップ３と半導体チップ１が接触
し、ショートなどの不良の原因となり、半導体装置の信
頼性が著しく低下すると共に歩留も悪くなる等の問題点
があった。However, since the bottom surface 3b of the cap 3 is formed in a flat plate shape in the conventional semiconductor device, when the area of the bottom surface 3b of the storage portion becomes large, the bottom surface 3b is formed.
It is easily deformed by vertical force. Due to the deformation of the cap 3, the cap 3 and the semiconductor chip 1 are brought into contact with each other, causing a defect such as a short circuit, resulting in a problem that the reliability of the semiconductor device is significantly lowered and the yield is deteriorated.
【０００８】本発明は上記の点に鑑みてなされたもの
で、被覆する面積が大きくなっても変形しにくいキャッ
プを有する半導体装置を提供することを目的とする。The present invention has been made in view of the above points, and an object of the present invention is to provide a semiconductor device having a cap that is difficult to be deformed even when the area covered is large.
【０００９】[0009]
【課題を解決するための手段】本発明は半導体素子が収
納されたパッケージの開口部をキャップにより覆い、パ
ッケージ内を密封してなる半導体装置において、前記キ
ャップのパッケージの主面に対し所定の間隔をおいて対
向している部分に凸部を有する形状に変形してなる。According to the present invention, in a semiconductor device in which an opening of a package containing a semiconductor element is covered with a cap and the inside of the package is hermetically sealed, the cap has a predetermined distance from the main surface of the package. It is deformed into a shape having a convex portion in a portion facing each other.
【００１０】[0010]
【作用】キャップのパッケージの主面に対し所定の間隔
をおいて対向している部分に凸部を有する形状に変形さ
せることにより、凸部により形成される凹凸形状により
キャップにかかる力を分散させることができるため、キ
ャップが変形しにくくなる。By deforming the cap into a shape having a convex portion at a portion facing the main surface of the package at a predetermined interval, the force applied to the cap is dispersed by the uneven shape formed by the convex portion. Therefore, the cap is less likely to be deformed.
【００１１】[0011]
【実施例】図１は本発明の第１実施例の断面図、図２は
本発明の第１実施例の平面図を示す。本実施例ではＰＧ
Ａ（Ｐｉｎ Ｇｒｉｄ Ａｒｒａｙ Ｐａｃｋａｇｅ）
型の半導体装置について説明する。同図中、８は半導体
チップを示す。1 is a sectional view of a first embodiment of the present invention, and FIG. 2 is a plan view of the first embodiment of the present invention. In this embodiment, PG
A (Pin Grid Array Package)
The semiconductor device of the type will be described. In the figure, 8 indicates a semiconductor chip.
【００１２】また、１２はパッケージで、例えば、セラ
ミック製の技材を積層した構成とされている。パッケー
ジ１２には外部回路との接続を行なう端子１２ａが植設
され、端子１２ａはスルーホール等により、半導体チッ
プ８との接続を行なう接触子（例えばテープリード）１
２ｂと接続されている。Reference numeral 12 is a package, which is constructed by laminating, for example, ceramic technical materials. A terminal 12a for connecting to an external circuit is implanted in the package 12, and the terminal 12a is a contactor (for example, tape lead) 1 for connecting to the semiconductor chip 8 by a through hole or the like.
2b is connected.
【００１３】半導体チップ８はパッケージ１２の接触子
１２ｂと接続される。The semiconductor chip 8 is connected to the contacts 12b of the package 12.
【００１４】１０はキャップで縁部１０ａを有し、コバ
ール等の金属よりなり、プレス加工等により底付容器状
に絞り変形され、形成される。キャップ１０にはその周
囲に縁部１０ａを有し、底面１０ｂには開口部１０ｂ−
１が形成される。開口部１０ｂ−１には半導体チップ８
が挿入され開口部１０ｂ−１を介してヒートシンク９と
接合される。Reference numeral 10 denotes a cap which has an edge portion 10a and is made of metal such as Kovar and is formed by being pressed and deformed into a bottomed container shape. The cap 10 has an edge portion 10a around its periphery, and the bottom surface 10b has an opening portion 10b-
1 is formed. The semiconductor chip 8 is provided in the opening 10b-1.
Is inserted and joined to the heat sink 9 through the opening 10b-1.
【００１５】また、開口部１０ｂ−１の周囲はプレス加
工等により外部に向って凸状に絞り変形された凸部１０
ｂ−２が形成される。Further, the periphery of the opening 10b-1 is convexly deformed in a convex shape toward the outside by press working or the like.
b-2 is formed.
【００１６】ヒートシンク９は開口部１０ｂ−１を覆う
ようにろう材１１によりキャップ１０に固着されると共
に、半導体チップ１と固着される。The heat sink 9 is fixed to the cap 10 by the brazing material 11 so as to cover the opening 10b-1, and also fixed to the semiconductor chip 1.
【００１７】このように凸部１０ｂ−２を底面１０ｂの
開口部１０ｂ−１周囲に形成することにより底面１０ｂ
に多数の屈曲点を形成することができるため応力を各点
に分散させることができ、変形しにくくなる。By thus forming the convex portion 10b-2 around the opening 10b-1 of the bottom surface 10b, the bottom surface 10b is formed.
Since a large number of bending points can be formed at the points, stress can be dispersed at each point, and deformation is less likely to occur.
【００１８】図３は本発明の第１実施例の他の例の断面
図を示す。同図中、図１，図２と同一構成部分には同一
符号を付し、その説明は省略する。FIG. 3 is a sectional view showing another example of the first embodiment of the present invention. In the figure, the same components as those in FIGS. 1 and 2 are designated by the same reference numerals, and the description thereof will be omitted.
【００１９】本実施例はフリップチップ方式の半導体装
置で、半導体チップ１７を端子１８ａと接続されたパタ
ーン上に接触子等を介さず直接載置し、外部との接続を
行なったものである。This embodiment is a flip-chip type semiconductor device in which the semiconductor chip 17 is directly placed on a pattern connected to the terminal 18a without a contactor or the like, and is connected to the outside.
【００２０】図４は本発明の第２実施例の断面図、図５
は本発明の第２実施例の平面図を示す。同図中、１３は
半導体チップ、１４はパッケージを示す。パッケージ１
４はセラミック板を積層した構成で、内部が段状に形成
され、内部底面に半導体チップ１３が固着される。FIG. 4 is a sectional view of the second embodiment of the present invention, and FIG.
Shows a plan view of a second embodiment of the present invention. In the figure, 13 is a semiconductor chip and 14 is a package. Package 1
Reference numeral 4 denotes a structure in which ceramic plates are laminated, the inside of which is formed in a step shape, and the semiconductor chip 13 is fixed to the bottom surface of the inside.
【００２１】また、パッケージ１４内部の段上にはメタ
ライズが形成され、半導体チップ１３はリード線１５に
よりパッケージ１４のメタライズと接続される。メタラ
イズはパッケージ１４の下面に植設された端子１４ｂと
接続されており、半導体チップ１３は端子１４ｂを介し
て外部回路との接続が行なわれる。Further, a metallization is formed on the step inside the package 14, and the semiconductor chip 13 is connected to the metallization of the package 14 by the lead wire 15. The metallization is connected to the terminal 14b implanted on the lower surface of the package 14, and the semiconductor chip 13 is connected to an external circuit via the terminal 14b.
【００２２】パッケージ１４の開口部１４ｃにメタルキ
ャップ１６をろう材１７により固着することにより封止
される。キャップ１６はメタル製の平板をプレス加工に
より変形させ、凸部１６ａがパッケージ１４内部に向っ
て形成されている。A metal cap 16 is fixed to the opening 14c of the package 14 with a brazing material 17 for sealing. The cap 16 is formed by deforming a metal flat plate by pressing to form a convex portion 16 a toward the inside of the package 14.
【００２３】図６は本発明の第３実施例の断面図を示
す。本実施例はＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋ
ａｇｅ）型の半導体装置に適用した例を示す。同図中、
１９は半導体チップを示す。半導体チップ１９はヒート
シンク２０に固着され、ヒートシンク２０はセラミック
板を積層し内部が上下方向に貫通したパッケージ２１の
上部開口部２１ａにろう材２２により固着される。FIG. 6 shows a sectional view of the third embodiment of the present invention. In this embodiment, a QFP (Quad Flat Pack) is used.
An example applied to an age) type semiconductor device is shown. In the figure,
Reference numeral 19 indicates a semiconductor chip. The semiconductor chip 19 is fixed to the heat sink 20, and the heat sink 20 is fixed by the brazing material 22 to the upper opening 21a of the package 21 in which ceramic plates are laminated and the inside penetrates in the vertical direction.
【００２４】パッケージ２１内部は、下方に向けて広が
る段差が形成されていて、段差にはガルウイング形状の
外部端子２１ｂと接続されたメタライズ（図示せず）が
形成される。半導体チップ１９はこのメタライズにボン
ディングワイヤ２３により接続され、外部回路と接続さ
れる。The inside of the package 21 is formed with a step extending downward, and a metallization (not shown) connected to the gull-wing-shaped external terminal 21b is formed in the step. The semiconductor chip 19 is connected to this metallization by a bonding wire 23 and is connected to an external circuit.
【００２５】また、パッケージ２１にはボンディングワ
イヤ２３を配線するために下部開口部２１ｄが形成され
ていて、下部開口部２１ｄはボンディングワイヤの形成
後キャップ２４をろう材２５によりろう付けすることに
より封止される。Further, the package 21 has a lower opening 21d for wiring the bonding wire 23. The lower opening 21d is sealed by brazing the cap 24 with the brazing material 25 after the bonding wire is formed. Be stopped.
【００２６】キャップ２４は平板をプレス加工等で絞り
変形させることにより、凸部２４ａが上方に向けて形成
されている。The cap 24 has a convex portion 24a formed upward by deforming a flat plate by pressing or the like.
【００２７】この凸部２４ａにより第１実施例と同様キ
ャップ２４が変形しにくくなる。The protrusion 24a makes it difficult for the cap 24 to be deformed as in the first embodiment.
【００２８】図７は本発明の第４実施例の断面図、図８
は本発明の第４実施例の平面図よりなる。本実施例はマ
ルチチップ方式で、ＰＧＡ型の半導体装置に適用した例
を示す。同図中、２６−１〜２６−９は半導体チップで
半導体チップ２６−１〜２６−９はパッケージ２８の上
面に形成された接触子（例えばテープリード）２８ｂと
接続される。接触子２８ｂはパッケージ下面に形成され
た外部端子２８ａと接続され、パッケージ２８の内部と
外部との接続が行なわれる。パッケージ２８にはキャッ
プ２９がろう材３１により固着される。FIG. 7 is a sectional view of the fourth embodiment of the present invention, and FIG.
Is a plan view of the fourth embodiment of the present invention. This embodiment shows an example applied to a PGA type semiconductor device by a multi-chip system. In the figure, reference numerals 26-1 to 26-9 denote semiconductor chips, and the semiconductor chips 26-1 to 26-9 are connected to contacts (for example, tape leads) 28b formed on the upper surface of the package 28. The contact 28b is connected to the external terminal 28a formed on the lower surface of the package, and the inside and outside of the package 28 are connected. A cap 29 is fixed to the package 28 with a brazing material 31.
【００２９】キャップ２９には複数の半導体チップ２６
−１〜２６−９に対応して複数の開口部２９−１〜２９
−９が形成されていて、開口部２９−１〜２９−９には
半導体チップ２６−１〜２６−９が挿入され、半導体チ
ップ２６−１〜２６−９は開口部２９−１〜２９−９を
介してヒートシンク２７と接触する。The cap 29 has a plurality of semiconductor chips 26.
-1 to 26-9 corresponding to a plurality of openings 29-1 to 29
-9 is formed, the semiconductor chips 26-1 to 26-9 are inserted into the openings 29-1 to 29-9, and the semiconductor chips 26-1 to 26-9 have openings 29-1 to 29-. It contacts the heat sink 27 via 9.
【００３０】キャップ２９はプレス加工等により絞り変
形され各開口部２９−１〜２９−９の周囲には凸部２９
ｂが外部に向って形成される。The cap 29 is squeezed and deformed by press working or the like, and convex portions 29 are formed around the openings 29-1 to 29-9.
b is formed toward the outside.
【００３１】ヒートシンク２７には半導体チップ２６−
１〜２６−９の底面が一致するよう凸部２７−１〜２７
−９が形成される。この凸部２７−１〜２７−９はキャ
ップ２９の開口部２９−１〜２９−９を覆うように形成
されて、キャップ２９にろう材３０により固着される。
このとき、ヒートシンク２７に半導体チップ２６−１〜
２６ｎが同時固着される。The heat sink 27 has a semiconductor chip 26-
The convex portions 27-1 to 27 so that the bottom surfaces of 1 to 26-9 are the same.
-9 is formed. The convex portions 27-1 to 27-9 are formed so as to cover the openings 29-1 to 29-9 of the cap 29 and fixed to the cap 29 by the brazing material 30.
At this time, the semiconductor chips 26-1 to 26-1 to the heat sink 27
26n are fixed simultaneously.
【００３２】したがって、凸部２７−１〜２７−９の高
さは半導体チップ２６−１〜２６ｎの厚さによって異な
ることになる。Therefore, the height of the convex portions 27-1 to 27-9 varies depending on the thickness of the semiconductor chips 26-1 to 26n.
【００３３】このように大きな被覆面積を有する半導体
装置において、キャップ２９に凸部２９ｂを形成するこ
とにより、多数の屈曲点を形成することができるため、
これにより矢印Ａ方向にかかる力を分散することがて
き、キャップ２９を変形しにくい構造とできる。In the semiconductor device having such a large covering area, by forming the convex portion 29b on the cap 29, a large number of bending points can be formed.
As a result, the force applied in the direction of arrow A can be dispersed, and the cap 29 can have a structure that is difficult to deform.
【００３４】図９は本発明の第４実施例の他の例の断面
図を示す。本実施例は第４実施例のマルチチップ方式の
半導体装置をフリップチップ方式のＱＦＰ型の半導体装
置に適用したものである。同図中、図７，図８と同一構
成部分には同一符号を付し、その説明は省略する。FIG. 9 shows a sectional view of another example of the fourth embodiment of the present invention. In this embodiment, the multi-chip type semiconductor device of the fourth embodiment is applied to a flip-chip type QFP type semiconductor device. 7, those parts which are the same as those corresponding parts in FIGS. 7 and 8 are designated by the same reference numerals, and a description thereof will be omitted.
【００３５】パッケージ３２にはその表面に半導体チッ
プ３３との接続パターンが形成され、接続パターンはパ
ッケージ３２下方に延出した外部端子３２ａと接続され
ている。半導体チップ３３は接続パターンと接触して、
外部端子３２ａと接続される。A connection pattern with the semiconductor chip 33 is formed on the surface of the package 32, and the connection pattern is connected with an external terminal 32a extending below the package 32. The semiconductor chip 33 contacts the connection pattern,
It is connected to the external terminal 32a.
【００３６】[0036]
【発明の効果】上述の如く、本発明によれば、キャップ
を凹凸形状に変形させることによりキャップにかかる負
荷を分散させることができるため、キャップが容易に変
形してしまうことがなく、半導体装置の大型化が可能と
なる等の特長を有する。As described above, according to the present invention, it is possible to disperse the load applied to the cap by deforming the cap into a concavo-convex shape, so that the cap is not easily deformed, and the semiconductor device. It has features such as large size.
【図面の簡単な説明】[Brief description of drawings]
【図１】本発明の第１実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the present invention.
【図２】本発明の第１実施例の平面図である。FIG. 2 is a plan view of the first embodiment of the present invention.
【図３】本発明の第１実施例の他の例の断面図である。FIG. 3 is a sectional view of another example of the first embodiment of the present invention.
【図４】本発明の第２実施例の断面図である。FIG. 4 is a sectional view of a second embodiment of the present invention.
【図５】本発明の第２実施例の平面図である。FIG. 5 is a plan view of a second embodiment of the present invention.
【図６】本発明の第３実施例の断面図である。FIG. 6 is a sectional view of a third embodiment of the present invention.
【図７】本発明の第４実施例の断面図である。FIG. 7 is a sectional view of a fourth embodiment of the present invention.
【図８】本発明の第４実施例の平面図である。FIG. 8 is a plan view of a fourth embodiment of the present invention.
【図９】本発明の第４実施例の他の例の断面図である。FIG. 9 is a sectional view of another example of the fourth embodiment of the present invention.
【図１０】従来の一例の断面図である。FIG. 10 is a sectional view of a conventional example.
８ 半導体チップ １０ キャップ １０ｂ−２ 凸部 １２ パッケージ ９ ヒートシンク 8 Semiconductor Chip 10 Cap 10b-2 Projection 12 Package 9 Heat Sink
Claims (2)
ージ（１２）をキャップ（１０）により覆い、該パッケ
ージ（１２）内を密封する半導体装置において、 前記キャップ（１０）の該パッケージの主面に対し所定
の間隔をおいて対向している部分に凸部（１０ｂ−２）
を有することを特徴とする半導体装置。1. A semiconductor device in which a package (12) accommodating a semiconductor chip (8) is covered with a cap (10) and the inside of the package (12) is hermetically sealed, the main surface of the package of the cap (10). A convex portion (10b-2) at a portion facing each other with a predetermined interval.
A semiconductor device comprising:
（９）に固着し、さらに該ヒートシンク（９）をキャッ
プ（１０）に固着し、該キャップ（１０）に開口した開
口部（１０ｂ−１）を介して該半導体チップ（８）を該
キャップ（１０）及び該キャップ（１０）が固着される
パッケージ（１２）により形成される収納部（１０ｂ）
内に収納してなる半導体装置において、 前記キャップ（１０）の前記開口部（１０ｂ−１）の周
囲を凸部（１０ｂ−２）を有する形状に変形させたこと
を特徴とする半導体装置。2. A semiconductor chip (8) is fixed to a heat sink (9), the heat sink (9) is fixed to a cap (10), and an opening (10b-1) opened in the cap (10) is formed. An accommodating portion (10b) formed by the semiconductor chip (8) via the cap (10) and a package (12) to which the cap (10) is fixed.
A semiconductor device housed inside, wherein the periphery of the opening (10b-1) of the cap (10) is deformed into a shape having a protrusion (10b-2).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3302087A JP2599233B2 (en) | 1991-11-18 | 1991-11-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3302087A JP2599233B2 (en) | 1991-11-18 | 1991-11-18 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05144959A true JPH05144959A (en) | 1993-06-11 |
| JP2599233B2 JP2599233B2 (en) | 1997-04-09 |
Family
ID=17904771
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3302087A Expired - Fee Related JP2599233B2 (en) | 1991-11-18 | 1991-11-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2599233B2 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5624155U (en) * | 1979-08-02 | 1981-03-04 | ||
| JPS57112055A (en) * | 1980-12-29 | 1982-07-12 | Fujitsu Ltd | Integrated circuit package |
| JPS63284836A (en) * | 1987-05-15 | 1988-11-22 | Ibiden Co Ltd | Package for surface mounting part |
-
1991
- 1991-11-18 JP JP3302087A patent/JP2599233B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5624155U (en) * | 1979-08-02 | 1981-03-04 | ||
| JPS57112055A (en) * | 1980-12-29 | 1982-07-12 | Fujitsu Ltd | Integrated circuit package |
| JPS63284836A (en) * | 1987-05-15 | 1988-11-22 | Ibiden Co Ltd | Package for surface mounting part |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2599233B2 (en) | 1997-04-09 |
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