JPH05144941A - Data treatment device - Google Patents

Abstract

PURPOSE:To extract parasitic resistance such as a wiring from a mask pattern data accurately, to appreciate and judge a value of a parasitic element from relation between the extracted parasitic element and a driving element, to decide a model of a parasitic element, to enable preparation of optimum simulation net list and to minimize intervention of man power. CONSTITUTION:A data extracting means 3 extracts necessary data from mask pattern data 1 according to designated extraction conditions 2, a parasitic element extracting means 4 extracts parasitic resistance, a judging means 5 appreciates and judges a value of a parasitic element from relation between a parasitic element and a driving element to decide a parasitic element model and a result output means 6 prepares an optimum simulation net list 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device for evaluating whether or not a designed mask pattern operates normally in LSI design.

[0002]

2. Description of the Related Art FIG. 13 is a block diagram showing a conventional data processing apparatus. In the figure, 1 is mask pattern data, 15 is circuit diagram data corresponding to the mask pattern data, 16 is parasitic resistance such as wiring, Parasitic element parameter extracting means for extracting parasitic capacitance, 17 is circuit connection data extracting means for extracting circuit connection data from the circuit diagram data 15,
Reference numeral 18 is a simulation input data creation for extracting only necessary data from the parasitic data obtained by the parasitic element parameter extraction means 16 and adding it to the data obtained by the circuit connection data extraction means 17 to create simulation input data. Means 19 are simulation input data obtained from the simulation input data creating means 18.

Conventionally, in order to evaluate whether or not a designed mask pattern operates normally, a method of executing simulation has been used. In the conventional data processing device, the circuit connection data extracting means 1 is previously extracted from the circuit diagram data 15.
Circuit connection data is extracted at 7 and parasitic resistance and parasitic capacitance such as wiring are extracted at the parasitic element parameter extraction means 16 from the mask pattern data 1 so that only necessary components are extracted in advance. Input data for simulation 18 is created by adding to the data. At that time, the model of the parasitic element was determined by a person by judging from the relationship between the parasitic element value and the driving element value.

[0004]

In the conventional data processing device, there is a problem in accurately extracting the parasitic resistance of wiring or the like.
Human intervention was required to create the optimal netlist for simulation including parasitic elements. Also,
Detection of a critical net has also been carried out by trial and error.

The present invention has been made in order to solve the above problems, and provides a data processing device capable of accurately extracting parasitic resistances of wirings and the like and performing optimum simulation for operation confirmation. The purpose is to do.
Further, the present invention has been made in order to solve the above problems, and accurately extracts the parasitic resistance of the wiring, etc., and detects the critical net from the relationship between the extracted parasitic element and the driving element. It is an object of the present invention to provide a data processing device for displaying on various drawings.

[0006]

A data processing apparatus according to a first aspect of the present invention is provided with, for example, a parasitic element extracting means for accurately extracting a parasitic resistance of a wiring and the like, and It determines the model of the parasitic element from the relationship with the driving element and outputs the optimum netlist for confirming the operation by simulation, and has the following elements. (A) Data extraction means for extracting necessary data from the mask pattern data according to a predetermined extraction condition, (b) Parasitic element extraction for recognizing a parasitic element from the extracted data and extracting a resistance value of the recognized parasitic element Means, (c) determination means for evaluating and determining the resistance value of the parasitic element based on the relationship between the parasitic element and the driving element for driving the parasitic element, and (d) an output in a predetermined format according to the evaluation / judgment result by the determining means. Result output means to perform.

The data processing device and the parasitic element extracting means according to the second aspect of the present invention include at least one or more of the following means. (A) means for extracting the resistance of the wiring portion, (b) means for extracting the resistance of the contact portion, (c) means for extracting the resistance of the diffusion portion,

A data processing apparatus according to a third aspect of the present invention includes a parasitic element extracting means for accurately extracting a parasitic resistance of a wiring and the like, and a critical net from the relationship between the extracted parasitic element and the driving element. Is detected and the optimum netlist is output. Alternatively, the critical net is displayed on the mask pattern diagram. Alternatively, the critical net is displayed on the circuit diagram. Alternatively, a parasitic element circuit diagram is created for each node and displayed on the screen according to the user's designation.

[0009]

In the invention of claim 1, the parasitic element extracting means accurately extracts the parasitic resistance of the wiring and the like, and the determining means further determines the parasitic element model from the relationship between the parasitic element and the driving element, Since the simulation netlist is generated, the optimum netlist is automatically created and human intervention can be minimized.

According to the second aspect of the present invention, the parasitic element extracting means obtains the resistance by distinguishing the wiring portion, the contact portion and the diffusion portion, so that the parasitic resistance value of each portion can be obtained more accurately.

In the invention according to claim 3, the output result means outputs each information as a list or a diagram, so that the result can be seen at a glance and the workability is improved.

[0012]

EXAMPLES Example 1. An embodiment of the invention described in claims 1, 2 and 3 will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a data processing device according to the present invention. In the figure, 1 is mask pattern data, 2 is extraction conditions for extracting necessary data from the mask pattern data, 3
Is data extraction means for extracting data according to specified extraction conditions, 4 is parasitic element extraction means for extracting parasitic resistance from the data extracted by the data extraction means 3, and 5 is driving with the extracted parasitic elements. Judgment means for evaluating / judging the value of the parasitic element from the relationship of the elements, 6 is an optimum simulation netlist 7 according to the evaluation / judgment result
Is a result output means for generating.

First, the operation will be described with reference to the block diagram shown in FIG. The data extraction unit 3 extracts necessary data from the mask pattern data 1 according to the specified extraction condition 2, the parasitic element extraction unit 4 extracts the parasitic resistance, and the determination unit 5 based on the result, The value of the parasitic element is evaluated and judged from the relationship between the parasitic element and the driving element to determine the model of the parasitic element, and the result output means 7 generates the optimum simulation netlist 7.

Next, the operations of the parasitic element extraction means 4 and the determination means 5 will be described in detail with reference to the flowchart of FIG. 2 and the mask pattern diagrams of FIGS. The processing is extraction of parasitic resistance of wiring polygon, extraction of contact resistance, MO
The diffusion resistance of the S transistor is extracted, and then evaluation and determination are performed in this order. First, on the basis of the data extracted by the data extracting means 3, in the wiring polygon data (FIG. 4), the contact portion between each side of the polygon data and the device or contact is obtained, and the polygon data and the device or contact are related to each other. (S1, S2). Next, the wiring polygon data for which the connection relationship has been taken is divided into rectangles (S3 to S).
10). The rectangular division method will be described below with reference to aluminum wiring data (FIG. 5). First, as shown in FIG. 6, it is divided by a line segment parallel to the X axis (S3), and further divided by a line segment parallel to the Y axis (S4). A rectangular corner polygon is searched for in the divided polygons, and the side of another polygon that is in contact with each side is corrected to the midpoint of the corner polygon (FIG. 7, S5), and a new node number is added to the intersection (S6). .. Next, if there is a polygon having an oblique line segment (S7), the polygon is divided by an oblique line segment (S8 in FIG. 8), and if a corner polygon exists in the divided polygons, it is described above. Similarly to the corner polygon, the side of another polygon that is in contact with each side is corrected to the midpoint of the corner polygon (S9 in FIG. 9), and a new node number is added to the intersection (S10). The resistance value of the wiring polygon data after the above rectangular division is obtained (S11). Next, contact polygons (ch1 in FIG. 3,
For ch2), the area of the polygon data is extracted (S
12) Find the contact resistance value. Next, contacts (channels in FIG. 3) that lead to device source / drain diffusion.
3) is searched for to establish a connection relationship with the device (S14).
Next, the sheet resistance coefficient of the source / drain diffusion of the MOS transistor is calculated from the channel width of the device and the distance between the device and the contact (S15). Next, series / parallel processing of the obtained parasitic resistance element is performed, and the value of the processed parasitic element is evaluated from the relationship with the driving element to determine the RC model.

Example 2. Hereinafter, another embodiment of the invention described in claim 3 will be described with reference to the drawings. FIG. 10 is a block diagram showing the configuration of the data processing apparatus according to this embodiment.
The same reference numerals are used for the same or corresponding parts as in the embodiment shown in FIG. In the drawing, 8 is a critical net display means on the mask pattern diagram for displaying a critical net on the mask pattern diagram based on the result of the determination means, and 9 is a mask pattern diagram displayed by the display means 8 described above. is there.

Next, the operation of the data processing apparatus of this embodiment will be described. It should be noted that the description of the same contents as those described in the section of the first embodiment will be omitted, and only the newly added means will be described. Based on the result of evaluation / judgment by the judging means 5, the critical net is displayed on the mask pattern diagram in a blinking manner on the mask pattern diagram so that a person can see it. As described above, according to this embodiment, the critical net display unit on the mask pattern diagram displays the critical net on the mask pattern diagram and gives a warning, thereby improving the design quality of the circuit.

Embodiment 3. Hereinafter, another embodiment of the invention described in claim 3 will be described with reference to the drawings. 11 is a block diagram showing the configuration of the data processing apparatus according to the present embodiment.
The same reference numerals are used for the same or corresponding parts as in the embodiment shown in FIG. In the figure, reference numeral 10 is a circuit diagram critical net display means for displaying a critical net on a mask pattern diagram based on the result of the determination means, and 11 is the circuit diagram critical net display means 1 described above.
It is a circuit diagram displayed by 0.

Next, the operation of the data processing apparatus of this embodiment will be described. It should be noted that the description of the same contents as those described in the section of the first embodiment will be omitted, and only the newly added means will be described. Based on the result evaluated / determined by the determination means 5, the critical net is displayed on the circuit diagram in a blinking manner on the circuit diagram so that a person can see it. As described above, according to this embodiment, the design quality of the circuit can be improved by the critical net display means on the circuit diagram displaying the critical net on the circuit diagram and giving a warning.

Example 4. Hereinafter, another embodiment of the invention described in claim 3 will be described with reference to the drawings. FIG. 12 is a block diagram showing the configuration of the data processing apparatus according to this embodiment.
The same reference numerals are used for the same or corresponding parts as in the embodiment shown in FIG. In the figure, 12 is a parasitic element circuit creating means for creating a parasitic element circuit diagram for each node based on the result of the judging means, and 13 is a parasitic element circuit diagram of a node designated on the circuit diagram. Parasitic element circuit diagram display means for, 14 is a circuit diagram displayed by the display means.

Next, the operation of the data processing apparatus of this embodiment will be described. It should be noted that the description of the same contents as those described in the section of the first embodiment will be omitted, and only the newly added means will be described. Based on the result evaluated / determined by the determination means 5, the parasitic element circuit creation means 12 creates a parasitic element circuit diagram for each node. Next, an attribute is added to correspond to the parasitic element circuit diagram created for each node of the circuit diagram. Then, the user designates the desired node on the circuit diagram to display the parasitic element circuit diagram of the node designated by the parasitic element circuit diagram display means 13 on the screen. As described above, according to this embodiment,
Since the parasitic element circuit diagram can be displayed for each node by the parasitic element circuit creation means and the parasitic element circuit diagram display means, the parasitic element information of the circuit can be understood at a glance and can be used for improving the design quality.

[0021]

As described above, according to the first and second aspects of the present invention, since the parasitic element extracting means is provided, the parasitic resistance can be accurately extracted, and the extraction result and the driving element are combined. Since the parasitic element value is evaluated from the relationship and the parasitic element model is determined and the simulation netlist is generated, the optimum netlist can be created and human intervention can be minimized. Further, the accuracy of the simulation can be improved by creating the optimum netlist, which in turn can improve the design quality.

As described above, according to the third aspect of the present invention, the visible display on the drawing is possible, the problematic portion can be seen at a glance, and the design quality can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data processing device according to an embodiment of the present invention.

FIG. 2 is a flow chart diagram showing processing of a parasitic element extraction means and a determination means in the data processing device according to the embodiment of the present invention.

FIG. 3 is a mask pattern diagram for explaining one embodiment of the present invention.

FIG. 4 is a diagram of wiring polygons for explaining an embodiment of the present invention.

FIG. 5 is a diagram of aluminum wiring for explaining an embodiment of the present invention.

FIG. 6 is a diagram of a rectangular division of aluminum wiring for explaining an embodiment of the present invention.

FIG. 7 is an exploded view of the aluminum wiring for explaining the embodiment of the present invention.

FIG. 8 is an exploded view of an oblique portion of the aluminum wiring for explaining the embodiment of the present invention.

FIG. 9 is an exploded view of the aluminum wiring for explaining the embodiment of the present invention.

FIG. 10 is a block diagram showing a configuration of a data processing device according to another embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a data processing device according to another embodiment of the present invention.

FIG. 12 is a block diagram showing a configuration of a data processing device according to another embodiment of the present invention.

FIG. 13 is a block diagram showing a configuration of a conventional data processing device.

[Explanation of symbols]

 1 Mask Pattern Data 2 Extraction Condition 3 Data Extraction Means 4 Parasitic Element Extraction Means 5 Judgment Means 6 Result Output Means 7 Simulation Netlist 8 Critical Net Display Means on Mask Pattern Diagram 9 Mask Pattern Diagram 10 Critical Net Display Means on Circuit Diagram 11 Circuit diagram 12 Parasitic element circuit creating means 13 Parasitic element circuit diagram displaying means 14 Parasitic element circuit diagram 15 Circuit diagram data 16 Parasitic element parameter extracting means 17 Circuit connection data extracting means 18 Simulation input data creating means 19 Simulation input data

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Claims (3)

[Claims] 1. A data processing device comprising the following elements: (a) data extracting means for extracting necessary data from mask pattern data according to a predetermined extraction condition; (b) recognizing a parasitic element from the extracted data; Parasitic element extraction means for extracting the recognized resistance value of the parasitic element, (c) Judgment means for evaluating and judging the resistance value of the parasitic element from the relationship between the parasitic element and the driving element for driving the parasitic element, (d) Result outputting means for outputting in a predetermined format according to the evaluation judgment result by the judging means. 2. The data processor according to claim 1, wherein said parasitic element extracting means has at least one of the following elements: (a) means for extracting a resistance of a wiring portion; and (b) a contact portion. Means for extracting the resistance of (c) the resistance of the diffusion portion, 3. The data output device according to claim 1, wherein said result output means has at least one of the following elements: (a) A netlist for simulation is created in accordance with the evaluation decision result by the decision means. Net list output means for outputting, (b) critical net display means on the mask pattern diagram for selecting a node that is considered to have an influence in the circuit and displaying it on the mask pattern in accordance with the evaluation determination result by the determination means, (c) determination A critical net display means on the circuit diagram for selecting a node which is considered to have an influence in the circuit according to the evaluation judgment result by the means, and (d) a parasitic net for each node according to the evaluation judgment result by the judgment means. Parasitic element circuit diagram display means for displaying the parasitic element circuit diagram by inversely converting the element into a circuit diagram.