JPH0442374A - Parasitic element display method - Google Patents

Abstract

PURPOSE:To easily confirm the electric parameter value of a parasitic element on a logic/circuit diagram and to easily verify a circuit by displaying the electric parameter value of the parasitic element extracted from a layout data on the logic/circuit diagram prepared when designing the logic circuit. CONSTITUTION:A data comparing and verifying part 14 compares an element wiring data extracted from the layout data with a logic/circuit diagram data stored in a storage part 3 and verifies those data, and based on a verified result, a connection information extracting part 15 extracts the connection information of the element including the electric parameter of the parasitic element. Based on the verified result, a parasitic element correspondence part 16 makes the part of generating the parasitic element correspondent to the wiring part of the logic/circuit diagram data, and the calculated electric parameter value is displayed at the correspondent wiring part on the logic/circuit diagram displayed on a CRT 2. Thus, the electric parameter value of the parasitic element can be easily confirmed on the logic/circuit diagram, and the circuit can be easily verified.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for displaying parasitic elements during circuit verification of a semiconductor integrated circuit such as an LSI designed on a CAD device, and in particular, relates to a method for displaying parasitic elements during circuit verification of a semiconductor integrated circuit such as an LSI designed on a CAD device. The present invention relates to a method for displaying electrical parameters of parasitic elements between.

[Conventional technology]

When designing a semiconductor integrated circuit such as an LSI, the designer first designs the logic circuit and detailed diagrams of the IC's internal circuits using a CAD device according to the required specifications, and then designs the layerer on the LSI chip. - A pattern is designed 81 using a CAD device. When verifying a designed 1, sl circuit, it is important to evaluate parasitic elements such as parasitic resistance and parasitic capacitance. Evaluation of parasitic elements is based on logic/human data.
Using the circuit diagram data and the layout pattern data that is the basis of the hook pattern, extract the parasitic elements of the circuit,
This is done by calculating and displaying the values of the electrical parameters.

FIG. 6 is a block diagram showing the functional configuration of a circuit verification system using a conventional parasitic element display method. In the figure, 1 is a CPU, CPII 1 is an element wiring extraction unit 11 that extracts element and wiring information from layout data;
Parasitic element extraction unit 1 that extracts parasitic elements of the extracted wiring
2. Parasitic resistance of parasitic elements.

An electrical parameter calculation unit 13 that calculates electrical parameter values such as parasitic capacitance values, a data comparison unit 14 that compares and verifies layout data and logic/circuit diagram data, and connections that extract connection information for circuit simulation. It is composed of an information extraction section 15.

The element wiring extraction section 11 extracts information on elements and wiring as element wiring data from the layout data stored in the storage section 3 by graphic calculation processing, and stores it in the storage section 3. The parasitic element extraction unit 12 extracts parasitic elements in wiring from the stored element wiring data, and stores the extracted parasitic elements in the storage unit 3 as parasitic element data.

The electrical parameter calculation unit 13 calculates electrical parameter values such as parasitic resistance values and parasitic capacitance values from the element and wiring graphic data based on the extracted element wiring data and parasitic element data, and stores them in the storage unit 3. . The calculated electrical parameter values are displayed on the CRT 2 on layout data. FIG. 8 is a diagram showing an example of a display, and shows electrical parameter values of parasitic elements of nodes when inverters are connected in series. The data comparison and verification unit 14 compares and verifies the element wiring data extracted from the layerer I data and the logic/circuit diagram data stored in the storage unit 3, and based on the verification results, the connection information extraction unit 15 A netlist, that is, element connection information including electrical parameters of parasitic elements is extracted.

Next, the operation of the conventional circuit simulation system will be explained. FIG. 7 is a flowchart showing the processing contents of CP[I1 during graphic verification in a conventional circuit verification system. First, information on elements such as transistors and resistors and information on wiring between them are extracted from layout data using graphical arithmetic processing (step #1). Next, based on the element and wiring information, extract the part where the parasitic element occurs in the wiring part (Step #2), and calculate the electrical parameter value using the graphic data such as the area data of the extracted part where the parasitic element occurs. In calculation step 43), the calculated electrical parameter value is added to the corresponding element and wiring information.

Next, as shown in FIG. 8, the calculated electrical parameter values are displayed on the corresponding elements or wiring parts on the layout data displayed on the CRT 2 (step #14). The circuit designer visually checks the electrical parameter values at the locations where parasitic elements that are thought to have an influence occur and the values estimated at the time of layout design (step #15). When it is determined that the electrical parameter value is close to the estimated value as a result of the check (
Step 115: vES) compares and verifies the element and wiring information extracted from the layout data with logic/circuit diagram data (step #4), and based on the verification results, element connection information including electrical parameter values. Then, a circuit simulation is executed based on the extracted connection information (Step #7). Then, the simulation results are checked by comparing them with the predicted expected values (step #8). If the simulation results are good, the simulation ends, and if the results are bad, the connection information for circuit simulation is corrected (step #10), and the circuit is re-circulated. Run the simulation (step 111) and check the circuit simulation (step 111).
2). If the simulation result is good, modify the layout data based on the modified connection information in step 113.
), return to step #l. Also, if the simulation result is not good in step #12, return to step #10,
Correct the connection result again.

If the electrical parameter value deviates significantly from the predicted expected value in step 115, the layout data is corrected and the process returns to step 1116>.

[Problem to be solved by the invention]

If an abnormality is found in the operation of a certain node as a result of circuit simulation, it is necessary to evaluate the electrical parameter values of that node in order to investigate the cause. However, with conventional parasitic element display methods, it is not possible to directly know the electrical parameter values of nodes, and as shown in Figure 8, circuit designers use the electrical parameter values displayed on the layout data to The electrical parameter values of the node were known and evaluated by replacing them on the diagram.

Therefore, there are problems in that it takes a long time to evaluate electrical parameter values, and circuit verification becomes a complicated task. Furthermore, if a problem occurs in the simulation execution results, it is very difficult to find the problem because the problem must be found using the extracted connection information.

The present invention has been made in view of the above circumstances, and it is possible to easily create a logic/circuit diagram by displaying electrical parameter values of parasitic elements extracted from layout data on the logic/circuit diagram created at the time of designing the logic circuit. It is an object of the present invention to provide a method for displaying parasitic elements that allows checking the electrical parameter values of parasitic elements and facilitating circuit verification.

[Means to solve the problem]

The parasitic element display method according to the present invention associates the occurrence part of the parasitic element with the wiring part on the logic/circuit diagram based on the element and wiring information extracted from the layout data, and displays the parasitic element on the logic/circuit diagram. The electrical parameter values are displayed.

[Effect]

In the present invention, when layout data is created, information on elements and wiring is extracted by means such as graphic processing,
The portion where the parasitic element occurs on the wiring is extracted, and its electrical variation value is calculated.

The extracted element and wiring information and the logic/circuit diagram data are then compared and verified, and the parts where the parasitic elements occur are associated with the wiring parts on the logic/circuit diagram. The calculated electrical parameter values are displayed in this section.

〔Example〕

Hereinafter, the present invention will be explained based on drawings showing embodiments thereof. FIG. 1 is a block diagram showing the functional configuration of a circuit verification system using the parasitic element display method according to the present invention. In the present invention, a database is created that includes element wiring data extracted from layout data and electrical parameter values corresponding thereto.

In the figure, l is a CPU, and the CPU 1 includes an element wiring extraction unit 11 that extracts element and wiring information from layout data, a parasitic element extraction unit 12 that extracts parasitic elements of the extracted wiring, and a parasitic element extraction unit 12 that extracts parasitic elements of the extracted wiring. resistance.

An electrical parameter calculation unit 13 calculates electrical parameter values such as parasitic electricity values, a data comparison verification unit 14 performs comparison verification between layout data and logic/circuit diagram data, and a data comparison verification unit 14 performs comparison verification between layout data and logic/circuit diagram data. It is composed of a parasitic element correspondence section 16 that associates a wiring portion with a portion where a parasitic element occurs, and a connection information extraction section 15 that extracts connection information for circuit simulation. The element wiring extraction section 11 extracts wiring information as element wiring data from the layout data stored in the storage section 3 by graphic calculation processing, and stores it in the storage section 3. The parasitic element extraction unit 12 extracts parasitic elements in the wiring from the stored element wiring data, and stores the parasitic elements in the storage unit 3 as data. The electrical parameter calculation unit 13 calculates electrical parameter values such as parasitic resistance values and parasitic capacitance values from the element and wiring graphic data based on the extracted element wiring data and parasitic element data, and stores them in the storage unit 3. . The data comparison and verification section 14 compares and verifies the element wiring data extracted from the layout data and the logic/circuit diagram data stored in the storage section 3, and based on the verification results, the connection information extraction section 15 generates a netlist for circuit simulation. , that is, element connection information including electrical parameters of parasitic elements is extracted.

In addition, the parasitic element correspondence unit 16 correlates the occurrence part of the parasitic element with the wiring part of the logic/circuit diagram data based on the verification result, and applies the calculated electrical parameter value to the logic/circuit displayed on the CRT 2. Displayed on the corresponding wiring part (node) on the diagram.

Next, the operation of the circuit verification system using the parasitic element display method of the present invention will be explained. Figure 2 shows the CP during circuit verification.
It is a flowchart showing the processing contents of [+1].

First, information on elements such as transistors and resistors and information on wiring between them are extracted from the layout data using graphic arithmetic processing (step 11). Next, based on the element and wiring information, the area where the parasitic element occurs in the wiring part is extracted (Step #2), and the electrical Calculate parameter values Step #3): Add the calculated electrical parameter values to the corresponding element and wiring information.

Next, the element and wiring information extracted from the layout data is compared and verified with the logic/circuit diagram data (step #4), and the verification results are used to identify the wiring parts on the logic/circuit diagram and the occurrence of parasitic elements. Make a correspondence with the parts (step #
5) Extract element connection information including electrical parameter values. Step 16). Execute circuit simulation based on the extracted connection information (Step #7). Then, check the simulation results by comparing them with the predicted expected values (step #8).
If the simulation results are good, the simulation ends; if the simulation results are bad, problems in the circuit simulation results are analyzed on the logic/circuit diagram, and the calculated electrical parameter values are displayed on the logic/circuit diagram to find the problem areas. (Step #9). Then, the connection information for the circuit simulation at the problematic location is corrected (Step #10), the circuit simulation is executed again (Step #11), and the circuit simulation is checked (Step #12). If the simulation result is good, the layout data of the problematic area is corrected based on the corrected connection information (step 1113), and the process returns to step #l. If the simulation result is not good in step #12, the process returns to step #9 and the electrical parameter values are displayed again.

Next, a method of outputting electrical parameter values to the logic/circuit diagram will be explained. 3 to 5 are diagrams showing display screens of logic circuit diagrams. If two element and gate symbols 2121 are connected to the node 23 of the logic/circuit diagram, the logic/circuit diagram is displayed and at the same time, the electrical parameter value of the parasitic resistance is displayed near the node 23, as shown in FIG. Is the parasitic resistance value 1? (=10.OKΩ) and the parasitic capacitance value C (=100PIl) are displayed.

Also, if there are three or more symbols 21 in the node 23 of the logic circuit diagram,
．． 21... is connected, two ports/
When the operator specifies IzA and IzB by key operation, etc., the sum of the electrical parameter values between symbols A and B is displayed as shown in FIG. Also, at this time, node 2
3 by the operator, a sub-window at the lower left of the screen is opened to display the connection relationships of the parasitic elements 22, 22, .

[Effects of the Invention] As explained above, in the present invention, information on elements and wiring extracted based on layout data is compared and verified with logic/circuit diagrams, and wiring parts on logic/circuit diagrams and parasitic resistances are determined. The electrical parameters of the parasitic resistance extracted from the LSI layout data are displayed on the logic/circuit diagram by associating them with the occurrence parts, so the electrical parameters at the nodes of wiring between elements can be displayed. Values can be easily confirmed on logic/circuit diagrams, and circuit verification can be easily performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a circuit verification system using the parasitic element display method according to the present invention, FIG. 2 is a flowchart showing the processing contents of the CPU during circuit verification, and FIGS.
Fig. 5 is a diagram showing an example of displaying parasitic elements, Fig. 6 is a block diagram showing the configuration of a circuit verification system using a conventional parasitic element display method, and Fig. 7 is a diagram showing a conventional CPII during circuit verification.
FIG. 8 is a flowchart showing the processing contents, and FIG. 8 is a diagram showing an example of a conventional display of electrical parameter values of parasitic elements. 11... Element wiring extraction section 12... Parasitic element extraction section 13... Electrical parameter calculation section 14... Data comparison verification section 15... Connection information extraction section 16... Parasitic element correspondence section 21 . . . Symbol 22 . . Parasitic element 23 . . . Node In the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) A parasitic element display method that extracts a portion where a parasitic element occurs from layout data of a semiconductor integrated circuit, calculates the electrical parameter value of the extracted portion where the parasitic element occurs, and displays the calculated electrical parameter value. In the step, information on elements and wiring of the semiconductor integrated circuit is extracted from the layout data, the extracted information on elements and wiring is compared with logic/circuit diagram data of the semiconductor integrated circuit, and extracted parasitic The method is characterized in that the generation part of the element is associated with the wiring part on the logic/circuit diagram, and the calculated electrical parameter value is displayed on the generation part of the parasitic element on the logic/circuit diagram. How to display parasitic elements.