JPH0514394A - Cell phase change circuit - Google Patents

Abstract

PURPOSE:To automatically recover trouble after release of an input condition even at the time of abnormal write or read and to prevent the loss of cells to minimize an influence of trouble. CONSTITUTION:Input data 10 and a write-pulse 12 are written in a FIFO 1, and its contents are outputted by a read permission signal 30. The output of the FIFO 1 and a read pulse 21 are written in a register 230. A read control means 200 gives the read permission signal 30 to the FIFO 1 and the register 230 based on a read clock signal 21, a read pulse 22, a write pulse 24, and the read pulse held in the register 230 and gives a control signal 25 to a selector 210 to selectively output output data 20.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used in a cell phase transfer circuit between ISDN asynchronous transfer mode circuits. In particular, an asynchronous transfer mode (A in which a cell having a fixed bit length is used as a unit, and clock signals and cell phase pulses different from each other operate
TM) circuit can be transmitted and received between circuits, and even if the input side and output side cell phase pulses are input in an abnormal cycle, they are subordinate to that and compensate the operation that minimizes the effect of cycle fluctuations. The present invention relates to a cell phase transfer circuit.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram of a conventional cell phase transfer circuit. FIG. 5 is a time chart showing the operation of the conventional cell phase transfer circuit.

Conventionally, as shown in FIGS. 4 and 5, a cell phase transfer circuit uses a FIFO unit 3 of a bit unit or a byte unit which is not conscious of the cell length of a predetermined cycle TC, and a write clock signal on the input side. 11 and the write pulse (cell phase pulse) 12, the input data 10 delimited by the write pulse 12 is divided into one cell D _n and D _n , respectively.
Writing was performed as _{n + 1} , D _{n + 2} , ....

Similarly, on the output side, the read clock signal 21
In accordance with the read pulse 22 and the read pulse 22, the data held in the FIFO 3 is sequentially read and output as cells in the time zone delimited by the read pulse 22 (read data 2
3). In the above series of operations, the control means 4 causes the number of write cells identified by the write clock signal 11 and the write pulse 12, the read clock signal 21 and the read pulse 22.
The number of read cells identified by
The number of held cells is recognized, and if there is no cell to be read, the selector 210 is switched by the control signal 28 to select the output of the insignificant cell generating means 220 to output the insignificant cell. .

[0005]

However, in such a conventional cell phase transfer circuit, the clock side and the pulse input of the read side and the value of the predetermined period TC are constantly guaranteed on the write side. That was the assumption. If it is not guaranteed for that reason, for example, when a clock signal or a pulse is missing due to a malfunction of an external circuit and a pseudo pulse is generated due to mixing of noise, a phase shift of writing or reading of a cell occurs and excess data is stored in the FIFO 3. Remains. The residual data causes a phase shift between the read pulse 22 and the read data cell 23 on the output side, and the conventional circuit cannot autonomously recognize the occurrence of the failure. Furthermore, as a secondary obstacle, the control means 4 cannot recognize the FIF.
O3 has a problem (for example, overflow or underflow), and when initialized, all other normal cells in the FIFO 3 are discarded, and the operation of the peripheral circuits is suspended during that period.

The present invention solves the above problems.
(EN) Provided is a cell phase transfer circuit capable of automatically recovering after recovery of an input condition even if abnormal writing or reading is performed, and suppressing the propagation of a failure to a necessary minimum without losing a cell. The purpose is to

[0007]

SUMMARY OF THE INVENTION The present invention is a FIFO that holds cells of a predetermined cycle input in synchronization with a write pulse.
And a cell phase transfer circuit including a cell that generates a specified cell, and a read-out permission to write the write pulse together with the cell based on the write clock signal to the FIFO, and to input the read clock signal. A register for outputting the contents based on the signal, for writing the output and read pulse of the FIFO on the basis of the read enable signal and the read clock signal, and outputting the contents on the basis of the read clock signal, and a control signal to be input. A selector that selects the output of the FIFO, the register, and the involuntary cell generation means based on the above, and the read permission based on the read pulse, the read clock signal, the write pulse from the FIFO, and the read pulse held in the register. A read control means for outputting a signal and a control signal. To.

Further, according to the present invention, the read control means determines the cycle of the next read pulse by means for outputting the read enable signal when the read pulse is inputted and the read pulse held in the register. When the inspection means to be inspected and the write pulse and the read pulse from the FIFO are synchronized and the inspection result of the inspection means is appropriate, the control signal is given to the selector to output the cell from the FIFO. When the inspection result is inappropriate, the output of the read enable signal is prohibited, and the control signal is given to the selector until the two pulses are synchronized and the two pulses are synchronized, and the cell from the register is output. FIFO above
Is empty and there is no write pulse from it, the means for supplying the control signal to the selector until the write pulse is detected to output the insignificant cell from the insignificant cell generating means is included. it can.

[0009]

A write pulse is written in the FIFO together with a cell on the basis of the write clock signal, and the content is output on the basis of the read clock signal and the input read permission signal. FI based on the read enable signal and the read clock signal to the register
The output and read pulse of the FO are output based on the write / read clock signal. The selector selects the output of the FIFO, the register, and the insignificant cell generation means based on the control signal that is input. The read control means outputs a read enable signal and a control signal based on the read pulse, the read clock signal, the write pulse from the FIFO and the read pulse held in the register.

As described above, even if abnormal writing or reading is performed, it is possible to automatically recover after the recovery of the input condition, and it is possible to minimize the spread of the failure without losing the cell.

[0011]

Embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a cell phase change circuit according to an embodiment of the present invention.

In FIG. 1, the cell phase changing circuit includes a FIFO 1 that holds input data 10 as cells having a predetermined cycle input in synchronization with a write pulse 12, and an insignificant cell generating means 220 that generates a specified insignificant cell. Equipped with.

The feature of the present invention is that the FI
Input data 10 to FO1 based on write clock signal 11
Together with the write pulse 12 and the read clock signal 2
1 and a means for outputting the content based on the input read permission signal 30. The output of the FIFO 1 and the read pulse 22 based on the read permission signal 30 and the read clock signal 21 are output based on the write read clock signal 21. A register 230, a selector 210 that selects the output of the FIFO1, the register 230, and the involuntary cell generation means 220 based on the input control signal 25, a read pulse 22, a read clock signal 21, a write pulse 24 from the FIFO 1, and a register 230. And a read control means 200 for outputting a read permission signal 30 and a control signal 25 based on the read pulse 12 held at.

The read control means 200 outputs the read permission signal 30 when the read pulse 22 is input, and the check means for checking the cycle of the next read pulse by the read pulse held in the register 230. And the FIFO
When the write pulse 24 and the read pulse 22 from 1 are synchronized and the inspection result 29 of this inspection means is appropriate, the control signal 25
To the selector 210 to output the read data 23 as a cell from the FIFO 1, and when the inspection result 29 is inadequate, the output of the read enable signal 30 is prohibited and the inspection result 29 becomes appropriate until the two pulses are synchronized. Control signal 2
5 is supplied to the selector 210 to cause the read data 26 to be output as a cell from the register 230. If the write pulse 24 from the FIFO 1 is empty and there is no write pulse 24, the control signal 25 is output until the write pulse 24 is detected. Selector 2
10 to output the insignificant cell from the insignificant cell generation means 220.

The operation of the cell phase transfer circuit having such a configuration will be described. FIG. 2 is a time chart showing the cell phase changing operation of the cell phase changing circuit of the present invention. FIG. 3 is a time chart showing the read operation of the cell phase changing circuit of the present invention.

Referring to FIG. 1, first, the write operation to the FIFO 1 will be described. Input data 10 input in synchronization with write clock signal 11 and write pulse 12 is written in FIFO 1 together with write pulse 12. At this time, even if a cell having an abnormal length occurs due to a failure in an external circuit, the cell is written into the FIFO 1 without being distinguished from a normal cell.

Next, the read operation for the FIFO 1 and the register 230 will be described. Here, the predetermined cycle of the normal read pulse 22 is TC. Read clock signal 2
When 1 and the read pulse 22 are input to the read control means 200, the read control means 200 outputs the read permission signal 30 to the FIFO 1 to instruct the read of the FIFO 1. FIFO
When 1 receives the read permission signal 30, the same read data 23 is simultaneously output to the register 230 and the selector 210.
At this time, the read pulse 22 also outputs the read data 23 from the FIFO 1 and the write pulse 24 simultaneously with the register 230.
Write to.

The read control means 200 recognizes that the output read data 23 of the FIFO 1 has a write pulse 24 indicating the beginning of the read data 23, and inputs the selector 210 to the output read data 23 of the FIFO 1 (of the selector 210). Switch to input 213). FIFO1 is read enable signal 3
When receiving 0 and outputting read data 23, the FIFO
If 1 is empty and there is no write pulse 24,
The read data 23 is written to the register 230 and the reading of the FIFO1 is continued until the write pulse 24 can be detected, and during that time, the input of the selector 210 is input so that the insignificant cell is output by the insignificant cell generation means 220. Enter 211
Switch to.

Next, the operation when the read pulse 22 is input in an abnormal cycle will be described with reference to FIGS. 2 and 3. The read pulse 22 _n is input, the FIFO 1 receives the read enable signal 30 and the read is enabled, and the read data 23
And read pulse 2 while outputting write pulse 24 _n
Read pulse 22 _n in read pulse cycle test position in register 230 when the 2 _n and read pulse 22 n _{+ 1} cycle erroneous due to external noise during the read pulse 22 _n 'is generated
When the cycle of the read pulse 22 _n ′ and the cycle of the read pulse 22 _n ′ is inspected and it is determined that the predetermined cycle TC is not normal, the read control means 200 inputs the selector 210 to the output read data 2
Switch to input 212 to be 6. At this time, the register 230 is read so that the read pulse 22 and the head of the read data 23 written in the register 230 always match.

Further, the FIFO 1 continues until the writing of the read data 23 into the register 230 is completely finished, and when the writing is finished, the reading of the FIFO 1 is stopped. Further, the read pulse 22 _{n + 1} is written in the register 230, and when it is confirmed that the predetermined cycle TC with the read pulse 22 _{n + 2} to be input next is normal, the reading of the FIFO 1 is restarted and the selector 210 of the selector 210 is restarted. The input 213 is switched so that the input becomes the output read data 23 of the FIFO1.

When the FIFO 1 is again read-enabled and the read data 23 is being output, the next read pulse 22
_{When n + 3} is missing, the read control means 200 stops the read permission signal 30 and stops the reading of the FIFO1, the read pulse 22 _{n + 4} is input, and the input of the selector 210 is continued until the read becomes possible. Is switched to the input 211 and the output is switched to the output of the involuntary cell generation means.

[0022]

As described above, according to the present invention, even if abnormal writing or reading is performed, the data is automatically recovered after the recovery of the input condition, and the propagation of the fault is performed without loss of cells. It has an excellent effect that it can be suppressed to the necessary minimum.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of a cell phase transfer circuit according to an embodiment of the present invention.

FIG. 2 is a time chart showing a transfer operation of the cell phase transfer circuit of the present invention.

FIG. 3 is a time chart showing a read operation of the cell phase transfer circuit of the present invention.

FIG. 4 is a block configuration diagram of a conventional cell phase transfer circuit.

FIG. 5 is a time chart showing a transfer operation of a conventional cell phase transfer circuit.

[Explanation of symbols]

1,3 FIFO 4 Control means 10 input data 11 Write clock signal 12 Write pulse 20 output data 21 Read clock signal 22 Read pulse 23, 26 Read data 24 Write pulse held in FIFO 25, 27, 28 control signal 29 test results 30 Read permission signal 200 Read control means 210 selector 220 Unintentional cell generation means 230 registers

Claims (2)

[Claims] 1. A cell phase transfer circuit comprising a FIFO for holding cells of a predetermined cycle input in synchronism with a write pulse, and an insignificant cell generating means for generating a specified insignificant cell, wherein the FIFO is written to the FIFO. Means for writing the write pulse together with the cell based on a clock signal, and outputting the content based on a read clock signal and an input read enable signal, and outputting and reading the FIFO based on the read enable signal and the read clock signal A register for writing a pulse and outputting its content based on the read clock signal, a selector for selecting the output of the FIFO, the register and the insignificant cell generation means based on an input control signal, the read pulse and the read clock signal , Based on the write pulse from the FIFO and the read pulse held in the register. Cell phase transfer circuit, characterized in that a read control means for outputting the read enable signal and the control signal can. 2. The read control means outputs the read enable signal when the read pulse is input, and an inspecting means for inspecting the cycle of the next read pulse by the read pulse held in the register. When the write pulse from the FIFO and the read pulse are synchronized and the inspection result of the inspection means is appropriate, the control signal is given to the selector to output the cell from the FIFO. When it is inappropriate, the output of the read enable signal is prohibited, and the control signal is given to the selector to output the cell from the register until the inspection result becomes appropriate and the two pulses are synchronized, and the FIFO becomes empty. When there is no write pulse from that state, the control signal is given to the selector until the write pulse is detected, and the involuntary cell generation process is performed. 2. The cell phase transfer circuit according to claim 1, further comprising means for outputting an insignificant cell from the stage.