JPH0514388A - Band control system for atm network - Google Patents

Band control system for atm network

Info

Publication number
JPH0514388A
JPH0514388A JP3159334A JP15933491A JPH0514388A JP H0514388 A JPH0514388 A JP H0514388A JP 3159334 A JP3159334 A JP 3159334A JP 15933491 A JP15933491 A JP 15933491A JP H0514388 A JPH0514388 A JP H0514388A
Authority
JP
Japan
Prior art keywords
cell
cells
vci
band
storage means
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3159334A
Other languages
Japanese (ja)
Other versions
JP2862709B2 (en
Inventor
Edamasu Kamoi
條益 鴨井
Tomoji Kuroyanagi
智司 黒柳
Kazuo Hajikano
一雄 初鹿野
Ryuichi Takechi
竜一 武智
Takeshi Kawasaki
健 川崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15933491A priority Critical patent/JP2862709B2/en
Publication of JPH0514388A publication Critical patent/JPH0514388A/en
Application granted granted Critical
Publication of JP2862709B2 publication Critical patent/JP2862709B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

PURPOSE:To control the increase of momentary traffic to reduce abandonment of cells by reading out cells in a storage means with periods of proportions corresponding to declared bands to smooth and output burst cells. CONSTITUTION:Input cells from a communication line are separated in accordance with set VCI numbers by a separating means 1 and are stored in cell storage means 2. Data corresponding to band declaration values declared for respective VCI numbers are preliminarily set to a control means 5, and cells are read out from cell storage means 2 at each timing and are multiplexed by a cell multiplexing means 4 and are outputted to the communication line. Since cells are read out with periods of proportions corresponding to declared bands in this manner, cells are outputted at speeds in declared bands and burst cells are smoothed and outputted. Consequently, the increase of momentary traffic is controlled to reduce abandonment of cells. Further, a maximum cell storage value setting means 3 is added to adjust the abandonment volume of cells.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はATM網における帯域制
御方式に関し,特にATM網の通信路上へ送出されるセ
ルの帯域が申告値通りに守られているかを監視するポリ
シング機構を備える帯域制御方式に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a band control system in an ATM network, and more particularly to a band control system provided with a policing mechanism for monitoring whether or not the band of cells transmitted to the communication path of the ATM network is protected according to a declared value. Regarding

【0002】ATM(Asynchronous Transfer Mode) の
通信では,一定速度の音声やデータの他に可変速度の画
像やバーストデータのような情報を扱うため,網側では
通信帯域を把握することが非常に困難である。従って,
瞬時的に申告された帯域よりも大きいトラヒックが入力
されることがある。そのため,網が過負荷状態となって
サービス品質が低下(セル廃棄など)する可能性があ
る。
In ATM (Asynchronous Transfer Mode) communication, information such as variable speed images and burst data is handled in addition to constant speed voice and data, so it is very difficult for the network side to grasp the communication band. Is. Therefore,
Traffic that is larger than the declared bandwidth may be input instantaneously. As a result, the network may become overloaded and the quality of service may deteriorate (cell discard, etc.).

【0003】このような問題に対処するために,網の入
力部にトラヒック量を監視して何らかの規制処理を行う
帯域制御を行う必要がある。
In order to deal with such a problem, it is necessary to perform bandwidth control by monitoring the traffic volume at the input part of the network and performing some kind of restriction processing.

【0004】[0004]

【従来の技術】図8は従来例1の構成である。図8にお
いて,80は入力通信路の各セルのヘッダに含まれたV
CI(各呼に対応して付与された仮想チャネル番号:Vi
rtual Channel Identifire) を識別するVCI識別手
段,81は各VCIの番号#1〜#nに対応して設けら
れたセル通過計数手段,82は各VCIに対応する呼に
ついて予め申告された帯域(例えば,ピーク値)に対応
するセル数の値(一定時間内のセル数)を保持する申告
計数保持手段,83は比較手段,84は論理和手段,8
5は廃棄手段である。
2. Description of the Related Art FIG. 8 shows a configuration of a first conventional example. In FIG. 8, 80 is V included in the header of each cell of the input communication path.
CI (Virtual channel number assigned to each call: Vi
rtual channel identifire), VCI identification means, 81 is a cell passage counting means provided corresponding to each VCI number # 1 to #n, and 82 is a band declared in advance for a call corresponding to each VCI (for example, , A peak value) and a value of the number of cells (the number of cells within a certain time period) corresponding to the peak value).
5 is a disposal means.

【0005】動作を説明すると,入力通信路上に複数の
呼のセルが多重化されて入力すると,VCI識別手段8
0において各セルのVCIが識別され,識別されたVC
Iに対応する出力(VCI#1〜#n)を発生する。こ
れにより,出力が供給された各VCI番号毎のセル通過
計数手段81が計数を行う。各VCIに対応するセル通
過計数手段81の一定時間内の計数値(これをAとす
る)と,申告計数保持手段82に設定された申告数(こ
れをBとする)は比較手段83で比較され,Aの値がB
の値をオーバすると,そのVCIを表示する出力が発生
し,論理和手段84から廃棄手段85に対してこのVC
Iを持つセルを廃棄する指示が与えられる。これにより
廃棄手段は,該当VCIを持つセルを廃棄して出力通信
路へ送出しない。
To explain the operation, when a plurality of call cells are multiplexed and input on the input communication path, the VCI identifying means 8
0, the VCI of each cell is identified, and the identified VC
Outputs (VCI # 1 to #n) corresponding to I are generated. As a result, the cell passage counting means 81 for each VCI number to which the output is supplied counts. The comparison means 83 compares the count value (denoted as A) of the cell passage counting means 81 corresponding to each VCI with the declared number (denoted as B) set in the declared count holding means 82. And the value of A is B
When the value of is exceeded, an output for displaying the VCI is generated, and the logical sum means 84 sends this VC to the discard means 85.
An instruction is given to discard the cell with I. As a result, the discarding unit discards the cell having the corresponding VCI and does not send it to the output communication path.

【0006】次に図9に示す従来例2の構成を説明す
る。図9の,90は帯域監視手段,91はマーク付加手
段,92はATM網である。この従来例2は,マークド
セル(marked cell)方式と称され,帯域監視手段90
は,上記従来例1と同様に入力通信路上のセルをVCI
毎に一定時間内の到着数を計数し,各VCI毎の申告値
(制御部より入力する)と比較して到着セル数が申告値
をオーバすると,該当VCIが違反したことをマーク付
加手段91に指示する。これにより,マーク付加手段9
1は,該当VCIを持つセルに対しマーク(例えば,ヘ
ッダ内の予め決められた特定ビットに“1”を設定)を
付して,ATM網92に送出する。ATM網92では,
網内において輻輳が発生するとマークが付されたセルを
優先的に廃棄する処理を行う。
Next, the configuration of the conventional example 2 shown in FIG. 9 will be described. In FIG. 9, 90 is a band monitoring means, 91 is a mark adding means, and 92 is an ATM network. This conventional example 2 is called a marked cell system and is a band monitoring means 90.
In the same manner as in Conventional Example 1 above, the cells on the input communication path are
The number of arrivals within a fixed time is counted for each time, and when the number of arriving cells exceeds the declared value by comparing with the declared value (input from the control unit) for each VCI, the mark adding means 91 indicates that the corresponding VCI is violated. Instruct. Thereby, the mark adding means 9
The numeral 1 attaches a mark (for example, "1" is set to a predetermined specific bit in the header) to the cell having the corresponding VCI, and sends it to the ATM network 92. In the ATM network 92,
When congestion occurs in the network, the marked cells are preferentially discarded.

【0007】[0007]

【発明が解決しようとする課題】上記した従来例1の方
式では,一定時間内のセルの到着数を監視していたため
平均的なトラヒックの変動にしか対応できず,瞬時的に
トラヒックが増大した場合には制御できないという問題
があった。
In the method of the prior art 1 described above, since the number of arrivals of cells within a fixed time is monitored, only the fluctuation of average traffic can be dealt with, and the traffic increases instantaneously. There was a problem that it could not be controlled.

【0008】従来例2の方式では,平均的には帯域が守
られているにも関わらず何らかの影響で瞬時的にバース
ト性が増大したセルの場合,ポリシング制御部から出力
するセルのトラヒック特性は何ら変化しないためATM
網でセルが廃棄されてサービス品質が低下するという問
題があった。
In the system of the second conventional example, in the case of a cell in which the burst property is instantaneously increased by some influence despite the band being protected on average, the traffic characteristic of the cell output from the policing controller is ATM because there is no change
There has been a problem that cells are discarded in the network and the quality of service deteriorates.

【0009】本発明は瞬時的にトラヒックが増大したセ
ルに対してセル廃棄を少なくすると共に申告された帯域
を越えないように制御することができるATM網におけ
る帯域制御方式を提供することを目的とする。
It is an object of the present invention to provide a band control method in an ATM network which can control a cell whose traffic is instantaneously increased so as to reduce cell discard and not to exceed a declared band. To do.

【0010】[0010]

【課題を解決するための手段】図1は本発明の原理構成
図,図2は読出し制御手段の第1の原理構成図,図3は
読出し制御手段の第2の原理構成図である。
FIG. 1 is a block diagram showing the principle of the present invention, FIG. 2 is a block diagram showing the first principle of read control means, and FIG. 3 is a block diagram showing the second principle of read control means.

【0011】図1において,1はセルをVCIに応じて
分離するセル分離手段,2は各VCIに対応して設けら
れたセル蓄積手段,3はセル蓄積手段2に蓄積可能なセ
ル数が設定される最大セル蓄積量設定手段,4はセル多
重手段,5は申告帯域に応じてセル蓄積手段からのセル
を読出す読出し制御手段である。
In FIG. 1, 1 is a cell separating means for separating cells according to VCI, 2 is a cell accumulating means provided corresponding to each VCI, and 3 is a number of cells accumulating in the cell accumulating means 2. Maximum cell storage amount setting means, 4 is cell multiplexing means, and 5 is read control means for reading cells from the cell storage means in accordance with the declared band.

【0012】また,図2,図3において,20は選択番
号蓄積手段,21は周期カウンタ,22はランダムカウ
ンタを表す。本発明は入力セルをVCI毎に設けられた
セル蓄積手段に各VCIのセルを蓄積し,その際最大セ
ル蓄積量設定手段に設定されたセル量以上のセルは廃棄
する一方で,各セル蓄積手段に蓄積したセルはそれぞれ
のVCIの申告帯域に対応した周期で読み出すものであ
る。
In FIGS. 2 and 3, 20 is a selection number accumulating means, 21 is a cycle counter, and 22 is a random counter. According to the present invention, input cells are stored in the cell storage means provided for each VCI, and cells of each VCI are stored. At this time, cells having a cell amount equal to or larger than the cell amount set in the maximum cell storage amount setting means are discarded, while storing each cell. The cells stored in the means are read out at a cycle corresponding to each VCI declared band.

【0013】[0013]

【作用】図1において入力通信路からのセルはセル分離
手段1に入力してセルのヘッダに設定されたVCIの番
号に応じて分離され,各VCIに対応する各セル蓄積手
段2に蓄積される。各セル蓄積手段2はFIFO(Firs
t In First Out) 型のメモリで構成され一定容量を持
ち, 蓄積されたデータはセル多重手段4により選択され
た1つのセル蓄積手段2の先頭のセルを読出すと,次の
タイミングでは他のセル蓄積手段2が選択され,その中
の先頭のセルを読出すことにより出力通信路に多重化し
て出力される。
In FIG. 1, cells from the input communication path are input to the cell separation means 1 and separated according to the VCI number set in the cell header, and stored in each cell storage means 2 corresponding to each VCI. It Each cell storage means 2 has a FIFO (Firs
t In First Out) type memory having a certain capacity, and the accumulated data is read out from the head cell of one cell accumulating means 2 selected by the cell multiplexing means 4 The cell accumulating means 2 is selected, and the first cell in the cell accumulating means 2 is read and multiplexed on the output communication path and output.

【0014】読出しは読出し制御手段5により行われ,
読出し制御手段5には予め各VCI(呼)に対して予め
申告された帯域申告値に対応するデータが制御部(図示
せず)から設定されており,各タイミング毎に読出し制
御手段5からセル蓄積手段2を選択する信号が発生する
と,対応するセル蓄積手段2からセルが読出される。
Reading is performed by the read control means 5,
Data corresponding to a band declaration value previously declared for each VCI (call) is set in the read control means 5 from a control unit (not shown), and the read control means 5 sets cells at each timing. When a signal for selecting the storage means 2 is generated, a cell is read from the corresponding cell storage means 2.

【0015】このように各VCIに応じてそれぞれの申
告帯域に対応した割合の周期で各セル蓄積手段2を読出
すことにより,出力通信路には各VCIのセルが申告帯
域内の速度で且つバースト的なセルを平滑化して出力す
ることができる。
In this way, by reading out each cell accumulating means 2 in a cycle corresponding to each declared band according to each VCI, the cells of each VCI are at the speed within the declared band on the output communication path. Burst cells can be smoothed and output.

【0016】図1には各セル蓄積手段2に対応して最大
セル蓄積量設定手段3が設けられている。この最大セル
蓄積量設定手段3には,制御部から各VCI毎に申告さ
れた帯域申告値に応じたセル蓄積手段2に蓄積格納なセ
ル数(最大値)を設定してセル蓄積量を制御可能にする
場合に使用する。この最大セル蓄積量設定手段3から最
大値がセル蓄積手段2に供給されると,セル蓄積手段2
は蓄積されたセル数が最大値に達するとそれ以上のセル
が入力されても蓄積を行わない(セル廃棄)。このた
め,バースト的に瞬間的にセルが多数到着してもこの段
階で抑制することができる。
In FIG. 1, maximum cell storage amount setting means 3 is provided corresponding to each cell storage means 2. The maximum cell storage amount setting means 3 controls the cell storage amount by setting the number of cells (maximum value) that can be stored and stored in the cell storage means 2 according to the band declared value declared for each VCI from the control unit. Used when possible. When the maximum value is supplied from the maximum cell storage amount setting means 3 to the cell storage means 2, the cell storage means 2
When the number of accumulated cells reaches the maximum value, does not accumulate even if more cells are input (cell discard). Therefore, even if a large number of cells arrive instantaneously in a burst, it can be suppressed at this stage.

【0017】図2に示す読出し制御手段(図1の5)の
第1の原理構成を説明する。制御部から,選択番号蓄積
手段20の各アドレスに,VCIの番号(またはセル蓄
積手段2の番号)のデータが書き込まれる。このデータ
は,各セル蓄積手段2に蓄積される各VCIの申告帯域
に比例した個数だけ均等な間隔をおいたアドレスに格納
される。選択番号蓄積手段20は,周期カウンタ21の
カウント値を読出しアドレスとして読出され,読出され
たデータはセル多重手段4へ供給される。この例では,
選択番号蓄積手段20の各アドレスは周期カウンタ21
によりアドレスの順に読出される。
The first principle configuration of the read control means (5 in FIG. 1) shown in FIG. 2 will be described. Data of the VCI number (or the cell storage unit 2 number) is written to each address of the selection number storage unit 20 from the control unit. This data is stored in addresses that are evenly spaced by the number proportional to the declared bandwidth of each VCI stored in each cell storage unit 2. The selection number accumulating means 20 is read with the count value of the cycle counter 21 as a read address, and the read data is supplied to the cell multiplexing means 4. In this example,
Each address of the selection number storage means 20 has a cycle counter 21.
Are read in the order of addresses.

【0018】次に図3に示す読出し制御手段の第2の原
理構成を説明する。図3の選択番号蓄積手段20は,上
記図2の第1の原理構成と同様に各アドレスにVCIの
番号(またはセル蓄積手段2の番号)のデータが制御部
から書き込まれるが,書き込み位置は任意である(均等
間隔にする必要がない)。このデータを読み出すアドレ
スはランダムカウンタ22から発生する。このため,選
択番号蓄積手段20の書き込みアドレスの位置に関係の
無い順にセル蓄積手段2の読み出しが行われる。
Next, the second principle configuration of the read control means shown in FIG. 3 will be described. In the selection number accumulating means 20 of FIG. 3, the VCI number (or the cell accumulating means 2 number) data is written to each address from the control section as in the first principle configuration of FIG. Optional (no need to be evenly spaced). The address for reading this data is generated from the random counter 22. Therefore, the cell accumulating means 2 is read out in an order not related to the position of the write address of the selection number accumulating means 20.

【0019】[0019]

【実施例】図4は実施例1の構成図,図5は実施例2の
構成図,図6はFIFOの構成例,図7はATM網にお
ける本発明が適用される部分を示す図である。
FIG. 4 is a block diagram of the first embodiment, FIG. 5 is a block diagram of the second embodiment, FIG. 6 is a configuration example of a FIFO, and FIG. 7 is a diagram showing a portion to which the present invention is applied in an ATM network. .

【0020】図4の実施例1の構成では入力通信路が8
Mbps(メガビット・パー・セコンド)の帯域を持つ
ものとし,入力通信路上にVCIが1番(#1で表示)
のセル(申告帯域が4Mbps)と,VCIが4番(#
4)のセル(申告帯域が1Mbps)が現在入力されて
いるものとする。
In the configuration of the first embodiment shown in FIG. 4, the input communication path is 8
It has a bandwidth of Mbps (megabits per second), and the VCI is the first on the input communication path (displayed as # 1).
Cell (report band is 4 Mbps) and VCI is number 4 (#
It is assumed that the cell of 4) (declared band is 1 Mbps) is currently input.

【0021】図4において,40はVCI抽出部,41
はデコーダ,42は各VCI毎に設けられセル蓄積用の
バッファであるFIFO(書き込みと読み出しを同時に
行う2ポートメモリ),43は各FIFOに対応してセ
ル蓄積量のしきい値(セル蓄積量の最大値)が設定され
るしきい値設定部,44はセルを多重化するセレクタ,
45はデコーダ,46はセレクタにおける選択動作を制
御するデータが格納されたRAM(Random Access Memo
ry) ,47は8周期カウンタである。なお,RAMは8
個のアドレスに対応するデータ蓄積容量を持つ。
In FIG. 4, reference numeral 40 denotes a VCI extraction unit, 41
Is a decoder, 42 is a FIFO (two-port memory for writing and reading simultaneously) which is a buffer for cell storage provided for each VCI, and 43 is a threshold of the cell storage amount (cell storage amount corresponding to each FIFO). The maximum value of the threshold), 44 is a selector for multiplexing cells,
Reference numeral 45 is a decoder, and 46 is a RAM (Random Access Memo) in which data for controlling the selection operation of the selector is stored.
ry) and 47 are 8-cycle counters. The RAM is 8
It has a data storage capacity corresponding to each address.

【0022】図4の実施例の動作を説明すると,8Mb
psの入力通信路上に申告帯域4MbpsのVCI#1
のセルと申告帯域1MbpsのVCI#4のセルが統計
多重されて入力通信路に送られくると,しかしこれらの
セルは申告値どうりの帯域で到着するとは限らない。
The operation of the embodiment shown in FIG. 4 will be described. 8 Mb
VCI # 1 with declared bandwidth of 4 Mbps on ps input communication path
, And the cell of VCI # 4 having the declared band of 1 Mbps are statistically multiplexed and sent to the input communication path, but these cells do not always arrive in the band of the declared value.

【0023】VCI抽出部40は入力通信路上のセルの
ヘッダからVCIを抽出してデコーダ41において識別
する。デコーダ41の識別結果に応じて対応する番号の
FIFO42が書込み駆動され,到着したセルが対応す
るFIFO42,即ちFIFO#1とFIFO#4に書
込まれる。
The VCI extraction unit 40 extracts the VCI from the header of the cell on the input communication path and identifies it in the decoder 41. According to the identification result of the decoder 41, the FIFO 42 having a corresponding number is write-driven, and the arriving cell is written in the corresponding FIFO 42, that is, FIFO # 1 and FIFO # 4.

【0024】各VCIに対応するFIFO42に対し,
最大蓄積セル量を設定して蓄積量の制御を行う場合,予
め制御部(図示せず)よりしきい値をしきい値設定部4
3に設定する。この出力は対応するFIFO42に供給
され,各FIFO42はそのしきい値を越えない範囲で
入力するセルの蓄積動作を行う。
For the FIFO 42 corresponding to each VCI,
When controlling the storage amount by setting the maximum storage cell amount, a threshold value is set in advance by the control unit (not shown).
Set to 3. This output is supplied to the corresponding FIFO 42, and each FIFO 42 performs the accumulation operation of the input cell within the range not exceeding the threshold value.

【0025】図6にFIFOの構成例を示す。この動作
を説明すると,FIFOに入力したセルは,書込信号が
供給されるとセルバッファに書込まれ,セル数カウンタ
61がカウントアップ(+1)し,読出し信号が入力し
てセルが1つ読出されると,セル数カウンタ61はカウ
ントダウン(−1)する。従って,このセル数カウンタ
61のカウント数はセルバッファ60に蓄積されている
セル数を表す。
FIG. 6 shows an example of the structure of the FIFO. This operation will be described. The cell input to the FIFO is written in the cell buffer when the write signal is supplied, the cell number counter 61 counts up (+1), and the read signal is input to add one cell. When read, the cell number counter 61 counts down (-1). Therefore, the count number of the cell number counter 61 represents the number of cells accumulated in the cell buffer 60.

【0026】セル数カウンタ61のカウント値は比較回
路62において,しきい値設定部(図4の43)から出
力されたしきい値と比較され,カウンタ値がしきい値を
越えると“0”が発生し,それ以外の場合は“1”が発
生する。このため,セルバッファ60の書込み信号は,
アンド回路63が比較回路62から“1”が供給されて
いる時セルバッファに供給され,“0”の時セルバッフ
ァに供給されず,この時入力したセルは書込まれない
(廃棄される)。
The count value of the cell number counter 61 is compared with the threshold value output from the threshold value setting section (43 in FIG. 4) in the comparison circuit 62, and when the counter value exceeds the threshold value, it is "0". Occurs, otherwise "1" occurs. Therefore, the write signal of the cell buffer 60 is
The AND circuit 63 is supplied to the cell buffer when "1" is supplied from the comparison circuit 62, and is not supplied to the cell buffer when "0", and the input cell is not written (discarded) at this time. .

【0027】このしきい値設定設定部43に設定するし
きい値に応じて入力トラヒック特性に対するセル廃棄等
の通信品質を調整する。例えば,しきい値を高めに設定
すると,瞬時的なバーストに対するセルの廃棄率を少な
くすることができる。
The communication quality such as cell discard for the input traffic characteristics is adjusted according to the threshold value set in the threshold value setting / setting section 43. For example, if the threshold value is set higher, the cell discard rate for an instantaneous burst can be reduced.

【0028】なお,このFIFOのバッファは,図6の
場合1つのVCIに対応して1つ設けられているが,実
際には物理的に1つのバッファを論理的にVCI毎に分
離して複数個のVCIのセルを蓄積させる構成をとるこ
とができる。
In the case of FIG. 6, one FIFO buffer is provided corresponding to one VCI, but in reality, one buffer is physically separated for each VCI and a plurality of buffers are provided. A configuration of accumulating cells of VCI can be adopted.

【0029】図4の説明に戻って,RAM46には制御
部よりVCI#1とVCI#4の申告帯域4Mbpsと
1Mbpsに応じて,図6に示すようにアドレスの間隔
ができるだけ均等になるようにVCI番号が割り付けら
れる(書込む)。すなわち,VCI#1のセルの帯域は
4Mbpsなので,通信路の帯域8Mbpsに対し1/
2であり,RAM46の全アドレス8個の内の4個(A
DDR1,3,5,7)を使用し,更にその割り付け方
は1アドレスおきとする。同様にVCI#4のセルの帯
域は1Mbpsなので通信路の帯域8Mbpsの1/
8,つまり1アドレス(ADDR2)を割り付ける。
Returning to the explanation of FIG. 4, in the RAM 46, according to the declared bandwidths 4 Mbps and 1 Mbps of VCI # 1 and VCI # 4 from the control unit, as shown in FIG. A VCI number is assigned (written). That is, since the band of the cell of VCI # 1 is 4 Mbps, 1/1 / the band of the communication path is 8 Mbps.
2 and 4 out of 8 total addresses in RAM 46 (A
DDR1, 3, 5, 7) are used, and the allocation method is every other address. Similarly, since the cell band of VCI # 4 is 1 Mbps, 1 / of the communication channel band of 8 Mbps is used.
8, that is, 1 address (ADDR2) is allocated.

【0030】このRAM46は,8周期カウンタ47か
ら出力されるカウンタ値をアドレスとして順次読出さ
れ,RAM46から読み出されるVCI番号はデコーダ
45で識別され,番号に対応するFIFO42に対し読
出し信号が出力される一方,セレクタ44にも読み出さ
れたVCI番号が供給される。セレクタ44は読出しを
行ったFIFO42を選択して読み出されたセルを出力
通信路に送出する。
The RAM 46 is sequentially read by using the counter value output from the 8-cycle counter 47 as an address, the VCI number read from the RAM 46 is identified by the decoder 45, and a read signal is output to the FIFO 42 corresponding to the number. On the other hand, the read VCI number is also supplied to the selector 44. The selector 44 selects the read FIFO 42 and sends the read cell to the output communication path.

【0031】このようにして到着したセルがバースト的
なトラヒック特性を持っていて瞬間的にセルの到着数が
多くなってもFIFOから読み出した後は申告された帯
域を守ることができ,更にトラヒック特性を平滑化され
る。
Even if the number of cells arriving in this manner has a burst-like traffic characteristic and the number of cells arriving momentarily increases, the declared band can be protected after being read from the FIFO, and the traffic can be further protected. The characteristics are smoothed.

【0032】図5に示す実施例2の構成を説明すると,
図5の50〜56はそれぞれ図4の40〜46と同様の
回路または装置であり説明を省略する。57は8周期疑
似乱数発生カウンタである。
Explaining the configuration of the second embodiment shown in FIG. 5,
Reference numerals 50 to 56 in FIG. 5 are circuits or devices similar to those in 40 to 46 in FIG. Reference numeral 57 is an 8-period pseudo random number generation counter.

【0033】実施例2の場合,RAM56に制御部から
の指示により通信路の帯域中の各VCIが申告された帯
域の割合でRAM56のアドレスを割り付ける。この
時,上記実施例1の場合と違い,各VCIの割り付け方
はRAM56の空きアドレスに自由に設定できる。
In the case of the second embodiment, the addresses of the RAM 56 are assigned to the RAM 56 in accordance with the instruction from the control unit at the rate of the band in which each VCI in the band of the communication path is declared. At this time, unlike the case of the first embodiment, the allocation method of each VCI can be freely set to an empty address of the RAM 56.

【0034】このRAM56は,8周期疑似乱数発生カ
ウンタ57の出力をアドレスとして読出され,出力され
たVCI番号のFIFO52からセルを取り出し出力通
信路へ送出する。これによって,到着したセルがバース
ト的なトラヒック特性を持っていても,FIFO52か
ら読出した後は申告された帯域を守ることができ,更に
トラヒック特性も平滑化される。
This RAM 56 is read by using the output of the 8-period pseudo random number generation counter 57 as an address, takes out a cell from the FIFO 52 of the VCI number outputted, and sends it to the output communication path. As a result, even if the arriving cell has a bursty traffic characteristic, the declared band can be protected after being read from the FIFO 52, and the traffic characteristic can be smoothed.

【0035】次に,ATM網における本発明が適用され
る部分を図7を用いて説明する。図7のA.は中央交換
機の配置図であり,複数の遠隔集線部からの入力通信路
が交換機に入力する位置に本発明の帯域制御方式による
機構(例えば,ポリシング機構)を設けることができ
る。また,図7のB.の場合は,各遠隔集線部において
各加入者線が入力される部分に本発明の帯域制御方式に
より機構を設けた場合である。同様に,他の複数のVC
Iのセルを伝送する部分に適用できる。
Next, the part of the ATM network to which the present invention is applied will be described with reference to FIG. A. of FIG. Is a layout diagram of the central exchange, and a mechanism (for example, a polishing mechanism) according to the bandwidth control method of the present invention can be provided at a position where input communication paths from a plurality of remote concentrators input to the exchange. In addition, in FIG. In the above case, a mechanism is provided by the bandwidth control system of the present invention at the portion where each subscriber line is input in each remote concentrator. Similarly, other VCs
It can be applied to the part for transmitting I cells.

【0036】[0036]

【発明の効果】本発明によれば瞬時的にトラヒックが増
大したセルが発生してもセル蓄積手段から出力された後
のトラヒック特性は申告帯域内で平滑化(Traffic shap
ing)されるため,瞬時的にトラヒックが増大した場合に
も制御することができ,セル廃棄等のサービス品質を向
上することができる。
According to the present invention, even if a cell in which traffic is instantaneously increased occurs, the traffic characteristic after being output from the cell accumulating means is smoothed within the declared band (Traffic shap).
Therefore, it is possible to control even when the traffic increases instantaneously, and it is possible to improve the service quality such as cell discard.

【0037】また,トラヒック特性が平滑化される結果
として網を設定する場合にバッファ量を少なくすること
ができ経済的である。更に,VCI毎に設けられたセル
蓄積手段のキュー長を自由に設定できる最大セル蓄積量
設定手段を付加することにより,入力トラヒック特性に
バーストが発生してもセル蓄積手段からのセルの廃棄量
を調整することができる。
Further, as a result of smoothing traffic characteristics, the buffer amount can be reduced when setting a network, which is economical. Further, by adding a maximum cell storage amount setting means which can freely set the queue length of the cell storage means provided for each VCI, even if a burst occurs in the input traffic characteristic, the amount of cells discarded from the cell storage means. Can be adjusted.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の原理構成図である。FIG. 1 is a principle configuration diagram of the present invention.

【図2】読出し制御手段の第1の原理構成図である。FIG. 2 is a first principle configuration diagram of a read control unit.

【図3】読出し制御手段の第2の原理構成図である。FIG. 3 is a second principle configuration diagram of the read control means.

【図4】実施例1の構成図である。FIG. 4 is a configuration diagram of a first embodiment.

【図5】実施例2の構成図である。FIG. 5 is a configuration diagram of a second embodiment.

【図6】FIFOの構成例である。FIG. 6 is a structural example of a FIFO.

【図7】ATM網における本発明が適用される部分を示
す図である。
FIG. 7 is a diagram showing a portion to which the present invention is applied in an ATM network.

【図8】従来例1の構成図である。FIG. 8 is a configuration diagram of Conventional Example 1.

【図9】従来例2の構成図である。FIG. 9 is a configuration diagram of Conventional Example 2.

【符号の説明】[Explanation of symbols]

1 セル分離手段 2 セル蓄積手段 3 最大セル蓄積量設定手段 4 セル多重手段 5 読出し制御手段 1 cell separation means 2 cell storage means 3 Maximum cell storage amount setting means 4 cell multiplexing means 5 Read control means

───────────────────────────────────────────────────── フロントページの続き (72)発明者 武智 竜一 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 川崎 健 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Ryuichi Takechi             1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture             Within Fujitsu Limited (72) Inventor Ken Kawasaki             1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture             Within Fujitsu Limited

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 ATM網の通信路上を伝送されるセルの
帯域制御方式において, 複数の異なる呼識別用のVCI(仮想チャネル番号)を
持つセルが統計多重された通信路からVCI毎にセルを
振り分けるセル分離手段と, VCI毎にセルを蓄積するセル蓄積手段と, セル蓄積手段からのセルの読出しを制御する読出し制御
手段と, 読出し制御手段からの制御によりセル蓄積手段から読出
されたセルを多重するセル多重手段を備え, 読出し制御手段は,各VCI対応のセル蓄積手段からの
読出しを,セルを送出する通信路の帯域中の各VCIに
対して予め申告した帯域の比率により読出すことを特徴
とするATM網における帯域制御方式。
1. A band control method for a cell transmitted on a communication path of an ATM network, wherein a cell having a plurality of different VCIs (virtual channel numbers) for call identification is statistically multiplexed from a communication path to a cell for each VCI. Cell separating means for allocating, cell accumulating means for accumulating cells for each VCI, read control means for controlling reading of cells from the cell accumulating means, and cells read from the cell accumulating means under control of the read controlling means. The read control means is provided with a cell multiplexing means for multiplexing, and the read control means reads the read from the cell storage means corresponding to each VCI in accordance with the ratio of the band previously declared for each VCI in the band of the communication path transmitting the cell. A bandwidth control method in an ATM network.
【請求項2】 請求項1において, 前記VCI毎の各セル蓄積手段に,蓄積可能なキュー長
を設定する最大蓄積量設定手段を設け,該最大蓄積量設
定手段の設定値により入力トラヒック特性にバーストが
発生した時のセル蓄積手段におけるセル廃棄量を調整す
ることを特徴とするATM網における帯域制御方式。
2. The cell storage means for each VCI according to claim 1, wherein a maximum storage amount setting means for setting a queue length that can be stored is provided, and an input traffic characteristic is set according to a set value of the maximum storage amount setting means. A band control system in an ATM network, characterized in that the amount of cell discard in a cell storage means when a burst occurs is adjusted.
【請求項3】 請求項1において, 前記セル蓄積手段からのセルの読出しを制御する読出し
制御手段は, 読出しを行うセル蓄積手段の選択番号を蓄積する選択番
号蓄積手段と,選択番号蓄積手段のアドレスを順次指定
する周期カウンタにより構成し, 選択番号蓄積手段は,セルを送出する通信路の帯域中の
各VCIが予め申告した帯域の割合で,且つアドレス間
隔が均等になるように割り付けることを特徴とするAT
M網における帯域制御方式。
3. The read control means for controlling the reading of a cell from the cell storage means according to claim 1, comprising a selection number storage means for storing a selection number of the cell storage means to be read, and a selection number storage means. The selection number accumulating means is configured by a cycle counter that sequentially specifies addresses, and the selection number accumulating means allocates each VCI in the band of the communication path for transmitting cells so that the VCI has a pre-declared band ratio and the address intervals are even. Characteristic AT
Bandwidth control method in M network.
【請求項4】 請求項1において, 前記セル蓄積手段からのセルの読出しを制御する読出し
制御手段は, 読出しを行うセル蓄積手段の選択番号を蓄積する選択番
号蓄積手段と,選択番号蓄積手段のアドレスをランダム
に指定するカウンタにより構成し, 選択番号蓄積手段は,セルを伝送する通信路の帯域中の
各VCIが予め申告した帯域の割合で割りつけ,選択番
号蓄積手段からの読出しをランダムに行うことを特徴と
するATM網における帯域制御方式。
4. The read control means for controlling reading of a cell from the cell storage means according to claim 1, comprising a selection number storage means for storing a selection number of the cell storage means for reading and a selection number storage means. The selection number accumulating means is configured by a counter that randomly designates addresses, and the selection number accumulating means allocates at a rate of the band previously declared by each VCI in the band of the communication path for transmitting cells, and reads from the selection number accumulating means at random. A bandwidth control method in an ATM network characterized by performing.
JP15933491A 1991-07-01 1991-07-01 Bandwidth control device and bandwidth control method in ATM network Expired - Fee Related JP2862709B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15933491A JP2862709B2 (en) 1991-07-01 1991-07-01 Bandwidth control device and bandwidth control method in ATM network

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Application Number Priority Date Filing Date Title
JP15933491A JP2862709B2 (en) 1991-07-01 1991-07-01 Bandwidth control device and bandwidth control method in ATM network

Publications (2)

Publication Number Publication Date
JPH0514388A true JPH0514388A (en) 1993-01-22
JP2862709B2 JP2862709B2 (en) 1999-03-03

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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08274794A (en) * 1995-03-27 1996-10-18 Koninkl Ptt Nederland Nv Signal acceptance permission device in atm guard device
US6965566B2 (en) 2000-02-16 2005-11-15 Fujitsu Limited Packet flow control apparatus and a method for controlling the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08274794A (en) * 1995-03-27 1996-10-18 Koninkl Ptt Nederland Nv Signal acceptance permission device in atm guard device
US6965566B2 (en) 2000-02-16 2005-11-15 Fujitsu Limited Packet flow control apparatus and a method for controlling the same

Also Published As

Publication number Publication date
JP2862709B2 (en) 1999-03-03

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