JPH0514374A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To shorten the communication time in the whole of a system consisting of a center and terminals. CONSTITUTION:A center 100 selectively generates a frame synchronizing pattern for down frame and that for up frame by a switching signal S1 and transmits them to a terminal 200. In the terminal 200, the up frame synchronizing pattern in down data S8 and S9 is detected in a frame synchronizing pattern detecting part 240 for up frame by a synchronizing clock S11. A prescribed time slot S16 of the up frame of the terminal 200 is set to an up time slot designating part 270, and an up data output part 280 transmits up data S20 to the center 100 by a prescribed time slot of the terminal 200 in accordance with an output permission signal S17 corresponding to the time slot S16, an up data load signal S18, and an up shift clock signal S19.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission device for transmitting various data between a center and a terminal.

[0002]

2. Description of the Related Art Conventionally, in a data transmission device for transmitting various data between a center and a terminal, the amount of upstream data transmitted from the terminal to the center is extremely small compared to the amount of downstream data transmitted from the center to the terminal. In the case of a center-to-end system, a polling method is adopted in which transmission of upstream data is sequentially and periodically invited from the center to each terminal. In this case, the polled terminal starts data transmission when preparation for data transmission is completed. In this specification, the direction from the terminal to the center is referred to as “upward”, and the direction from the center to each terminal is referred to as “downward”.

[0003]

However, in the above-mentioned conventional polling-type data transmission apparatus, since the center periodically invites the transmission of uplink data to each terminal, the system is used when the number of terminals is large. There is a problem that the communication time as a whole becomes long.

Therefore, an object of the present invention is to provide a data transmission device which can shorten the communication time of the entire system.

[0005]

According to the present invention, in order to achieve the above object, a center sends an uplink frame synchronization pattern to a terminal, and the terminal generates an uplink frame according to the uplink frame synchronization pattern, Uplink data is transmitted in a predetermined time slot. That is, according to the present invention, an uplink frame is generated by a center transmitting an uplink frame synchronization pattern and an uplink frame synchronization pattern from the center, and the uplink data is transmitted in a predetermined time slot of each terminal of the uplink frame. There is provided a data transmission device having a terminal that operates. Here, "upstream frame" refers to one cycle of a frame signal (referred to as an upstream frame signal) for transmitting upstream data. Further, in the following description, "downstream frame" means one cycle of a frame signal (downstream frame signal) for transmitting downlink data.

[0006]

Since the present invention has the above-mentioned configuration, there is no need for polling for soliciting transmission of upstream data from the center device to each terminal periodically, and therefore the communication time of the entire system can be shortened. it can.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. 1A is a block diagram showing a center of an embodiment of a data transmission apparatus according to the present invention, and FIG. 1B is a block diagram showing a terminal of an embodiment of a data transmission apparatus according to the present invention. 2 (a) to 2 (i) are timing charts showing main signals in the center of FIG. 1 (a), and FIGS.
(I) is a timing chart showing main signals in the terminal of FIG. 1 (b).

In the center 100 shown in FIG. 1 (a),
The control circuit 110 outputs the switching signal S1 of the frame synchronization pattern for the downstream frame and the frame synchronization pattern for the upstream frame to the frame synchronization pattern generator 120,
Also, the frame synchronization pattern and the selection signal S5 of the transmission data 130 are output to the selection circuit 140, and further, the load signal S6 for the downlink frame and the shift clock signal S7 are output to the parallel / serial conversion output circuit 150. The downlink frame is a frame from the center 100 to the terminal 200 shown in FIG. 1B, and the uplink frame is a frame from the terminal 200 to the center 100. The control circuit 110 also processes the upstream data S20 (described later) input from the terminal 200 via the upstream data input unit 160.

The frame synchronization pattern generator 120 selectively generates a frame synchronization pattern for a downstream frame and a frame synchronization pattern for an upstream frame by parallel signals in response to the switching signal S1.
5, the transmission data 130 or the frame synchronization pattern is selected. The parallel / serial conversion output circuit 150
The transmission data 130 and the frame synchronization pattern selected by the selection circuit 140 are converted into a serial signal and the downlink data S8 and S9 are sent to the line.

In the terminal 200 shown in FIG. 1 (b), the clock synchronization unit 220 uses the downlink data S8 from the center 100,
The synchronous clock S11 is reproduced by S9. Further, the frame synchronization pattern detection unit 230 for the downlink frame outputs the detection signal S12 of the downlink frame synchronization pattern in the downlink data S8 and S9 by the synchronization clock S11, and the frame synchronization unit 260 outputs the downlink frame synchronization pattern. The downstream frame synchronization signal S13 is generated by the detection signal S12 of FIG. 2 and the synchronization clock S11 and output to the control circuit 210.

Further, the frame synchronization pattern detection unit 240 for the upstream frame outputs the detection signal S14 of the upstream frame synchronization pattern in the downstream data S8 and S9 to the synchronization clock S.
11 and outputs to the control circuit 210. A predetermined time slot S16 of the upstream frame of this terminal 200 is set in the upstream time slot designating unit 270, and the control circuit 210 detects the downstream frame synchronization signal S13 and the upstream frame synchronization pattern in this predetermined time slot S16. An output permission signal S17 based on the signal S14,
The upstream data load signal S18 and the upstream shift clock signal S19 are output. The upstream data output unit 280 uses the output permission signal S17, the upstream data load signal S18, and the upstream shift clock signal S19 to send the upstream data S20 to the center 10 in a predetermined time slot of the terminal 200.
Send to 0.

Next, the operation of the above embodiment will be described with reference to FIGS. As shown in FIGS. 2A to 2D, when the control circuit 110 of the center 100 outputs the frame synchronization pattern switching signal S1 on a frame-by-frame basis, the frame synchronization pattern generator 120 outputs 1 by the frame synchronization pattern switching signal S1. A frame synchronization pattern A for a downstream frame and a frame synchronization pattern B for an upstream frame are selectively generated in frame units.

As shown in FIG. 2 (e), when the control circuit 110 outputs the selection signal S5 synchronized with the downlink frame signal, the selection circuit 140 uses the selection signal S5 to transmit the transmission data 130 (D) or The first and second frame synchronization patterns A and B (C in the figure) are alternately selected. Next, when the control circuit 110 outputs the load signal S6 and the shift clock signal S7 as shown in FIGS. 2F and 2G, the parallel / serial conversion output circuit 150 outputs
Serial data S8 as shown in FIGS. 2 (h) and 2 (i),
Output S9 to the transmission line.

In the terminal 200, the downlink data synchronization signal is detected by the clock synchronization section 220, and the downlink frame synchronization pattern A is detected by the frame synchronization pattern detection section 230.
The frame sync pattern B for upstream is detected by the frame sync pattern detector 240, and the data itself is converted into parallel data by the serial / parallel converter 250.

That is, the clock synchronization section 220 is shown in FIG.
As shown in (a), the clock signal S11 synchronized with the downlink data is reproduced to download the downlink frame synchronization pattern detector 2
30, an upstream frame synchronization pattern detection unit 240,
Serial / parallel conversion unit 250 and frame synchronization unit 26
Output to 0. Downlink frame synchronization pattern detector 23
0 is the clock signal S11 as shown in FIG.
Detection signal S of downlink frame synchronization pattern A synchronized with
12 is output to the frame synchronization unit 260, the frame synchronization unit 260 establishes frame synchronization by the clock signal S11 and the detection signal S12, and the downlink frame synchronization signal S13 as shown in FIG. Output. In addition, the upstream frame synchronization pattern detection unit 240
Outputs the detection signal S14 of the upstream frame synchronization pattern B synchronized with the clock signal S11 to the control circuit 210 as shown in FIG.

The control circuit 210 controls the downstream frame synchronization signal S13 and the upstream frame synchronization pattern B detection signal S1.
4, the upstream frame signal S as shown in FIG.
15 is generated, and the output permission signal S17 and the upstream data load signal S18 as shown in FIGS. 3 (f) to 3 (h) are generated in the predetermined time slot of this terminal 200 designated by the upstream time slot designation unit 270. , And outputs the upstream shift clock signal S19 to the upstream data output unit 280.

The upstream data output unit 280 outputs the upstream data S20 as shown in FIG. 3 (i) to the center 100 in response to the output permission signal S17, the upstream data load signal S18, and the upstream shift clock signal S19. Therefore, the center 100 receives the data via the upstream data input section 160 shown in FIG.

Therefore, according to the above embodiment, the center 100 transmits the frame synchronization pattern A for the downstream frame and the frame synchronization pattern B for the upstream frame in the unit of one frame to the terminal 200, and the terminal 200 transmits the downlink frame. Since the downstream frame synchronization signal S13 is generated by the frame synchronization pattern A, and the upstream frame signal S15 is generated by this downstream frame synchronization signal S13 and the upstream frame synchronization pattern B, the upstream frame signal S15 is transmitted in a predetermined time slot. It becomes unnecessary for the terminal 200 to periodically invite the terminal 200 to transmit the upstream data. Therefore, the communication time of the entire system can be shortened.

According to this embodiment, for example, when the number of terminals 200 is large within a few kilometers from the center 100, data can be efficiently transmitted in a particularly short time, and the circuit configuration is also improved. Easy and cheap. Further, in the above embodiment, the center 100 transmits the frame synchronization pattern B for one upstream frame to the terminal 200 within one frame. However, the frame synchronization pattern B for a plurality of upstream frames is transmitted. Terminal 20
0 may transmit the uplink data by one or more of the plurality of second frame synchronization patterns B.

[0020]

As is apparent from the above detailed description, according to the present invention, there is no need for polling for soliciting uplink data from the center device for each terminal periodically. Therefore, the communication time of the entire system can be shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a data transmission device according to the present invention.

FIG. 2 is a timing chart showing main signals in the center of FIG.

3 is a timing chart showing main signals in the terminal of FIG.

[Explanation of symbols]

 100 center 110, 210 control circuit 120 frame synchronization pattern generation unit 200 terminal 200 clock synchronization unit 230, 240 frame synchronization pattern detection unit 260 frame synchronization unit 270 upstream time slot unit 280 upstream data output unit

Claims (1)

Claim: What is claimed is: 1. A center that transmits a synchronization pattern for creating an upstream frame signal together with downlink data to each terminal, and an upstream frame signal according to the synchronization pattern for the upstream frame given from the center. A data transmission device having a terminal that generates and transmits uplink data in a predetermined time slot for each terminal in an uplink frame that is one cycle of the uplink frame signal.