JPH05143454A - Cache control system - Google Patents

Abstract

PURPOSE:To effectively utilize a cache memory even when accessing any specified area on a shared memory for the exclusive control of shared resources in a data processor provided with a cache memory. CONSTITUTION:When a processor 1a reads a specified area 4a on a shared memory 4 for the exclusive control of shared resources 4b by a specified operation, it is discriminated whether the copy of the specified area 4a is held in a cache memory 1b or not and when it is held, the copy of the specified area 4a is read from the cache memory 1b. When the copy of the specified area 4a is not held in the cache memory 1b, the specified area 4a on the shared memory 4 is read and updated at the same time, and data before the update are returned to the side of a data processor 3 as read data. These read data are inputted to the cache memory 1b and held.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache control method for a data processing system in which a plurality of data processing devices access a common resource, and more particularly to a cache for a specific area on a memory for exclusive control of the common resource. Control method for capturing.

[0002]

2. Description of the Related Art Exclusive control of a shared resource when a plurality of data processing devices access a shared resource is generally tested by a single memory access to a specific area on a memory accessed by the plurality of data processing devices. And it is realized by a specific operation that updates.

The specific area is usually called a "semaphore area". In addition, this operation is only available when the specified 1-bit read and set on the semaphore area is performed by a single memory access, or when the value of the semaphore area is a specific value. There is a method called "compare and swap" in which the operation of replacing with another value is performed by one memory access. In particular, the specific bit in "test and set" is called a semaphore bit.

The semaphore bit read by a device is 0
If so, it means that the corresponding shared resource is not occupied by another device, and the own device can obtain the access right. At the same time, the device that has acquired the access right writes 1 to the semaphore bit, so that another device cannot acquire the access right to the shared resource. When the access to the shared resource by the device itself ends, the device clears the semaphore bit. In the semaphore bit read in the subsequent “test and set” operation, 0 is read, so that the other device can obtain the access right to the shared resource.

In the above-mentioned "test and set", since the semaphore bit is read and written by one memory access, one device reads the semaphore bit and then the other device sets it. Does not read the semaphore bit, and multiple devices do not simultaneously gain access to the shared resource.
Even in the "compare and swap", the above operation is performed by one memory access, so that the exclusive control similar to the "test and set" can be realized.

By the way, conventionally, even when the data processing device is provided with a cache memory, the cache memory is used when performing the above-mentioned "test and set" or "compare and swap". Instead, it was realized by directly accessing the shared memory. This is because the "test and set" and "compare and swap" described above read and update the semaphore area with a single operation.
If a device writes the read semaphore bit 0 to the cache during “test and set”, this semaphore bit 0 is the one before update, and the device reads 0 and at the same time the semaphore bit of the main memory device is read. This is because writing 1 to the bit causes a problem that the contents of the semaphore bits of the cache and the main memory do not match.

Further, since the cache is usually constructed in units of blocks of a plurality of words, reading in units of blocks is effective in normal memory access. However, in reading and writing semaphore bits, it is in units of 1 bit. There is a drawback in that reading and writing of data, and reading in block units including extra data is rather slow and leads to deterioration in performance.

However, when a plurality of devices frequently access the shared resource as described above, the "test and set" operation is also frequently performed. And while one device gains access to the shared resource,
If another device wants to gain access to the shared resource, it will repeat the "test and set" operation until one device clears the semaphore bit. This "test and set" operation directly accesses the memory without using the cache, which significantly increases the memory usage rate and increases the probability of waiting for the memory access of another device due to the memory busy. However, there is a drawback that the efficiency of the entire system is reduced.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned drawbacks of the prior art. In a data processing device having a cache memory, the "test
Certain operations such as "and set"
An object of the present invention is to improve the efficiency of the system by enabling effective use of the cache memory even when accessing a specific area on the shared memory for exclusive control of the shared resource.

[0010]

In order to solve the above problems, the first aspect of the present invention is, as shown in FIG. 1, a data processing device 1 having a cache memory 1b, and a plurality of data processing devices 1. , 3 have a shared resource 4b accessed by the shared memory 4 and a specific area 4a provided on the shared memory 4 is tested and updated by a single memory access to perform exclusive control of the shared resource 4b. In the cache control method in the realized data processing devices 1 and 3, by the above specific operation,
When the specific area 4a on the shared memory 4 is read, the cache memory 1b holding a copy of the specific area 4a is accessed and the specific area 4a is stored in the cache memory 1b.
When there is no copy of the specified area 4a, the specified area 4a on the shared memory 4 is read and sent to the processor 1a in the data processing device 1 and also written to the cache memory 1b, and the specified area 4a is copied to the cache memory 1b. Exists, the cache memory 1b is accessed only and the shared memory 4 is not accessed. If another data processing device 3 writes to the specific area 4a of the shared memory 4, the cache memory 1b is accessed. Cache control means 1c for invalidating According to a second aspect of the present invention, when the specific area 4a on the shared memory 4 is read by the specific operation according to the first aspect, the specific area 4a is read.
When the cache memory 1b holding a copy of the specified area is accessed and there is no copy of the specified area 4a in the cache memory 1b, the specified area 4a on the shared memory 4 is accessed.
Is sent to the processor 1a of the data processing device 1, and the specific value is cached only when the specific area 4a is a specific value indicating that the shared resource 4b is being accessed by another data processing device 3. The cache control means 1c has a function of writing to the memory 1b. A third aspect of the present invention is the cache memory 1 according to the first aspect, which holds a copy of the specific area 4a when the specific area 4a on the shared memory 4 is read by the specific operation.
b is accessed, and when there is no copy of the specific area 4a in the cache memory 1b, the specific area 4a in the shared memory 4 is read and sent to the processor 1a of the data processing device 1 and also to the cache memory 1b. The cache control means 1c is provided with a function of writing a value replaced with a specific value indicating that the shared resource 4b is being accessed by another data processing device 3. According to claim 4, claim 1 or claim 2 or claim 3 is configured such that the cache memory 1b is also used as a cache memory in a normal memory access, and claim 5 claims 4 is provided with a means for discriminating between a cache hit determination in a specific operation and a cache hit determination in a normal memory access. According to claim 6, in claim 4 or 5, data is written to the cache memory 1b at the time of a cache miss in a specific operation and data is written to the cache memory 1b at the time of a cache miss in a normal memory access. It is provided with a means for separating writing from.

[0011]

The processor 1a performs a specific operation,
When reading the specific area 4a of the shared memory 4, it is determined whether or not a copy of the specific area 4a is held in the cache memory 1b, and if it is held, a copy of the specific area 4a is made from the cache memory 1b. To lead. If the cache memory 1b does not hold a copy of the specific area 4a, the specific area 4a on the shared memory 4 is read and updated at the same time, and the data before the update is used as read data on the data processing device side. Change back. This read data is input and held in the cache memory 1b. Since the specific area 4a on the shared memory 4 is read and updated at the same time, the copies of the specific area 4a of the shared memory 4 and the specific area 4a of the cache memory 1b are different, but the normal specific area 4a is accessed again. When the acquisition of the exclusive right of the shared resource 4b fails, in this case, the specific area 4a of the shared memory 4 is
Since there is a match between the copy of the specific area 4a held in the cache 12 and the copy, there is no problem. It is to be noted that, when reading and updating the specific area 4a on the shared memory 4 at the same time as in claim 2, it is shown that the specific area 4a is accessing the shared resource 4b by another data processing device 3. By writing to the cache memory 1b only when it is the specific value, it is possible to maintain the consistency between the copy of the specific area 4a of the shared memory 4 and the copy of the specific area 4a held in the cache memory 1b. In the above case,
As described in claim 3, by writing to the cache memory 1b a value replaced with a specific value indicating that the shared resource 4b is being accessed by another data processing device 3,
The data in the shared memory 4 is always registered in the cache, and high-speed access is possible even when reading again.

[0012]

FIG. 2 is a diagram showing the overall construction of the present invention. In the figure, 11-1, 11-2 are data processing devices, 1
2 is a common bus, 13 is a memory control circuit, 14 is a shared memory, 20 is a processor, 21 is a cache control circuit, 2
2 is a cache memory, 23 is a memory interface,
24-1 is an address bus, 24-2 is an access information bus, 25 is a data bus, 26 is a cache control signal, 2
7 is a cache invalidation address bus, 28-1 is a memory data bus, 31 is a semaphore control circuit, 41 is a semaphore area, and 42 is a shared resource to be exclusively controlled.

In the figure, a plurality of data processing devices 11
-1, 11-2 are connected to the shared memory 14 via the common bus 12 and the memory control circuit 13. Shared memory 14
A shared resource 42 accessed by the plurality of data processing devices 11-1 and 11-2 and a semaphore area 41 for exclusive control of the shared resource 42 are provided above the shared resource 42. Although the shared resource 42 is provided on the shared memory 14 in this embodiment, the shared resource may be another resource such as I / O.

The memory control circuit 13 is a data processing device 11.
-1, 11-2 are means for controlling memory access, and the memory control circuit 13 is provided with a semaphore control circuit 31 for performing exclusive control on shared resources. For test and set access. Data processing device 1
A cache control circuit 21 and a cache memory 22 for holding block data or semaphore bytes on the shared memory 14 are provided in the 1-1 and 11-2. When accessing the shared memory 14, the processor 20 reads data from the cache memory 22 if the data of the address to be accessed is held in the cache memory 22.

The memory interface 23 is means for interfacing between the data processors 11-1 and 11-2 and the common bus, and the address bus 24-1 sends out an address signal when the processor 20 makes a memory access. The bus and access information bus 24-2 is a normal memory
The data bus 25 is a bus for outputting information indicating the type of access or test set access, and the data bus 25 is a bus for outputting data.

A cache control signal 26 is a signal for controlling the cache memory 22, a cache invalidation address bus 27 is a bus for transmitting an address when another data processing device accesses the memory, and a memory data bus 28.
-1 is a bus to which the read data from the shared memory 14 is transmitted.

FIG. 5 is a diagram showing the format of the semaphore area on the shared memory 14, in which the semaphore bit is assigned to the first bit of the semaphore area. FIG. 3 is a diagram showing a specific configuration of the cache control circuit 21 and the cache memory 22 in FIG. In the figure, 1
01 is an address save register, 102 is a tag, 103
Is a memory address register, 104 is a comparator, 105 is a valid flag register, 106 is a tag mode flag register, 107 is a comparator, 108 is a cache memory control signal generation circuit, 109 is a data selection circuit, 110 is an OR circuit, and 111 is A control switching circuit, 112 is a selection information generating circuit, and 113 to 116 are buffer memories.

Address save register 1 in FIG.
01 is a register for holding a memory address sent from the address bus 24-1, tag 102 is a register for holding an address corresponding to data registered in the cache memory, and memory address register 103 is a memory. This is a register for holding the cache invalidation address input from the interface 23. The address save register 101, the tag 102, and the memory address register 103 are each composed of 32 bits.

The comparator 104 is the address save register 1
01 is a comparator for comparing the contents of the tag 102, and when the output of the control switching circuit 111 is a logic indicating a normal memory access mode, the upper 28 of the 32 bits of the register 101 and the 32 bits of the tag 102 are used. Compare bits, and when in test and set mode, compare all 32 bits.

The valid flag register 105 is a register for holding a valid flag V indicating that the address registered in the tag is valid, and becomes "1" when valid. The tag mode flag register 106 is a register that holds a tag mode flag M indicating that the data held in the cache memory is a semaphore byte, and becomes "1" when the semaphore byte is held. The comparator 107 is a comparator that compares the contents of the memory address register 103 and the tag 102.

Cache memory control signal generation circuit 108
Is a circuit for generating a signal for controlling the cache memory 22, a data selection circuit 109 is a circuit for selecting and outputting necessary data out of the data from the buffer memories 113 to 116 or the memory interface 23, and the control switching circuit. A circuit 111 outputs a mode switching signal 1111 by discriminating between a memory access and a test and set access. The mode switching signal 1111 is a logic 0 during a normal memory access.
And becomes a logic 1 at the time of test and set access. The selection information generation circuit 112 is the buffer memory 1
The circuits for generating selection information signals to the data selection circuit 109 for selecting information from 13 to 116, and the buffer memories 113 to 116 are circuits for holding data.
Composed of bytes.

Next, the operation of the embodiment will be described with reference to FIGS. At the time of normal memory access, the processor 20 sends an address to the address bus 24-1 and
The access information indicating the memory access is output to the access information bus 24-2. The address and access information are input to the cache control circuit 21, the address is input to the address save register 101 of FIG.
Further, the access information is input to and set in the control switching circuit 111 of FIG.

The control switching circuit 111 decodes the access information to determine whether it is a normal memory access or a test and set access, and a mode switching signal 1111.
Is sent. As described above, the mode switching signal 1111 becomes logical 0 in the normal memory access and becomes logical 1 in the test and set access. In this case, since it is a normal memory access, a logical 0 is input to the comparator 104, and the comparator 104, as described above,
The upper 28 bits of the address save register 101 and the upper 28 bits of the tag 102 are compared to determine whether or not the cache is hit, that is, whether or not desired data exists in the cache memory 22.

In this embodiment, the buffer memory 1
Since 13 to 116 are composed of 16 bytes, and 16 bytes of block data are read into the cache memory 22 at one time in a normal memory read, by comparing the upper 28 bits of the address as described above, the cache You can determine whether or not you hit.

In the above comparison, if the comparison results match, it is found that the desired data exists in the cache memory 22, and the match signal EQ1 indicates the selection information generating circuit 112.
Sent to. At the same time, the lower 4 bits of the address save register 101 are set to the selection information generation circuit 112.
Entered in. The selection information generation circuit 112 generates selection information from the lower 4 bits and gives it to the selector 109 in the cache memory 22. The selector 109 selects a necessary word (16 bits) or byte (8 bits) of the buffer memories 113 to 116 in the cache memory 22 based on the lower 4 bits and sends it to the processor 20. The value of the address save register 101 is set in the tag 102, the tag mode flag M of the tag mode flag register 106 is set to 0, and the data held in the cache memory 22 is block data.

On the other hand, if the comparison result is a mismatch, that is, a mishit, the address on the address bus 24-1 is output to the common bus 12 via the memory interface 23 and the shared memory 14 via the memory control circuit 13. Is accessed. The data read from the shared memory 14 is input to the cache memory 22 via the memory control circuit 13, the common bus 12, the memory interface 23, and the memory data bus 28-1.

When the desired data does not exist in the cache memory 22, that is, in the case of a cache mishit, the shared memory 14 is accessed in block units, in this embodiment, in 16-byte units. Is 4 bytes, read data is input to the cache memory 22 four times in a row and written to the buffer memories 113 to 116. Further, of the block data read from the shared memory 14, desired data is selected by the selector 109 and sent to the processor 20.

In the case of the test and set instruction, the processor 20 sends out the address to the address bus 24-1 and outputs the access information indicating the test and set access to the access information bus 24-2. To do. The address and access information are input to the cache control circuit 21, the address is set in the address save register 101 of FIG. 3, and the access information is set in the control switching circuit 111 of FIG.

The control switching circuit 111 decodes the access information and determines whether it is a normal memory access or a test and set access, and a mode switching signal 1111.
Is sent. In this case, since it is the test and set access, the logic 1 is input to the comparator 104 and the comparator 1
The comparison target bit of 04 is changed from 28 bits to 32 bits. That is, 3 of the address save register 101
Two bits are compared with all 32 bits of the tag 102 to determine whether or not the cache is hit, that is, whether or not the semaphore byte is held in the cache memory 22.

When the comparison results match, that is, when there is a hit, the match signal EQ1 is sent to the selection information generating circuit 112. At the same time, the control switching circuit 111
The switching signal 1111 which is the output of the selection information generation circuit 1
12 and its output gives the selector 109 a signal for selecting the least significant byte of the buffer memory 116.
The selector 109 selects the semaphore byte held in the least significant byte of the buffer memory 116, and the processor 2
Give to 0.

Further, if the comparison result does not match, that is, if it is a mishit, the address on the address bus 24-1 is passed through the memory interface 23 to the common bus 1.
2 and the shared memory 14 is accessed via the memory control circuit 13. The data read from the shared memory 14 is input to the cache memory 22 via the memory control circuit 13, the common bus 12, the memory interface 23, and the memory data bus 28-1. Further, information indicating that the memory control circuit 13 is also a test and set access is stored in the memory interface 2.
3, transmitted via the common bus 12 and the memory control circuit 1
The semaphore control circuit 31 for the shared memory 14
Provides test and set access. That is,
The semaphore byte is read and 1 is set to the most significant bit position at the same time, and the data before being set to 1 is returned to the data processor as read data. This read data is transferred to the cache memory 2 via the memory control circuit 13, the common bus 12 and the memory interface 23.
Entered in 2.

In this case, read data of only necessary bytes is transferred to the processor 20 via the selector 109, instead of access in block units as in normal memory access. The cache memory control signal generation circuit 108 also generates a write enable signal 26-2 and sets the read data in the least significant byte of the buffer memory 116. Also, address save register 1
The value 01 is newly set in the tag 102, and the tag mode flag M of the tag mode flag register 106 is set to 1 to indicate that the data held in the cache memory 22 is a semaphore byte.

Next, when another data processing device or the like writes to the shared memory 14, the address thereof is passed through the memory control circuit 13, the common bus 12, the memory interface 23, and the cache invalidation address bus 27 to the cache invalidation address register 103. Given to and set. At this time, when the tag mode flag M is 0, that is, when the data held in the cache memory 22 is block data, the comparator 107 sets the tag and the address at which another device has accessed the shared memory. The address to be compared with the existing address is the upper 28 bits.
As a result of comparing the cache invalid address register 103 and the upper 28 bits of the tag 102, if they match, the valid flag V of the valid flag register is reset and the data in the cache memory 22 is invalidated.

When the tag mode flag M is 1 when another data processing device or the like writes to the shared memory 14, that is, when the data held in the cache memory 22 is a semaphore byte, the comparator 107 In, the comparison target address of the address accessed by the other device to the shared memory and the address set in the tag is all 32 bits. If they match as a result of the comparison, the valid flag V of the valid flag register 105 is reset and the data in the cache memory 22 is invalidated, as described above. (In this case, it is premised that writing to the semaphore byte is limited to 1-byte writing.)

In the above embodiment, when the read semaphore bit is 0, the semaphore control circuit 31 of the memory control circuit 13 sets the semaphore bit 41 of the shared memory 14 to 1 by the test and set instruction.
Rewrite On the other hand, the semaphore byte held in the cache memory 22 is 0 before update read from the shared memory 14 by the test and set instruction, and the semaphore bytes of the shared memory 14 and the cache memory 22 are different.

However, normally, the semaphore byte is accessed again when the semaphore bit of the read data is 1, that is, when the acquisition of the exclusive right of the shared resource 42 fails. In this case, the shared memory 1
When the semaphore byte 4 is accessed, the semaphore byte is not rewritten, and the semaphore byte of the shared memory 14 and the semaphore byte of the cache memory 22 match.

When another device finishes accessing the shared resource 42 and rewrites the semaphore bit of the shared memory 14 to 0, the data in the cache memory 22 is invalidated as described above, and the semaphore byte read by the processor 20 is performed. At this time, the semaphore byte of the shared memory 14 is read and the data of the cache memory 22 is rewritten to 0. As described above, the semaphore byte of the shared memory 14 and the semaphore byte of the cache memory 22 do not match only when the own processor 20 succeeds in acquiring the exclusive right of the shared resource 42. Since we don't read the semaphore bytes after we get the exclusive right, the above inconsistency is not a problem.

As described above, according to the first embodiment of the present invention, even if the semaphore bytes are fetched into the cache memory 22, it is possible to realize efficient access without any contradiction. It is not impossible to read the semaphore bytes even after the acquisition of the exclusive right. In this case, since the mismatch between the shared memory 14 and the cache memory 22 is only the semaphore bit of the semaphore byte, this is a problem within the range that can be considered when creating a program. Next, consider the program creation. An embodiment will be described in which the shared memory 14 and the cache memory 22 can be kept consistent with each other.

FIG. 4 is a diagram showing another embodiment of the present invention in which the consistency between the shared memory 14 and the cache memory 22 can be maintained as described above. In this embodiment, as shown in FIG. , The portion corresponding to the semaphore bit of the data on the memory data bus from the memory interface 23 is transferred via the line 28-2 to the cache control circuit 21.
To enter.

The semaphore bits input to the cache control circuit 21 are input to the cache memory control signal generation circuit 108 shown in FIG. The cache memory control signal generation circuit 108 writes to the cache memory 22 only when the semaphore bit read from the shared memory 14 is 1, and when the semaphore bit is 0, the cache memory 22.
Not write to. In this case, the address of the address save register 101 is not written in the tag 102, and the valid flag V is not set. That is, when the semaphore bit is 0, the previously registered state is maintained.

As a result, the mismatch between the shared memory 14 and the cache memory 22 as in the first embodiment does not occur, and the matching is completely maintained. In the embodiment described above, if the semaphore bit is 0, it will not be registered in the cache memory 22, so if the program tries to read the semaphore byte again, a mishit occurs and the shared Since the memory 14 is accessed, there is a drawback that the access time is delayed.

The third embodiment of the present invention is to improve the above-mentioned drawbacks. As shown in FIG. 4, the semaphore bit is forcibly set in the cache memory 22 at the time of a miss hit by the test and set. The signal 26-3 is transmitted. That is, in FIG. 4, at the time of a mishit in the test and set, when the cache memory control signal generation circuit 108 of the cache control circuit 21 sends the write enable signal 26-2 to the buffer memory 116, the semaphore bit forced set signal is output. 26-3 is transmitted. This signal is sent to the buffer memory 116 via the OR circuit 110 and forcibly sets the most significant bit of the least significant byte of the buffer memory 116, that is, the bit corresponding to the semaphore bit to 1.

That is, in the memory access by the test and set, the semaphore bit of the shared memory 14 is always updated to 1, so that the cache memory 22 may also be the memory access by the test and set. If transmitted by the access information, the same update as the shared memory 14 can be performed. According to this embodiment, the data in the shared memory 14 and the cache memory 22 completely match each other, and the shared memory 14
Since the data of 1 is always registered in the cache memory 22, it is possible to access at high speed even when the data is read again.

[0044]

As is clear from the above description,
According to the present invention, even when a semaphore area is accessed by a test and set instruction or the like, the cache memory can be effectively used, so that the system performance can be greatly improved.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram showing an overall configuration of the present invention.

FIG. 3 is a diagram showing an embodiment of the present invention.

FIG. 4 is a diagram showing another embodiment of the present invention.

[Explanation of symbols]

1, 3, 11-1, 11-2 Data processing device 2, 12 Common bus 13 Memory control circuit 4, 14 Shared memory 1a, 20 Processor 1c, 21 Cache control circuit 1b, 22 Cache memory 23 Memory interface 24-1 Address Bus 24-2 Access information bus 25 Data bus 26 Cache control signal 27 Cache invalidation address bus 28-1 Memory data bus 31 Semaphore control circuit 41 Semaphore area 4b, 42 Shared resource 101 Address save register 102 Tag 103 Memory address register 104, 107 Comparator 105 Effective Flag Register 106 Tag Mode Flag Register 108 Cache Memory Control Signal Generation Circuit 109 Data Selection Circuit 110 OR Circuit 111 Control Switching Circuit 112 Selection Information Generation Synthesis circuit 113, 114, 115, 116 Buffer memory

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[Procedure amendment]

[Submission date] January 14, 1993

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Figure 5

[Correction method] Added

[Correction content]

FIG. 5 is a diagram showing a format of a semaphore area.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yasutoshi Sakurai 1015 Kamiodanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Koichi Odawara, 1015, Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Takumi Nonaka 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Eiji Kanaya, 1015, Kamikodanaka, Nakahara-ku, Kawasaki, Kanagawa Prefecture

Claims (6)

[Claims] 1. A data processing device (1) having a cache memory (1b) and a shared resource accessed by a plurality of data processing devices (1, 3).
(4b) and shared memory (4), the specific area (4a) provided on the shared memory (4) is tested and updated by a single memory access. Exclusive operation of the shared resource (4b) by a specific operation. In the cache control method in the data processing device (1) that realizes control, a cache that holds a copy of the specific area (4a) when the specific area (4a) on the shared memory (4) is read by the specific operation described above. When the memory (1b) is accessed and there is no copy of the specified area (4a) in the cache memory (1b), the specified area (4a) on the shared memory (4) is read and the data processing device (1 ) In the processor (1a), write to the cache memory (1b), and if there is a copy of the specific area (4a) in the cache memory (1b), access only the cache memory (1b). Access shared memory (4) Without a specific region (4 other data processing device (3) is a shared memory (4)
A cache control method comprising a cache control means (1c) for invalidating the cache memory (1b) when a write is performed to a). 2. A shared memory according to a specific operation.
(4) When reading the specific area (4a) above, the specific area (4a)
Access the cache memory (1b) that holds a copy of the specified area, and if there is no copy of the specified area (4a) in the cache memory (1b), read the specified area (4a) on the shared memory (4). Is sent to the processor (1a) of the data processing device (1) and the specific area (4a) is a specific value indicating that the shared resource (4b) is being accessed by another data processing device (3). 2. The cache control method according to claim 1, wherein the specific value is written to the cache memory (1b) only in the case. 3. A shared memory according to a specific operation.
(4) When reading the specific area (4a) above,
If the cache memory (1b) holding the copy of a) is accessed and there is no copy of the specified area (4a) in the cache memory (1b), the specified area (4a) on the shared memory (4) is A specific value that indicates that the data is read and sent to the processor (1a) of the data processing device (1) and that the shared memory (4b) is being accessed by the other data processing device (3) in the cache memory (1b). 2. The cache control method according to claim 1, wherein the value replaced with is written. 4. A cache control system according to claim 1, wherein the cache memory (1b) is also used as a cache memory in a normal memory access. 5. The cache control method according to claim 4, further comprising means for separating a cache hit determination in a specific operation from a cache hit determination in a normal memory access. 6. A means for separating writing of data into the cache memory (1b) at the time of a cache miss in a specific operation and writing of data into the cache memory (1b) at the time of a cache miss in a normal memory access. The cache control method according to claim 4 or 5, characterized in that.