JPH0514313A - Automatic gain control circuit - Google Patents
Automatic gain control circuitInfo
- Publication number
- JPH0514313A JPH0514313A JP3186798A JP18679891A JPH0514313A JP H0514313 A JPH0514313 A JP H0514313A JP 3186798 A JP3186798 A JP 3186798A JP 18679891 A JP18679891 A JP 18679891A JP H0514313 A JPH0514313 A JP H0514313A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- output
- gain control
- circuit
- transmission
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【0001】[0001]
【技術分野】本発明は、スペクトル拡散通信方式におけ
る自動利得制御回路に関する。例えば、スペクトル拡散
通信や無線通信に適用されるものである。TECHNICAL FIELD The present invention relates to an automatic gain control circuit in a spread spectrum communication system. For example, it is applied to spread spectrum communication and wireless communication.
【0002】[0002]
【従来技術】本発明に係る従来技術を記載した公知文献
としては、例えば、特開昭61−93745号公報があ
る。この公報の「スペクトル拡散送受信装置」は、情報
信号で電圧制御発振器の発振周波数を変え、この発振信
号を擬似雑音発生器により擬似雑音を発生させるクロッ
クとすると共に、前記発振信号と前記擬似雑音とでスペ
クトラム拡散して送信し、受信部では相関検出器、バン
ドパスフィルタ、電圧制御発振器、擬似雑音発生器等で
ループ形成することにより、従来より簡単な構成で、し
かも直流ドリフトの影響を受けにくくしたものである。
しかしながら、PN符号の自己相関特性を利得制御信号
に用いるため、相関特性が三角形状であり、そのため、
位相変動があると受信信号の増幅利得まで変動するとい
う欠点があった。2. Description of the Related Art As a known document describing the prior art of the present invention, there is, for example, Japanese Patent Laid-Open No. 61-93745. The "spread spectrum transmitter / receiver" of this publication changes the oscillation frequency of a voltage-controlled oscillator with an information signal and uses this oscillation signal as a clock for generating pseudo noise by a pseudo noise generator, and at the same time, generates the oscillation signal and the pseudo noise. With the spread spectrum, the signal is transmitted, and the receiving section forms a loop with a correlation detector, bandpass filter, voltage controlled oscillator, pseudo noise generator, etc., which has a simpler configuration than before and is less susceptible to DC drift. It was done.
However, since the autocorrelation characteristic of the PN code is used for the gain control signal, the correlation characteristic has a triangular shape.
If there is a phase variation, there is a drawback that the amplification gain of the received signal also varies.
【0003】これを防止する方法として、受信側で1チ
ップ分時間ずれた2つのPN符号を用意し、夫々の受信
信号との相関を相関器により求め、両者の和を利得制御
信号とすることにより、同期点近傍における相関特性を
平坦にし、位相変動の影響を受けない利得制御信号を得
ることが出来る。しかし、新たなる問題点として、回路
に何等かの非対称性がある場合に両信号のバランスがく
ずれ、やはり位相変動が受信信号の増幅利得の変動を招
くという欠点を生じる。As a method of preventing this, two PN codes that are time-shifted by one chip are prepared on the receiving side, the correlation with each received signal is obtained by a correlator, and the sum of the two is used as a gain control signal. This makes it possible to flatten the correlation characteristic in the vicinity of the synchronization point and obtain a gain control signal that is not affected by phase fluctuations. However, as a new problem, when there is some asymmetry in the circuit, the two signals are out of balance, and the phase variation also causes a variation in the amplification gain of the received signal.
【0004】図4(a)〜(c)は、前記公報に記載さ
れている従来のスペクトル拡散送受信装置の構成図で、
図(a)は送信機、図(b)は受信機、図(c)は相関
特性を示す図である。図中、31は電圧制御発振器、3
2は分周器、33はPN符号発生器、34は乗算器、3
5は利得制御増幅器、36は相関検波器、37は電圧制
御発振器、38はPN符号発生器、39は乗算器、40
は帯域通過フィルタ(BPF)、41は検波器である。FIGS. 4A to 4C are block diagrams of the conventional spread spectrum transmitter / receiver described in the above publication.
FIG. 7A is a transmitter, FIG. 8B is a receiver, and FIG. 8C is a diagram showing correlation characteristics. In the figure, 31 is a voltage controlled oscillator, 3
2 is a frequency divider, 33 is a PN code generator, 34 is a multiplier, 3
5 is a gain control amplifier, 36 is a correlation detector, 37 is a voltage controlled oscillator, 38 is a PN code generator, 39 is a multiplier, 40
Is a band pass filter (BPF), and 41 is a detector.
【0005】図(a)の送信側においては、電圧制御発
振器31の出力を分周器32で分周し、該分周器32の
出力でPN符号発生器33を駆動し、該PN符号発生器
33の出力と前記電圧制御発振器31の出力を乗算器3
4により掛合わせて送信信号としている。一方、受信側
では、受信信号を利得制御増幅器35で増幅した後、同
期復調部により受信信号と同期の取れたPN符号を生成
し、PN符号発生器38と増幅された受信信号を乗算器
39により掛合わせて逆拡散し、これを帯域通過フィル
タ(BPF)40に対して検波器41により信号の振幅
を求め、該検波器41の出力を制御信号として利得制御
増幅器35の利得制御を行なっている。この時、逆拡散
過程において同一符号の相関を求めているため、その相
関特性は図(c)の様な三角形状になる。同期点はその
ピーク点にあるので同期点の位相が進んでも遅れても相
関値が小さくなり、制御信号に変動を来たす。On the transmission side of FIG. 1A, the output of the voltage controlled oscillator 31 is divided by a frequency divider 32, and the PN code generator 33 is driven by the output of the frequency divider 32 to generate the PN code. The output of the multiplier 33 and the output of the voltage controlled oscillator 31 are multiplied by the multiplier 3
4 is used as a transmission signal. On the other hand, on the receiving side, after the received signal is amplified by the gain control amplifier 35, a PN code synchronized with the received signal is generated by the synchronous demodulation unit, and the PN code generator 38 and the amplified received signal are multiplied by the multiplier 39. The signal amplitude is obtained by the detector 41 for the band pass filter (BPF) 40, and the gain control of the gain control amplifier 35 is performed by using the output of the detector 41 as a control signal. There is. At this time, since the correlation of the same code is obtained in the despreading process, the correlation characteristic has a triangular shape as shown in FIG. Since the synchronization point is at the peak point, the correlation value becomes small regardless of whether the phase of the synchronization point is advanced or delayed, which causes fluctuation in the control signal.
【0006】[0006]
【目的】本発明は、上述のごとき実情に鑑みてなされた
もので、拡散信号自体に工夫を施すことにより、1つの
相関器で同期点近傍で平坦な相関特性を実現し、これを
利得制御信号に用いることで、位相変動の影響を受けな
い利得制御回路を提供すること、また、従来の2つの相
関器を用いる方式に対しては、回路のバランスを考慮す
る必要をなくし、相関器が1つになることで回路構成を
大幅に簡単化すること、さらに、送信拡散信号または受
信拡散信号に工夫を懲らすことで相関特性のピーク部分
を平坦にし、位相の変動による相関特性の変動を無くし
て利得制御の安定化を図るようにした自動利得制御回路
を提供することを目的としてなされたものである。[Object] The present invention has been made in view of the above-described circumstances, and by devising the spread signal itself, one correlator realizes a flat correlation characteristic in the vicinity of the synchronization point, and gain control By providing a gain control circuit that is not affected by phase fluctuations by using it for a signal, and with respect to the conventional method using two correlators, there is no need to consider the circuit balance, and The circuit configuration is greatly simplified by becoming one, and the peak part of the correlation characteristic is flattened by discriminating the transmission spread signal or the reception spread signal, and the fluctuation of the correlation characteristic due to the phase fluctuation. It is an object of the present invention to provide an automatic gain control circuit which eliminates the above and stabilizes the gain control.
【0007】[0007]
【構成】本発明は、上記目的を達成するために、(1)
情報信号によって発振周波数を制御される電圧制御発振
器と、該電圧制御発振器の出力をクロック信号として擬
似雑音符号を発生する擬似雑音符号発生器と、該擬似雑
音符号発生器の出力信号を2分し、一方の出力信号を入
力する遅延回路と、該遅延回路の出力を入力し、前記擬
似雑音符号発生器の2分された他方の出力信号とを入力
して送信信号とする加算器とから成る送信回路と、該送
信回路からの送信信号を受信信号として増幅する利得制
御増幅器と、該利得制御増幅器の出力信号と、前記送信
回路と同一の擬似雑音符号発生器からの出力信号との相
関を演算する相関器と、該相関器の相関出力の直流成分
のみを通過させ、前記利得制御増幅器の制御信号を出力
する低域通過フィルタとから成る受信回路を有するこ
と、或いは、(2)情報信号によって発振周波数を制御
される電圧制御発振器と、該電圧制御発振器の出力をク
ロック信号として擬似雑音符号を発生する擬似雑音符号
発生器と、該擬似雑音符号発生器の出力信号を2分し、
一方の出力信号を入力する遅延回路と、該遅延回路の出
力を入力し、前記擬似雑音符号発生器の2分された他方
の出力信号を入力する加算器と、該加算器の出力と前記
電圧制御発振器の出力とを掛け合わせて送信信号とする
乗算器とから成る送信回路と、該送信回路からの送信信
号を受信信号として増幅する利得制御増幅器と、該利得
制御増幅器の出力信号と前記送信回路と同一の擬似雑音
符号発生器からの出力信号との相関を演算する相関器
と、該相関器の相関出力の搬送波成分のみを通過させる
帯域通過フィルタと、該帯域通過フィルタの出力を検波
し、前記利得制御増幅器の制御信号を出力する検波器と
から成る受信回路を有すること、更には、(3)前記
(1)又は(2)において、前記情報信号により変調を
受けた信号を2分し、一方を遅延回路に通した後に再び
足し合わせる代りに、擬似雑音符号の1チップ時間内に
おける信号の送信時間幅を狭めたものを送信信号とした
こと、更には、(4)前記(1),(2)又は(3)の
送信回路における擬似雑音符号発生器と遅延回路と加算
器の回路部分あるいは擬似雑音符号の1チップ時間内に
おける信号の送信時間幅を狭めた符号の発生回路部分を
受信側の擬似雑音符号発生器で構成したことを特徴とし
たものである。以下、本発明の実施例に基づいて説明す
る。In order to achieve the above object, the present invention provides (1)
A voltage-controlled oscillator whose oscillation frequency is controlled by an information signal, a pseudo-noise code generator that generates a pseudo-noise code using the output of the voltage-controlled oscillator as a clock signal, and an output signal of the pseudo-noise code generator A delay circuit for inputting one output signal and an adder for inputting the output of the delay circuit and the other half of the output signal of the pseudo-noise code generator for inputting as a transmission signal. A transmission circuit, a gain control amplifier that amplifies the transmission signal from the transmission circuit as a reception signal, an output signal of the gain control amplifier, and a correlation between an output signal from the same pseudo noise code generator as the transmission circuit. A receiving circuit composed of a correlator for calculation and a low-pass filter for passing only the DC component of the correlation output of the correlator and outputting the control signal of the gain control amplifier; or (2) A voltage-controlled oscillator whose oscillation frequency is controlled by a report signal, a pseudo-noise code generator that generates a pseudo-noise code using the output of the voltage-controlled oscillator as a clock signal, and an output signal of the pseudo-noise code generator are divided into two. ,
A delay circuit for inputting one output signal, an adder for inputting the output of the delay circuit and the other half of the output signal of the pseudo noise code generator, an output of the adder and the voltage A transmission circuit comprising a multiplier for multiplying the output of the controlled oscillator into a transmission signal, a gain control amplifier for amplifying the transmission signal from the transmission circuit as a reception signal, an output signal of the gain control amplifier and the transmission A correlator that calculates the correlation with the output signal from the same pseudo-noise code generator as the circuit, a band-pass filter that passes only the carrier component of the correlation output of the correlator, and the output of the band-pass filter is detected. A receiver circuit comprising a detector for outputting a control signal of the gain control amplifier, and (3) the signal modulated by the information signal in (1) or (2) is divided into two parts. Then Instead of passing the signal through a delay circuit and then adding them again, a signal having a narrower signal transmission time width within one chip time of the pseudo noise code is used as the transmission signal, and further, (4) above (1), The circuit portion of the pseudo noise code generator, the delay circuit, and the adder in the transmission circuit of (2) or (3) or the code generation circuit portion in which the transmission time width of the signal within one chip time of the pseudo noise code is narrowed is received. It is characterized by being configured by a pseudo noise code generator on the side. Hereinafter, description will be given based on examples of the present invention.
【0008】図1(a)〜(c)は、本発明による自動
利得制御回路の一実施例を説明するための構成図で、図
(a)は送信機(送信回路)、図(b)は受信機(受信
回路)、図(c)は相関特性を示す図である。図中、1
は電圧制御発振器、2はPN符号発生器、3は遅延回
路、4は加算器、5は利得制御増幅器、6は相関器、7
は電圧制御発振器、8はPN符号発生器、9は乗算器、
10は低域通過フィルタ(LPF)である。PN符号と
してM系列を用いた場合、その自己相関特性は図4
(c)のようになる。従って、送受信の一方においてP
N符号を±1/2チップずらしたものを足し合わせて元
のPN符号と相関を取ると、その特性は図1(c)のよ
うな台形状となる。この相関出力を利得制御に用いたも
のが図1に示す実施例(請求項1)である。図(a)の
送信側においては、情報信号によって電圧制御発振器1
の発振周波数を制御し、該電圧制御発振器1の出力をク
ロック信号としてPN符号発生器2を駆動してPN符号
を発生させる。続いて、該PN符号発生器2の出力を2
分し、一方のみ遅延回路3に通して1チップ分遅らせた
後、加算器4に入力して両者の和信号を生成して送信信
号とする。前記PN符号発生器2の出力を±1とする
と、送信信号は±2,0の3値を取ることになる。1 (a) to 1 (c) are configuration diagrams for explaining an embodiment of an automatic gain control circuit according to the present invention. FIG. 1 (a) is a transmitter (transmission circuit) and FIG. 1 (b). Is a receiver (reception circuit), and FIG. 7C is a diagram showing correlation characteristics. 1 in the figure
Is a voltage controlled oscillator, 2 is a PN code generator, 3 is a delay circuit, 4 is an adder, 5 is a gain control amplifier, 6 is a correlator, and 7
Is a voltage controlled oscillator, 8 is a PN code generator, 9 is a multiplier,
Reference numeral 10 is a low pass filter (LPF). When the M sequence is used as the PN code, its autocorrelation characteristic is shown in FIG.
It becomes like (c). Therefore, P
When the values obtained by shifting the N code by ± 1/2 chip are added and the correlation with the original PN code is obtained, the characteristic becomes a trapezoidal shape as shown in FIG. An embodiment (claim 1) shown in FIG. 1 uses this correlation output for gain control. On the transmission side in FIG. 3A, the voltage-controlled oscillator 1
Of the voltage controlled oscillator 1 is used as a clock signal to drive a PN code generator 2 to generate a PN code. Then, the output of the PN code generator 2 is set to 2
Then, only one of them is passed through the delay circuit 3 to be delayed by one chip, and then input to the adder 4 to generate a sum signal of the two, which is used as a transmission signal. When the output of the PN code generator 2 is ± 1, the transmission signal has three values ± 2 and 0.
【0009】受信側においては、まず利得制御増幅器5
で受信信号を増幅し、該利得制御増幅器5の出力を2分
して、一方をPN符号の同期及び復調に用いる。他方の
出力は同期復調部からの同期の取れたPN符号と乗算器
9により掛合され、低域通過フィルタ10により直流成
分のみが取り出されて利得制御増幅器5の制御信号とな
る。該利得制御信号の特性は遅延時間に対して、図1
(c)のような台形状になるため、遅延量0の付近で多
少の位相変動が生じても利得制御増幅器5に影響を及ぼ
すことが無い。なお、この実施例では遅延回路3の遅延
量が丁度1チップの場合について述べたが、この値に限
るものではない。但し、遅延量をもっと少なくしても多
くしても相関出力が平坦な領域は減少する。On the receiving side, first, the gain control amplifier 5
The received signal is amplified at 2, the output of the gain control amplifier 5 is divided into two, and one is used for synchronization and demodulation of the PN code. The other output is multiplied by the synchronized PN code from the synchronous demodulation unit by the multiplier 9, and the low-pass filter 10 extracts only the DC component and becomes the control signal of the gain control amplifier 5. The characteristics of the gain control signal are shown in FIG.
Because of the trapezoidal shape as shown in (c), the gain control amplifier 5 is not affected even if some phase fluctuation occurs near the delay amount 0. Although the delay amount of the delay circuit 3 is just one chip in this embodiment, the delay amount is not limited to this value. However, even if the delay amount is further reduced or increased, the area where the correlation output is flat decreases.
【0010】図2は、本発明による自動利得制御回路の
他の実施例を示す図で、図中、11は分周器、12は乗
算器、13は帯域通過フィルタ(BPF)、14は検波
器で、その他、図1と同じ作用をする部分は同一の符号
を付してある。図1の実施例と異なるのは、送信側にお
いて、電圧制御発振器1の出力を分周器11により分周
し、該分周器11の出力をクロック信号として駆動した
PN符号を前記電圧制御発振器1の出力と掛合わせて送
信信号としている点である。このため、送信信号を無線
帯域に移すことが可能で、本発明を無線通信に応用でき
る。受信側においては、これに対応して利得制御増幅器
5で増幅した受信信号を、これを用いて同期復調部で生
成したPN符号と乗算器9により掛合わせ、帯域通過フ
ィルタ13により逆拡散された搬送波成分のみを取り出
して検波器14により検波し、利得制御増幅器5の利得
制御信号とする。FIG. 2 is a diagram showing another embodiment of the automatic gain control circuit according to the present invention. In the figure, 11 is a frequency divider, 12 is a multiplier, 13 is a band pass filter (BPF), and 14 is detection. Other parts that have the same functions as those in FIG. 1 are denoted by the same reference numerals. The difference from the embodiment of FIG. 1 is that, on the transmission side, the output of the voltage controlled oscillator 1 is frequency-divided by a frequency divider 11, and the PN code driven by using the output of the frequency divider 11 as a clock signal is used as the voltage controlled oscillator. The point is that the output of 1 is multiplied to form a transmission signal. Therefore, the transmission signal can be transferred to the wireless band, and the present invention can be applied to wireless communication. On the receiving side, the received signal amplified by the gain control amplifier 5 corresponding to this is multiplied by the PN code generated in the synchronous demodulation section by this using the multiplier 9 and despread by the band pass filter 13. Only the carrier wave component is taken out and detected by the detector 14 to be the gain control signal of the gain control amplifier 5.
【0011】図3(a),(b)は、本発明による自動
利得制御回路の更に他の実施例(請求項3)を示す図
で、図(a)は送信機、図(b)は相関特性を示す図で
ある。図中、21は電圧制御発振器、22はPN符号発
生器、23はスイッチである。図1(c)の相互相関特
性を持つ符号を使用する代りに、図3(b)の相互相関
特性を持つ符号を使用する。この符号は通常のPN符号
をその駆動クロックの半周期だけ出力することにより得
られる。PN符号発生器22からの±1の出力をスイッ
チ23に入力し、符号クロックでこのスイッチ23のO
N,OFFを制御すれば良い。スイッチ23としてはト
ランジスタやFET等種々のものが考えられる。図1,
図2中の遅延回路3と加算器4の代りに図3の回路を用
いることで、図3(b)の相互相関特性が得られ、遅延
時間の影響を受けない利得制御信号を得ることが出来
る。なお、ここでは出力をクロックの半周期としたが、
これに限るものではなく、出力期間を短くするほど相関
出力がピークを示す範囲が広がるとともに、ピーク値が
下がる。3 (a) and 3 (b) are views showing still another embodiment (claim 3) of the automatic gain control circuit according to the present invention. FIG. 3 (a) is a transmitter, and FIG. It is a figure which shows a correlation characteristic. In the figure, 21 is a voltage controlled oscillator, 22 is a PN code generator, and 23 is a switch. Instead of using the code having the cross-correlation characteristic of FIG. 1C, the code having the cross-correlation characteristic of FIG. 3B is used. This code is obtained by outputting a normal PN code for only half a cycle of the drive clock. The ± 1 output from the PN code generator 22 is input to the switch 23, and the O of the switch 23 is turned on by the code clock.
It is sufficient to control N and OFF. As the switch 23, various types such as transistors and FETs can be considered. Figure 1,
By using the circuit of FIG. 3 instead of the delay circuit 3 and the adder 4 in FIG. 2, the cross-correlation characteristic of FIG. 3B can be obtained, and a gain control signal that is not affected by the delay time can be obtained. I can. In addition, here, the output is a half cycle of the clock,
The present invention is not limited to this, and the shorter the output period is, the wider the range where the correlation output shows a peak and the lower the peak value are.
【0012】次に、請求項4の発明は、請求項1〜3で
述べた発明における送信側と受信側のPN符号を入替え
たもので、送信側の回路構成を簡単にしたい場合に有効
である。以上の例はすべてPN符号の駆動クロック周波
数を変調する形式の送受信機について述べたが、変復調
方式に関してはこれ以外にも振幅変調や位相変調等が考
えられ、これらについても本発明が適用できるのはもち
ろんのことである。同期を取るだけのためならば変調す
る必要もない。また、伝送媒体としては、有線以外に電
波や光等も使用できる。Next, the invention of claim 4 is the one in which the PN codes on the transmitting side and the receiving side in the invention described in claims 1 to 3 are interchanged, and is effective when it is desired to simplify the circuit configuration on the transmitting side. is there. Although all of the above examples have described the transmitter / receiver of the type that modulates the drive clock frequency of the PN code, the modulation / demodulation method may be amplitude modulation, phase modulation, or the like, and the present invention can be applied to these. Of course. There is no need for modulation if only synchronization is required. Further, as the transmission medium, radio waves, light, etc. can be used in addition to the wired communication.
【0013】[0013]
【効果】以上の説明から明らかなように、本発明による
と、以下のような効果がある。
(1)請求項1に対応する効果:送信側でPN符号を発
生させ、その出力信号を2分して一方を遅延回路に通し
た後、再び足し合わせた信号と、受信側のPN符号の相
関を求め、相関出力を直流成分のみ通過させるLPFに
通して利得制御信号としているため、相関値が一定の領
域で動作可能で、増幅器の利得が送受信機間のPN符号
間の位相変動による影響を受けない。
(2)請求項2に対応する効果:送信側でPN符号を発
生させ、その出力信号を2分して一方を遅延回路に通し
た後、再び足し合わせ、さらに搬送波を乗算器により掛
合わせた信号と、受信側のPN符号の相関を求め、相関
出力を搬送波帯域のみ通過させるBPFに通して検波
し、利得制御信号としているため、相関値が一定の領域
で動作可能で、増幅器の利得が送受信機間のPN符号間
の位相変動による影響を受けない。
(3)請求項3に対応する効果:情報信号により変調を
受けた信号を2分して一方を遅延回路に通した後、再び
足し合わせる代りに、PN符号の1チップ時間内におけ
る信号の送信時間幅を狭めた信号を送信信号として用い
たため、非常に簡単な回路を付加するだけで、請求項
1,2と同様の効果が得られる。また、信号を送信しな
い時間があるので、送信電力を低減にもつながる。
(4)請求項4に対応する効果:請求項1〜3の発明に
おける符号を送受信機間で交換しても同様の作用効果が
得られることを利用しており、回路設計上の自由度を増
すことが出来る。As is apparent from the above description, the present invention has the following effects. (1) Effect corresponding to claim 1: A PN code is generated on the transmitting side, its output signal is divided into two, one is passed through a delay circuit, and then the summed signal and the PN code on the receiving side are added. Since the gain control signal is obtained by calculating the correlation and passing the correlation output through the LPF that passes only the DC component, the correlation value can operate in a constant region, and the gain of the amplifier is affected by the phase fluctuation between the PN codes between the transmitter and the receiver. Do not receive (2) Effect corresponding to claim 2: A PN code is generated on the transmission side, the output signal is divided into two, one is passed through a delay circuit, then added again, and the carrier is multiplied by a multiplier. The correlation between the signal and the PN code on the receiving side is obtained, and the correlation output is detected by passing it through the BPF that passes only the carrier band, and the gain control signal is used. Therefore, the correlation value can operate in a constant region and the gain of the amplifier can be increased. It is not affected by the phase fluctuation between PN codes between the transmitter and the receiver. (3) Effect corresponding to claim 3: Instead of halving a signal modulated by an information signal and passing one through a delay circuit and then adding them again, transmission of the signal within one chip time of the PN code Since the signal whose time width is narrowed is used as the transmission signal, the same effects as those of claims 1 and 2 can be obtained by only adding a very simple circuit. Moreover, since there is a time when no signal is transmitted, the transmission power can be reduced. (4) Effect corresponding to claim 4: The fact that the same function and effect are obtained even if the codes in the inventions of claims 1 to 3 are exchanged between the transmitter and the receiver is utilized, and the degree of freedom in circuit design is increased. Can be increased.
【図1】 本発明による自動利得制御回路の一実施例を
説明するための構成図である。FIG. 1 is a configuration diagram for explaining an embodiment of an automatic gain control circuit according to the present invention.
【図2】 本発明による自動利得制御回路の他の実施例
を説明するための構成図である。FIG. 2 is a configuration diagram for explaining another embodiment of the automatic gain control circuit according to the present invention.
【図3】 本発明による自動利得制御回路の更に他の実
施例を説明するための構成図である。FIG. 3 is a configuration diagram for explaining still another embodiment of the automatic gain control circuit according to the present invention.
【図4】 従来のスペクトル拡散送受信装置の構成図で
ある。FIG. 4 is a block diagram of a conventional spread spectrum transmitter / receiver.
1…電圧制御発振器、2…PN符号発生器、3…遅延回
路、4…加算器、5…利得制御増幅器、6…相関器、7
…電圧制御発振器、8…PN符号発生器、9…乗算器、
10…低域通過フィルタ(LPF)。1 ... Voltage controlled oscillator, 2 ... PN code generator, 3 ... Delay circuit, 4 ... Adder, 5 ... Gain control amplifier, 6 ... Correlator, 7
... voltage-controlled oscillator, 8 ... PN code generator, 9 ... multiplier,
10 ... Low-pass filter (LPF).
Claims (4)
る電圧制御発振器と、該電圧制御発振器の出力をクロッ
ク信号として擬似雑音符号を発生する擬似雑音符号発生
器と、該擬似雑音符号発生器の出力信号を2分し、一方
の出力信号を入力する遅延回路と、該遅延回路の出力を
入力し、前記擬似雑音符号発生器の2分された他方の出
力信号とを入力して送信信号とする加算器とから成る送
信回路と、該送信回路からの送信信号を受信信号として
増幅する利得制御増幅器と、該利得制御増幅器の出力信
号と、前記送信回路と同一の擬似雑音符号発生器からの
出力信号との相関を演算する相関器と、該相関器の相関
出力の直流成分のみを通過させ、前記利得制御増幅器の
制御信号を出力する低域通過フィルタとから成る受信回
路を有することを特徴とする自動利得制御回路。1. A voltage-controlled oscillator whose oscillation frequency is controlled by an information signal, a pseudo-noise code generator that generates a pseudo-noise code using the output of the voltage-controlled oscillator as a clock signal, and an output of the pseudo-noise code generator. A signal is divided into two, and a delay circuit for inputting one of the output signals and an output of the delay circuit for inputting the other half of the output signal of the pseudo noise code generator are input as transmission signals. A transmission circuit including an adder, a gain control amplifier for amplifying a transmission signal from the transmission circuit as a reception signal, an output signal of the gain control amplifier, and an output from the same pseudo noise code generator as the transmission circuit. It has a receiving circuit including a correlator that calculates a correlation with a signal and a low-pass filter that passes only the DC component of the correlation output of the correlator and outputs the control signal of the gain control amplifier. Automatic gain control circuit as a characteristic.
る電圧制御発振器と、該電圧制御発振器の出力をクロッ
ク信号として擬似雑音符号を発生する擬似雑音符号発生
器と、該擬似雑音符号発生器の出力信号を2分し、一方
の出力信号を入力する遅延回路と、該遅延回路の出力を
入力し、前記擬似雑音符号発生器の2分された他方の出
力信号を入力する加算器と、該加算器の出力と前記電圧
制御発振器の出力とを掛け合わせて送信信号とする乗算
器とから成る送信回路と、該送信回路からの送信信号を
受信信号として増幅する利得制御増幅器と、該利得制御
増幅器の出力信号と前記送信回路と同一の擬似雑音符号
発生器からの出力信号との相関を演算する相関器と、該
相関器の相関出力の搬送波成分のみを通過させる帯域通
過フィルタと、該帯域通過フィルタの出力を検波し、前
記利得制御増幅器の制御信号を出力する検波器とから成
る受信回路を有することを特徴とする自動利得制御回
路。2. A voltage controlled oscillator whose oscillation frequency is controlled by an information signal, a pseudo noise code generator which generates a pseudo noise code using the output of the voltage controlled oscillator as a clock signal, and an output of the pseudo noise code generator. A delay circuit that divides the signal into two and inputs one output signal; an adder that inputs the output of the delay circuit and the other divided output signal of the pseudo noise code generator; Circuit comprising a multiplier for multiplying the output of the voltage control oscillator and the output of the voltage controlled oscillator into a transmission signal, a gain control amplifier for amplifying the transmission signal from the transmission circuit as a reception signal, and the gain control amplifier A correlator for calculating the correlation between the output signal of the correlator and the output signal from the same pseudo-noise code generator as the transmission circuit, a band pass filter for passing only the carrier component of the correlation output of the correlator, and the band An automatic gain control circuit comprising a receiving circuit including a detector for detecting an output of a band pass filter and outputting a control signal of the gain control amplifier.
2分し、一方を遅延回路に通した後に再び足し合わせる
代りに、擬似雑音符号の1チップ時間内における信号の
送信時間幅を狭めたものを送信信号としたことを特徴と
する請求項1又は2記載の自動利得制御回路。3. A signal transmission time width within one chip time of a pseudo noise code is narrowed instead of dividing a signal modulated by the information signal into two and passing one through a delay circuit and then adding them again. 3. The automatic gain control circuit according to claim 1, wherein the automatic gain control circuit is a transmission signal.
ける擬似雑音符号発生器と遅延回路と加算器の回路部分
あるいは擬似雑音符号の1チップ時間内における信号の
送信時間幅を狭めた符号の発生回路部分を受信側の擬似
雑音符号発生器で構成したことを特徴とする自動利得制
御回路。4. A code in which the transmission time width of a signal within one chip time of the pseudo noise code generator, delay circuit and adder in the transmission circuit of claim 1, 2 or 3 or the pseudo noise code is narrowed. The automatic gain control circuit is characterized in that the generation circuit part of is composed of a pseudo noise code generator on the receiving side.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3186798A JPH0514313A (en) | 1991-07-01 | 1991-07-01 | Automatic gain control circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3186798A JPH0514313A (en) | 1991-07-01 | 1991-07-01 | Automatic gain control circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0514313A true JPH0514313A (en) | 1993-01-22 |
Family
ID=16194774
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3186798A Pending JPH0514313A (en) | 1991-07-01 | 1991-07-01 | Automatic gain control circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0514313A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0641109A3 (en) * | 1993-05-28 | 1995-03-15 | Canon Kabushiki Kaisha | Code generating method for spread spectrum communication |
-
1991
- 1991-07-01 JP JP3186798A patent/JPH0514313A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0641109A3 (en) * | 1993-05-28 | 1995-03-15 | Canon Kabushiki Kaisha | Code generating method for spread spectrum communication |
US5537396A (en) * | 1993-05-28 | 1996-07-16 | Canon Kabushiki Kaisha | Diffusion code generating method for spread spectrum communication |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP3229393B2 (en) | Spread spectrum communication system | |
AU729145B2 (en) | Method for wireless information transfer | |
JP2744644B2 (en) | Delay locked loop circuit in spread spectrum receiver. | |
US5301206A (en) | Spread spectrum communication system | |
US4926440A (en) | Spread-spectrum communication apparatus | |
JPH07123232B2 (en) | Synchronous tracking device for spread spectrum communication | |
US5099495A (en) | Spread spectrum communication device | |
JPH0514313A (en) | Automatic gain control circuit | |
JP2752565B2 (en) | Spread spectrum radio | |
JP3304340B2 (en) | Receiver using spread spectrum | |
JPH0629948A (en) | Synchronization tracking circuit | |
JPH046924A (en) | Spread spectrum communication synchronization circuit | |
JPH0442629A (en) | Spread spectrum communication system | |
JP2771663B2 (en) | Wireless device | |
JPH0255978B2 (en) | ||
RU2115236C1 (en) | Communication system with wide-band signals | |
RU2222111C2 (en) | Device for receiving phase-keyed signals under interference conditions | |
JPH057196A (en) | Spread spectrum modulation/demodulation system | |
KR940002104B1 (en) | Modulation and demodulation method | |
JPH04302553A (en) | Transmitter and receiver for spread spectrum communication and spread spectrum communication equipment | |
JPH02100546A (en) | Spectrum diffusion communication system | |
JPH08237168A (en) | Spread spectrum communication equipment | |
JPH05122192A (en) | Automatic gain control circuit for spread spectrum receiver | |
JPH06197091A (en) | Spread spectrum communication system | |
JPH05268190A (en) | Spread spectrum communication equipment |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20051228 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20060411 |
|
A02 | Decision of refusal |
Effective date: 20060808 Free format text: JAPANESE INTERMEDIATE CODE: A02 |