JPH051427B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a radar scan conversion device that converts a video signal of a radar into a video signal scanned by a plurality of other radars.

(Prior Art) In marine traffic control systems, multiple radars are sometimes installed at different locations on land to monitor the movements of ships. In such a case, if a structure such as an island or a large bridge exists within the monitored area, false images may occur due to shadowed areas or multiple reflections between the structure and the ship. In such a case, either install another radar at an appropriate location within the sea area to supplement the image of the shadowed sea area or remove false images, and add the image detected by that radar to the images of the plurality of radars, or combine both images. Image synthesis between radars may be performed by calculating the correlation between the two radars. For this kind of image synthesis,
A radar scan conversion device is used to store an image of the another radar in the screen memory of the device, read out the stored contents according to a scanning signal of one of the plurality of radars, and read out the radar image. I was compositing it with my own footage. However, with conventional radar scan conversion devices, only one radar can be used for readout scanning, so as in the case above, multiple main radars can be combined with images from other radars that will be provided later. However, in the case where the radar scan conversion device is used for a plurality of radars, a corresponding number of radar scan conversion devices are required.

(Object of the Invention) An object of the present invention is to provide a radar scan conversion device that solves the above-mentioned drawbacks of the prior art by allowing the same storage contents to be read out simultaneously from a plurality of radars.

(Structure of the Invention) The present invention includes an address generation circuit that converts each position in the pointing direction of each antenna of a writing radar and a plurality of reading radars into virtual X-Y coordinates and outputs it as an X-Y memory address; an address switching circuit that switches and outputs each of the addresses in a predetermined order; an input buffer circuit that temporarily stores a video signal in the pointing direction of the antenna of the writing radar; and an input buffer circuit that switches the video signal from the input buffer circuit to the address. an X-Y memory that temporarily stores the video signal according to the address corresponding to the writing radar from the switching circuit and reads and outputs the stored video signal according to the address corresponding to each reading radar from the address switching circuit; and an output switching circuit that switches the video signal read from the XY memory in conjunction with switching of the address switching circuit and outputs it to each of the readout radars;
The radar scan conversion device is characterized by comprising an output buffer circuit that temporarily stores each output of the output switching circuit.

(Embodiment) FIG. 1 shows a block diagram of an embodiment of the present invention, in which 1 is an A/D conversion circuit, 2 is a sweep correlation circuit, 3 is an input buffer circuit, 4 is an input calculation circuit,
5 is an X-Y memory, 6 is an address switching circuit, 7 is an output switching circuit, 8 is a write address creation circuit, 9
are erase address generation circuits, 10, 11, and 12.
are read address generation circuits, 13, 14 and 15
is an output buffer circuit, 16, 17 and 18 are D/
A conversion circuit, 19 is a timing signal generation circuit,
V ₁ is an input terminal for the write video signal of radar 1 (not shown), V ₂ , V ₃ , and V ₄ are output terminals for the read video signals of radar 2, radar 3, and radar 4 (not shown), and T ₁ , T ₂ , T ₃ , and T ₄ are the input terminals of the trigger signals of radars 1, 2, 3, and 4, respectively, and A ₁ , A ₂ , A ₃ , and A ₄ are the input terminals of the trigger signals of radars 1, 2, 3, and 4, respectively. Antenna angle data input terminals, and C ₁ , C ₂ , C ₃ , and C ₄ are off-center data input terminals for radars 1, 2, 3, and 4, respectively.

The video signal of the radar 1 input from the write video signal input terminal V ₁ in FIG. 1 is sent to the A/D conversion circuit 1. A/D conversion circuit 1 has input terminal V ₁
Quantize the analog video signal from the distance (Δr)
Each time, the signal is converted into a multivalued digital signal, and this digital signal is sent to the sweep correlation circuit 2. The sweep correlation circuit 2 receives the digital signal from the A/D conversion circuit 1, performs so-called sweep correlation processing in which the signals at the same distance for each trigger are added a certain number of times n, and the signal subjected to the sweep correlation processing is added every n triggers. The signal is sent to the input buffer circuit 3 once every.
Here, the number of times n is an integer value within the number of hits of radar 1. The input buffer circuit 3 is composed of a line memory, receives the signal subjected to sweep correlation processing from the sweep correlation circuit 2, stores it in the line memory, and then outputs the signal in the same order as the input, but in a predetermined manner different from the input. The read output is read out at high speed and sent to the input arithmetic circuit 4. The input calculation circuit 4 receives the output of the input buffer circuit 3 and the output from the terminal 1 of the output switching circuit 7, and
It compares the magnitude of the inputs, outputs the larger input, and sends this output to the XY memory 5. The X-Y memory 5 is an X-Y memory (not shown).
It is composed of an array of memory elements and a memory control circuit, and its terminal A receives an address input, its terminal I receives a write input, and its terminal O outputs a read output. The XY memory 5 performs operations such as erasing, writing, and reading in conjunction with the switching operation of the address switching circuit 6. That is, X-Y
When the address switching circuit 6 is connected to the terminal O of the memory 5, the memory contents are erased, and when the address switching circuit 6 is connected to the terminal 1, the input is input from the input calculation circuit 4 to the terminal I of the X-Y memory 5. A signal is stored in an address corresponding to the address data inputted from the address switching circuit 6 to the terminal A, and when the address switching circuit 6 is connected to the terminal 2, 3, or 4, the address switching circuit 6 From X-Y memory 5
The memory contents of the address corresponding to the address data inputted to terminal A of are read out and outputted to terminal O, and this output is sent to output switching circuit 7. Note that the address data output to terminal A is
If the address is outside the storage range of the memory, zero is output from terminal O. The address switching circuit 6 inputs the address input to its terminals 0, 1, 2, 3, and 4.
The data is sequentially switched and output at a predetermined time interval, and the output address and data are
It is sent to terminal A of memory 5. The output switching circuit 7 performs switching operation in conjunction with the address switching circuit 6, and terminals 0, 1, 2, 3, and 4 of the output switching circuit 7
are switched in conjunction with the terminals of the address switching circuit 6 having the same number. The output switching circuit 7 receives the output read from the terminal O of the X-Y memory 5, sequentially switches it to terminals 1, 2, 3 and 4, and outputs it to terminal 1.
The output is sent to the input calculation circuit 4, and the terminals 2, 3,
and 4 are sent to output buffer circuits 13, 14, and 15, respectively.

The write address generation circuit 8 has input terminals T ₁ , A ₁ ,
and C ₁ respectively receive the trigger signal, the antenna angle data, and the off-center data of the radar 1, and quantize each position in the pointing direction of the antenna of the radar 1 at the same speed as the readout speed of the input buffer circuit 3. For each distance (Δr), an address for the X-Y memory 5 is created by converting it into virtual X-Y coordinates in order from distance zero, and this address data is sent to the address conversion circuit 6. and sin θ, cos θ (θ: pointing angle of the antenna of radar 1 with zero in the Y direction and positive in the rotation direction of the antenna)
data is sent to the erase address generation circuit 9. The erase address generation circuit 9 receives the address data and sinθ from the write address generation circuit 8.
cos θ data, an address for the X-Y memory 5 (this address is X' =X+Δd・cosθ,
It is expressed as Y'=Y-Δd·sinθ. Here,
X and Y are addresses input from the write address generation circuit 8. ) and sends this address data to the address switching circuit 6. Read address generation circuits 10, 11, and 12 receive input terminals T ₂ , T ₃ ,
and trigger signal on T ₄ , input terminals A ₂ , A ₃ , and A ₄
antenna angle data, and input terminals C ₂ , C ₃ ,
and received off-center data from C ₄ , Radar 2,
Each position in the pointing direction of the antenna of each of the radars 3 and 4 is converted into X-Y coordinates in order from distance zero for each quantized distance of the same degree as the quantized distance (Δr) described above.
An address for the -Y memory 5 is created, and each address data is sent to the address conversion circuit 6. The output buffer circuits 13, 14, and 15 each consist of two lines of line memories, receive the output of the output switching circuit 7, temporarily store it in one of the two lines of line memories, and The contents stored from the other line memory are transferred to its output buffer circuits 13, 14, and 1.
5 readout radars 2, 3, and 4 are read out for each trigger in the same order as the input and at a predetermined speed (usually the same speed as the actual video), and the readout outputs are sent to the D/A. Conversion circuits 16, 17,
and 18. Note that the two series of line memories are alternately switched at each switching cycle of the output switching circuit 7. Further, the radars from which the stored contents of the output buffer circuits 13, 14 and 15 are read are radar 2, radar 3, and radar 4, respectively. D/A conversion circuit 16, 17,
and 18 are output buffer circuits 13 and 1, respectively.
4 and 15, converts it from a digital signal to an analog signal, generates an analog video signal, and sends this video signal to output terminals V ₂ , V ₃ , and V _4, respectively. The timing signal generation circuit 19 has input terminals T ₁ , T ₂ , T ₃ ,
It receives trigger signals from radars 1, 2, 3, and 4 from T ₄ and creates various timing signals necessary for each circuit and sends them to each circuit.

FIG. 2 shows the positional relationship on the X-Y memory for explaining the operation of the embodiment shown in FIG.
The storage range of the memory 5, Q ₁ , Q ₂ , Q ₃ , and Q ₄ are the positions of radars 1, 2, 3, and 4, respectively, and L ₁ ,
L ₂ , L ₃ , and L ₄ are radars 1, 2, 3, and
and the pointing direction of the 4th antenna at a certain time,
L ₀ indicates a line indicating each erasure position at the same time.

FIG. 3 shows a time relationship for explaining the embodiment of FIG. m in FIG. 3 shows the switching time relationship among the X-Y memory 5, address switching circuit 6, and output switching circuit 7, T is the switching period, T ₀ is the erasing period, and T ₁
is the writing period of the video signal of radar 1, T ₂ , T ₃ ,
and T ₄ indicate the readout period of radars 2, 3, and 4, e is the erasure period, 1a, 1b, and 1c are the trigger signal of radar 1, and the input period of the sweep correlation processed signal to the input buffer circuit 3, respectively. , indicates a period in which the output read from the input buffer circuit 3 is written into the X-Y memory 5 via the input arithmetic circuit 4, and 2a, 3a, and 4a are respectively the radar 2,
3, and 4 trigger signals, 2b, 3b, and 4b
are the reading periods from the XY memory 5 of radars 2, 3, and 4, and 2c, 3c, and 4, respectively.
c indicates the readout period from the output buffer circuits 13, 14, and 15 of the radars 2, 3, and 4, respectively. Note that the hatched portions in 2c, 3c, and 4c indicate that the write signal of the hatched portion in 1b is being read.

Next, the operation of the above embodiment will be explained in Figs. 1 and 2.
This will be explained with reference to FIG. radar 1,
2, 3, and 4 are regular radio waves that emit constant-period pulse radio waves from a horizontally rotating aerial with sharp horizontal directivity, receive reflected signals from targets, detect and amplify them, and generate video signals. This is a search radar.

First, when the address switching circuit 6 is connected to its terminal O (erasure period T ₀ ), a certain small distance (Δd) from each position in the directional direction of the antenna of the radar 1
The stored contents of the memory elements on the XY memory 5 corresponding to the positions separated in the direction in which the pointing angle advances are erased. Then, the rotational speed of the antenna of radar 1, the switching period T, and the switching period T are set such that the time during which the directional line of the antenna of radar 1 crosses the corresponding area of the memory element located at the farthest position from the radar 1 is longer than the switching period T.
By determining the size of the corresponding area of the memory element, etc., as the antenna of the radar 1 rotates, the memory contents written on the memory element during the previous rotation are completely erased.

When the address switching circuit 6 is connected to its terminal 1 (writing period T ₁ ), the stored contents of the memory elements on the X-Y memory 5 corresponding to each position in the direction of the antenna of the radar 1 are read out. It is sent to the input calculation circuit 4 via the output switching circuit 7, where it is compared with the sweep correlation processed video signal of the radar 1 sent from the input buffer circuit 3 at every same distance, and the one with the larger amplitude value is signal is written to that memory element. The reason why the same distances can be compared is that the read speed of the input buffer circuit 3 and the speed of conversion into XY coordinates for each quantization distance of the write address generation circuit 8 are the same. In this manner, as the radar 1 antenna rotates, the memory element of the X-Y memory 5 stores the maximum value of the radar 1 correlated video signal written to that element. Since the signals to be stored are swept and correlated n times during the switching period T as explained above, the S/N is
There is no loss of signal due to extraction once every n triggers.

If the aforementioned small distance (Δd) is selected to be a value slightly larger than the diagonal length of the rectangular area corresponding to the memory element of the It is possible to make almost no blank time (or blank area) occur.

The address switching circuit 6 is connected to its terminal 2, 3, or 4.
(readout period T ₂ , T ₃ , or T ₄ ), the corresponding radar 2, 3, or 4
The stored contents of the memory element corresponding to each position in the pointing direction of the antenna (zero if outside the storage range) are read out and sent to the corresponding output buffer circuit 13, 14, or 15 via the output switching circuit 7. The same line memory contents are read out every time the radar is triggered during the period (equal to the switching period T) from here until the next readout contents are input, and the D/A conversion circuit 16, 17 or 18, the video signal is converted into an analog video signal and outputted from the output terminal V ₂ , V ₃ , or V ₄ . As the rotation of the antenna of radar 2, 3, or 4 progresses, the stored video signal of radar 1 at each position in the pointing direction of the antenna at that time is read out in the correct positional relationship at each switching period T. They are output one after another in a positional relationship that looks like it was directly detected by radar. Here, the antenna of each of the above-mentioned radars is set so that the time for the directional line of the antenna of that radar to cross the corresponding area of the memory element located at the farthest position from the reading radar 2, 3, or 4 is longer than the switching period T. By determining the rotational speed, the switching time T, the size of the corresponding area of the memory element, etc., it becomes possible to read out the contents recorded in the XY memory 5 without omitting them.

In this way, the video signal of radar 1 is converted into the scans (PPI scans) of radars 2, 3, and 4, and are output simultaneously.

As explained above, according to this embodiment, the video signal of radar 1 (writing radar) can be read out according to the scanning of each of the three radars, that is, radars 2, 3, and 4 (reading radar). .

Further, even when erasing video signals temporarily stored in the XY memory, according to this embodiment, almost no blank area is generated due to erasure.

In this embodiment, the X-Y memory addresses are created by converting each position in the direction of the antenna into virtual X-Y coordinates, but the effect is the same even if the reference coordinates are used. In addition, although the storage range of the memory M shown in FIG. 2 is square, it may be circular,
It can also have a shape such as a rectangle.

(Effects of the Invention) As described above, this invention converts each position in the antenna direction of a writing radar and a plurality of reading radars into virtual X-Y coordinates to create an address for an X-Y memory, By switching this address, the video signal of the written radar is stored in the X-Y memory, and the stored contents are read out for each radar and temporarily stored in the buffer circuit, so that each scan can be performed for multiple radars. Accordingly, the video signal of the written radar can be read out, and a scan conversion device has been realized which can read out the same storage contents to multiple radars at the same time.

In addition, in the above scan conversion device, by erasing memory elements corresponding to positions that are separated from each position in the pointing direction of the writing radar's antenna by a certain small distance in the direction in which the pointing angle advances, blank areas due to erasure can be eliminated. This made it possible to make it almost impossible.

Therefore, it is extremely effective when applied to maritime traffic control systems, etc., in which images of one radar are combined with images of a plurality of other radars.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of this invention;
The figure is for explaining the operation of the embodiment shown in FIG.
FIG. 3 is a time relationship diagram for explaining the operation of the embodiment shown in FIG. 1. 1... A/D conversion circuit, 2... sweep correlation circuit,
3...Input buffer circuit, 4...Input calculation circuit, 5...
X-Y memory, 6... Address switching circuit, 7... Output switching circuit, 8... Write address creation circuit, 9... Erase address creation circuit, 10, 11, 12... Read address creation circuit, 13, 14, 15... Output buffer circuit, 16, 17, 18...D/A conversion circuit,
19...Timing signal generation circuit.

Claims (1)

[Claims] 1 Each position in the pointing direction of each antenna of the writing radar and the plurality of reading radars is
an address creation circuit that converts into a Y coordinate and outputs each as a first address for the X-Y memory; an address switching circuit that switches and outputs each of the first addresses in a predetermined order; an input buffer circuit for temporarily storing a video signal; and an input buffer circuit for temporarily storing a video signal from the input buffer circuit according to a first address corresponding to a write radar from the address switching circuit; an X-Y memory that reads and outputs a signal according to a first address corresponding to each reading radar from the address switching circuit; and an X-Y memory that reads and outputs a signal according to a first address corresponding to each reading radar from the address switching circuit; What is claimed is: 1. A radar scan conversion device comprising: an output switching circuit that outputs an output for each read radar; and an output buffer circuit that temporarily stores each output of the output switching circuit.