JPH0513957A - Printed wiring board - Google Patents

Printed wiring board

Info

Publication number
JPH0513957A
JPH0513957A JP16140491A JP16140491A JPH0513957A JP H0513957 A JPH0513957 A JP H0513957A JP 16140491 A JP16140491 A JP 16140491A JP 16140491 A JP16140491 A JP 16140491A JP H0513957 A JPH0513957 A JP H0513957A
Authority
JP
Japan
Prior art keywords
board
groove
printed wiring
wiring board
boards
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16140491A
Other languages
Japanese (ja)
Inventor
Toshihiro Nagai
利弘 長井
Megumi Fujikawa
恵 藤川
Makoto Ota
誠 太田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP16140491A priority Critical patent/JPH0513957A/en
Publication of JPH0513957A publication Critical patent/JPH0513957A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01BCABLES; CONDUCTORS; INSULATORS; SELECTION OF MATERIALS FOR THEIR CONDUCTIVE, INSULATING OR DIELECTRIC PROPERTIES
    • H01B3/00Insulators or insulating bodies characterised by the insulating materials; Selection of materials for their insulating or dielectric properties
    • H01B3/18Insulators or insulating bodies characterised by the insulating materials; Selection of materials for their insulating or dielectric properties mainly consisting of organic substances
    • H01B3/30Insulators or insulating bodies characterised by the insulating materials; Selection of materials for their insulating or dielectric properties mainly consisting of organic substances plastics; resins; waxes
    • H01B3/44Insulators or insulating bodies characterised by the insulating materials; Selection of materials for their insulating or dielectric properties mainly consisting of organic substances plastics; resins; waxes vinyl resins; acrylic resins
    • H01B3/443Insulators or insulating bodies characterised by the insulating materials; Selection of materials for their insulating or dielectric properties mainly consisting of organic substances plastics; resins; waxes vinyl resins; acrylic resins from vinylhalogenides or other halogenoethylenic compounds
    • H01B3/445Insulators or insulating bodies characterised by the insulating materials; Selection of materials for their insulating or dielectric properties mainly consisting of organic substances plastics; resins; waxes vinyl resins; acrylic resins from vinylhalogenides or other halogenoethylenic compounds from vinylfluorides or other fluoroethylenic compounds

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PURPOSE:To enable a printed wiring board to absorb residual stress by a groove so as to be protected against warpage even if the board is subjected to hot pressing by a method wherein a groove is provided to an inner board or an outer board. CONSTITUTION:An inner board 4 of a copper plated laminated board is etched for the formation of a circuit pattern 7, and a groove 11 is formed on the part of the board 4 where a copper foil is not provided. On the other hand, outer boards 2 and 3 formed of insulating boards plated with copper foils are laminated on the inner board 4 through the intermediary of adhesive agents 12 and 13, and the adhesive agents 12 and 13 are cured by hot pressing to form the boards into one piece. The copper foils of the outer boards 2 and 3 are etched into circuit patterns 5 and 6 for the formation of a printed wiring board 1. As mentioned above, as the groove 11 is provided to the inner board 4, residual stress induced by the expansion coefficient difference between the boards 2, 3, and 4 owing to the difference between the copper residues on their surfaces is absorbed by the groove 11, so that the board 1 can be protected against warpage.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明はプリント配線板に関す
るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board.

【0002】[0002]

【従来の技術】図3は従来のプリント配線板の断図面で
ある。図において、1はプリント配線板、2、3はプリ
ント配線板1を構成する外層板、4は外層板2、3間に
挾まれた内層板、5、6は外層板2、3に形成された回
路パターン、7は内層板4に形成された回路パターンで
ある。
2. Description of the Related Art FIG. 3 is a sectional view of a conventional printed wiring board. In the figure, 1 is a printed wiring board, 2 and 3 are outer layer boards constituting the printed wiring board 1, 4 is an inner layer board sandwiched between the outer layer boards 2 and 3, and 5 and 6 are formed on the outer layer boards 2 and 3. The circuit pattern 7 is a circuit pattern formed on the inner layer plate 4.

【0003】上記のプリント配線板1は、次のようにし
て製造される。まずガラス繊維/エポキシ樹脂複合材等
の絶縁基板の両面に銅箔を張った銅張積層板からなる内
層板4にエッチングを行って回路パターン7を形成す
る。そしてその両側に外層板2、3となるプリプレグお
よび銅箔を積層し、加熱プレスにより硬化させて、外層
板2、3を有する銅張多層基板を形成する。その後その
両面の銅箔をエッチングして回路パターン5、6を形成
してプリント配線板1が製造される。
The printed wiring board 1 is manufactured as follows. First, an inner layer plate 4 made of a copper clad laminate in which copper foil is stretched on both sides of an insulating substrate such as a glass fiber / epoxy resin composite material is etched to form a circuit pattern 7. Then, a prepreg and a copper foil to be the outer layer plates 2 and 3 are laminated on both sides thereof and cured by hot pressing to form a copper clad multilayer substrate having the outer layer plates 2 and 3. After that, the copper foils on both sides are etched to form the circuit patterns 5 and 6, and the printed wiring board 1 is manufactured.

【0004】[0004]

【発明が解決しようとする課題】しかるに、上記のよう
な従来のプリント配線板においては、外層板2、3およ
び内層板4の表裏面に形成される回路パターン5、6、
7の銅残存率に差があるため、プリプレグを積層して加
熱プレスする際、膨張係数の差により内部応力が残り、
ソリが発生するという問題点があった。
However, in the conventional printed wiring board as described above, the circuit patterns 5, 6 formed on the front and back surfaces of the outer layer boards 2, 3 and the inner layer board 4, respectively.
Since there is a difference in the copper remaining rate of 7, when laminating prepregs and hot pressing, internal stress remains due to the difference in expansion coefficient,
There was a problem that warpage occurred.

【0005】この発明は上記の問題点を解決するために
なされたもので、加熱プレスを行ってもソリが発生しに
くいプリント配線板を得ることを目的とする。
The present invention has been made in order to solve the above problems, and an object thereof is to obtain a printed wiring board in which warpage is unlikely to occur even when hot pressing is performed.

【0006】[0006]

【課題を解決するための手段】この発明のプリント配線
板は、回路パターンを形成した内層板および外層板を積
層したプリント配線板において、内層板または外層板に
溝を形成したものである。
The printed wiring board according to the present invention is a printed wiring board in which an inner layer board and an outer layer board having circuit patterns are laminated, and grooves are formed in the inner layer board or the outer layer board.

【0007】[0007]

【作用】この発明のプリント配線板は、内層板に回路パ
ターンを形成し、外層板および銅箔と積層して銅張積層
基板とし、これをエッチングして回路パターンを形成す
ることにより製造されるが、積層に際して内層板または
外層板に溝を形成して積層し、加熱プレスにより硬化さ
せて一体化する。
The printed wiring board of the present invention is manufactured by forming a circuit pattern on an inner layer board, laminating it with an outer layer board and a copper foil to form a copper clad laminated board, and etching this to form a circuit pattern. However, when laminating, grooves are formed in the inner layer plate or the outer layer plate, and the layers are laminated and cured by heating and pressing to be integrated.

【0008】内層板および外層板の銅残存率に差がある
場合、加熱プレスすると、膨張係数の差により内部応力
が残るが、溝を形成すると、残留応力は溝に吸収され、
ソリの発生は軽減される。
When there is a difference in copper residual ratio between the inner layer plate and the outer layer plate, internal stress remains due to the difference in expansion coefficient when hot-pressed, but when a groove is formed, the residual stress is absorbed by the groove,
The occurrence of sleds is reduced.

【0009】[0009]

【実施例】以下、この発明の一実施例を図について説明
する。図1は実施例のプリント配線板を示す図2のA−
A断面図、図2は平面図であり、図において、図3と同
一符号は同一または相当部分を示す。11は内層板4に
形成された溝、12、13は外層板2、3と内層板4間
を接合する接着剤である。溝11は幅方向に延びるよう
に複数個設けられている。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the printed wiring board of the embodiment at A- in FIG.
2 is a plan view, and the same reference numerals as those in FIG. 3 indicate the same or corresponding portions. Reference numeral 11 is a groove formed in the inner layer plate 4, and 12 and 13 are adhesives for joining the outer layer plates 2 and 3 and the inner layer plate 4 together. A plurality of grooves 11 are provided so as to extend in the width direction.

【0010】上記のプリント配線板1は、次のようにし
て製造される。まず従来と同様の銅張積層板からなる内
層板4にエッチングを行って回路パターン7を形成し、
回路パターン7のない部分に溝11を形成する。一方絶
縁基板の片面に銅箔を張った外層板2、3を、接着剤1
2、13を介して内層板4に積層し、加熱プレスにより
接着剤12、13を硬化させて一体化する。そして外層
板2、3の銅箔をエッチングして、回路パターン5、6
を形成し、プリント配線板1が製造される。接着剤1
2、13は外層板2、3および内層板4の絶縁基板と同
質のエポキシ系が好ましく、溝11に流れこまない程度
の量を使用する。
The above printed wiring board 1 is manufactured as follows. First, the inner layer plate 4 made of a copper clad laminate similar to the conventional one is etched to form a circuit pattern 7,
Grooves 11 are formed in the portions where the circuit pattern 7 is not present. On the other hand, the outer layer plates 2 and 3 in which a copper foil is stretched on one surface of the insulating substrate are attached to the adhesive 1
It is laminated on the inner layer plate 4 via 2 and 13, and the adhesives 12 and 13 are hardened and integrated by hot pressing. Then, the copper foils of the outer layer plates 2 and 3 are etched to form the circuit patterns 5 and 6.
And the printed wiring board 1 is manufactured. Adhesive 1
2 and 13 are preferably epoxy-based materials of the same quality as the insulating substrates of the outer layer plates 2 and 3 and the inner layer plate 4, and are used in such amounts that they do not flow into the groove 11.

【0011】上記のプリント配線板1においては、内層
板4に溝11が形成されているため、加熱プレスの際、
外層板2、3および内層板4の両面の銅残存率の差に基
づく膨張係数の差による残留応力は、溝11に吸収さ
れ、ソリの発生は軽減される。
In the printed wiring board 1 described above, since the groove 11 is formed in the inner layer board 4, it is
Residual stress due to the difference in expansion coefficient based on the difference in copper residual ratio between the outer layer plates 2 and 3 and the inner layer plate 4 is absorbed by the groove 11 and the occurrence of warpage is reduced.

【0012】なお、上記実施例では、溝11は内層板4
に形成したが、外層板2、3に形成してもよく、また内
層板4が複数枚あるときは、複数の内層板に形成するこ
とができる。また溝11は幅方向に形成したが、長手方
向に形成してもよい。さらに外層板2、3は予め形成し
た場合について説明したが、溝11に充填材を充填した
状態で、従来と同様にプリプレグを積層し、加熱プレス
により一体化して形成してもよい。
In the above embodiment, the groove 11 is formed in the inner layer plate 4
Although it may be formed on the outer layer plates 2 and 3, it may be formed on a plurality of inner layer plates 4 when there are a plurality of inner layer plates 4. Although the groove 11 is formed in the width direction, it may be formed in the longitudinal direction. Further, although the case where the outer layer plates 2 and 3 are formed in advance has been described, the prepreg may be laminated in the state where the groove 11 is filled with the filler as in the conventional case, and may be integrally formed by the heat press.

【0013】[0013]

【発明の効果】この発明によれば、内層板または外層板
に溝を形成したので、加熱プレスを行う場合でも、銅残
存率の差に基づく膨張係数の差により発生する残留応力
が溝に吸収され、ソリの発生が軽減される効果がある。
According to the present invention, since the groove is formed in the inner layer plate or the outer layer plate, the residual stress generated due to the difference in expansion coefficient based on the difference in the copper residual rate is absorbed in the groove even when hot pressing is performed. This is effective in reducing the occurrence of sleds.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例のプリント配線板を示す図2のA−A断
面図。
1 is a cross-sectional view taken along the line AA of FIG. 2 showing a printed wiring board according to an embodiment.

【図2】図1の平面図。FIG. 2 is a plan view of FIG.

【図3】従来のプリント配線板の断面図。FIG. 3 is a cross-sectional view of a conventional printed wiring board.

【符号の説明】[Explanation of symbols]

1 プリント配線板 2、3 外層板 4 内層板 5、6、7 回路パターン 11 溝 12、13 接着剤 1 Printed wiring board 2, 3 Outer layer board 4 Inner layer board 5, 6, 7 Circuit pattern 11 Groove 12, 13 Adhesive

Claims (1)

【特許請求の範囲】 【請求項1】 回路パターンを形成した内層板および外
層板を積層したプリント配線板において、内層板または
外層板に溝を形成して積層したことを特徴とするプリン
ト配線板。
Claim: What is claimed is: 1. A printed wiring board in which an inner layer board and an outer layer board each having a circuit pattern are laminated, wherein a groove is formed in the inner layer board or the outer layer board to laminate the printed wiring board. .
JP16140491A 1991-07-02 1991-07-02 Printed wiring board Pending JPH0513957A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16140491A JPH0513957A (en) 1991-07-02 1991-07-02 Printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16140491A JPH0513957A (en) 1991-07-02 1991-07-02 Printed wiring board

Publications (1)

Publication Number Publication Date
JPH0513957A true JPH0513957A (en) 1993-01-22

Family

ID=15734448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16140491A Pending JPH0513957A (en) 1991-07-02 1991-07-02 Printed wiring board

Country Status (1)

Country Link
JP (1) JPH0513957A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011517063A (en) * 2008-03-31 2011-05-26 巨擘科技股▲ふん▼有限公司 Method for balancing stress of multilayer substrate and multilayer substrate

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011517063A (en) * 2008-03-31 2011-05-26 巨擘科技股▲ふん▼有限公司 Method for balancing stress of multilayer substrate and multilayer substrate

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