JPH0513757A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To improve withstand voltage against an electrostatic pulse from the outside of an integrated circuit applied from an output pad with a more reduced integrated circuit layout area. CONSTITUTION:A gate electrode and a drain electrode of a protective field transistor TFN is connected with a pad P to which an electrostatic pulse which generates excessive voltage might be applied. A source electrode of the protective field transistor TFN is connected with a ground VSS. Once the electrostatic pulse is applied to the pad P, the connection between a drain electrode and a source electrode of a protective field transistor TFN becomes to the on-state owing to voltage applied to the gate electrode of the protective field transistor applied by said electrostatic pulse, and the electrostatic pulse applied from the output pad is released to the ground side. Thus, the output buffer circuit and other internal circuits are protected from the electrostatic pulse.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit provided between an internal circuit of an integrated circuit and an output pad connected to the outside of the integrated circuit, and more particularly to an output buffer circuit applied from the output pad. Withstands electrostatic discharge from outside the integrated circuit (electrostatic discharge breakdown voltage, hereinafter ES
(Referred to as D breakdown voltage).

[0002]

2. Description of the Related Art MOS (metal oxide semiconductor)
In an integrated circuit such as a mold, the input / output circuit of the integrated circuit connected to the input / output pin may be destroyed by an electrostatic pulse or the like applied from the input / output pin on the package of the integrated circuit. is there.

Therefore, conventionally, there has been disclosed a technique of protecting an input / output circuit of an integrated circuit from destruction due to an electrostatic pulse or the like which generates an excessive voltage applied from the outside of the integrated circuit, that is, electrostatic breakdown. There is. Hereinafter, such a technique is referred to as electrostatic protection.

For example, in Japanese Examined Patent Publication No. 2-36071, in an input protection structure for an integrated circuit device connected to a bonding pad forming an external electrical connection, a well portion having a reduced doping level is used to remove the semiconductor substrate from the semiconductor substrate. A source region and a drain region that include separate and enhanced doping level internal portions, one of these regions being connected to the bonding pad and the other region being connected to a reference voltage path; The surface area between the two regions is covered with a layer of insulating material of substantially uniform thickness corresponding to the thickness of the field oxide, and the insulating material of uniform thickness between the two regions. Disclosed is a technique relating to an input protection structure including the bonding pad provided on a layer and a conductive path electrically connecting an internal circuit. There.

The input protection structure of JP-B-2-36071 is a so-called field transistor, which is connected to a bonding pad and, when an electrostatic pulse is applied to a conductive path forming a gate electrode, the bonding is performed. An ON state is established between the source region and the drain region connected to the pad or the reference voltage path.
The electrostatic pulse applied to the bonding pad can be released to the reference voltage path to protect the internal circuit of the integrated circuit device from electrostatic breakdown.

FIG. 7 is a circuit diagram of a conventional output buffer circuit protected by static electricity.

In FIG. 7, an output signal from the internal circuit is output to pad P via an output buffer circuit formed of P channel MOS transistor TP and N channel MOS transistor TN.

In this output buffer circuit, a diode D1 having an anode connected to the power supply VDD and a cathode connected to the pad P is provided at the drain portion of the P-channel MOS transistor TP, and a drain portion of the N-channel MOS transistor TN. Has a diode D2 whose anode is connected to the pad P and whose cathode is connected to the ground VSS.
Exists respectively. These diodes D1 and D2
Have a role of preventing destruction of the output buffer due to an electrostatic pulse applied from the pad P from the outside of the integrated circuit.

These diodes D1 or D2 are
When a voltage higher than a normal voltage such as a power supply voltage normally applied between the power supply VDD and the ground VSS is applied to the pad P, the anode and the cathode are turned on, whereby the pad P and the power supply VDD are connected. Of the P-channel MOS transistor T by preventing an excessive potential difference between the pad P and the ground VSS.
Damage to the P and N channel MOS transistors TN and internal circuits due to excessive voltage is prevented.

[0010]

However, the technique disclosed in Japanese Patent Publication No. 2-36071 described above is an input protection structure of an integrated circuit device and improves the electrostatic breakdown voltage of an output buffer circuit. is not.

Further, in the conventional output buffer circuit protected by electrostatic discharge described above with reference to FIG. 7, it is necessary to increase the drain of the output buffer in order to obtain a sufficient ESD withstand voltage. There is a problem that it becomes wider.

Therefore, in order to further improve the ESD withstand voltage, the drain area of the output buffer must be further increased, or a diode having the same function as the diodes D1 and D2 must be newly formed and connected in parallel. Therefore, there is a problem that the integrated circuit layout area is increased.

The present invention has been made to solve the above-mentioned conventional problems, and provides an output buffer circuit provided between an internal circuit of an integrated circuit and an output pad connected to the outside of the integrated circuit. It is an object of the present invention to provide an output buffer circuit capable of improving the breakdown voltage against an electrostatic pulse applied from the output pad from the outside with a smaller integrated circuit layout area.

[0014]

According to the present invention, in an output buffer circuit provided between an internal circuit of an integrated circuit and an output pad connected to the outside of the integrated circuit, a gate electrode and a drain electrode are provided as described above. Provided with a protective field transistor connected to the conductive path to the output pad, the source electrode of which is connected to the ground side, the electrostatic pulse applied from the output pad is released to the ground side by the protective field transistor, The above problems have been achieved by improving the electrostatic breakdown voltage.

[0015]

According to the present invention, in order to improve the ESD breakdown voltage of the output buffer circuit, a protective field transistor capable of effectively improving the ESD breakdown voltage with a smaller integrated circuit layout area is used.

In this protective field transistor, the gate electrode and the drain electrode are connected to a conductive path to an output pad to which an electrostatic pulse may be applied. The source electrode of this protective field transistor is connected to the ground side.

Therefore, according to the present invention, when an electrostatic pulse is applied to the output pad, a voltage is applied to the gate electrode for turning on the drain electrode and the source electrode. , Between the drain electrode and the source electrode is turned on, the electrostatic pulse applied to the output pad can be released to the ground side, and the output buffer circuit and other circuits inside the integrated circuit are electrostatically charged. It is possible to protect from excessive voltage due to pulses.

The protective field transistor used in the present invention must have the following characteristics, but the present invention limits the specific structure of this protective field transistor. is not.

The state between the drain electrode and the source electrode is turned on. The voltage applied to the gate electrode must be higher than the normal voltage such as the power supply voltage used for the target integrated circuit. The electrostatic pulse applied from the output pad is released to the ground side without damaging the protective field transistor itself or other circuits,
Be sure to provide electrostatic protection.

An example of the structure of the protective field transistor having such characteristics is shown in FIG.
Will be described later.

[0021]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a circuit diagram of an output buffer circuit according to an embodiment of the present invention.

In FIG. 1, reference numerals TP, TN, D
1, D2, VDD, VSS and P are the same as those having the same reference numerals in FIG.

In the output buffer circuit of FIG. 1,
A protective field transistor TFN is used together with the protective diodes D1 and D2.

This protective field transistor TFN
Has a gate electrode and a drain electrode connected to a conductive path to the output pad P, and a source electrode connected to the ground VSS.

Further, this protective field transistor T
When a predetermined voltage higher than a normal voltage such as a power supply voltage applied between the power supply VDD and the ground VSS is applied to the gate electrode of the FN, the drain electrode and the source electrode are turned on. It is a thing.

FIG. 2 is a sectional view of a protective field transistor used in this embodiment.

In FIG. 2, the protective field transistor has a gate electrode 30, a drain electrode 32, and a source electrode 34.

The drain electrode 32 is connected to the n ⁺ drain 14 formed on the n well 16 formed on the P-type substrate 10.

The source electrode 34 is connected to the n ⁺ source 12 formed on the P-type substrate 10.

Also, these n well 16 and n ⁺ source 12
A channel stop 18 is formed between and.

The gate electrode 30 is provided above the position of the channel stop 18 and the like via the interlayer insulating film 22 and the field oxide film 24.

The gate electrode 30 and the drain electrode 32 of the protective field transistor described above are the pad P described above with reference to FIG. 1 by the aluminum wiring layer 20b.
It is connected to the. The source electrode of this protective field transistor is connected to the ground VSS described above with reference to FIG. 1 by the aluminum wiring layer 20a.

Reference numeral 26 is a passivation film.

In the protective field transistor shown in FIG. 2, the n well 16 improves the breakdown withstand voltage of the n ⁺ drain 14 of the protective field transistor.

As described above, according to this embodiment, the protection field transistor is effectively used, and the ESD withstand voltage of the output buffer circuit itself or other internal circuits is prevented from the electrostatic pulse applied from the output pad. Can be improved. Further, according to the present embodiment, compared with the case where the ESD withstand voltage of the output buffer circuit is improved by using only the conventional protection diode, if the degree of improvement of the ESD withstand voltage is the same, the integrated circuit layout area is reduced. be able to.

With respect to the ESD withstand voltage of this embodiment, an ESD withstand voltage test with a machine model as shown in FIG. 3 and an ESD withstand voltage test with a human body model as shown in FIG. 4 are performed.

In FIG. 3, in the ESD withstand test using a ground-based machine model, the VDD terminal of the integrated circuit 50 is opened, the VSS terminal is connected to the ground, and the changeover switch 52 is turned on with the c terminal and the b terminal turned on. After the test voltage V is applied to the capacitor C so that the terminal C and the terminal a are turned on, the output terminal O of the integrated circuit 50 is switched to the capacitor C. It is to add stored static electricity.

In the ESD withstand voltage test of the machine model based on the power source, the VSS terminal of the integrated circuit 50 is opened,
The same test is performed by connecting the VDD terminal to the ground.

In FIG. 4, the ESD withstand test of the human body model is almost the same as the ESD withstand test of the machine model of FIG. 3 described above regardless of whether it is ground reference or power supply reference. The difference is that the capacitance is small and the resistance R (1.5 kΩ) is used.

According to the ESD withstand voltage test using the machine model described above, the present embodiment can improve the ESD withstand voltage by about 100 V as compared with the conventional example described with reference to FIG.

Also, in the ESD withstand voltage test using the human body model described above, it has been confirmed that the present embodiment improves the ESD withstand voltage by about 500 V as compared with the conventional example described with reference to FIG. ..

FIG. 5 shows the ESD by the machine model ESD withstand voltage test in the conventional example described above with reference to FIG.
It is a graph of frequency distribution of breakdown voltage.

On the other hand, FIG. 6 is a graph of the frequency distribution of the ESD withstand voltage by the machine model ESD withstand voltage test in this embodiment.

As is clear from the comparison between FIG. 5 and FIG. 6, according to this embodiment, the ESD withstand voltage can be improved.

[0046]

As described above, according to the present invention, in the output buffer circuit provided between the internal circuit of the integrated circuit and the output pad connected to the outside of the integrated circuit, less integrated circuits are provided. With the layout area, it is possible to obtain an excellent effect that the withstand voltage against an electrostatic pulse applied from the outside of the integrated circuit applied from the output pad can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an output buffer circuit according to an embodiment of the present invention.

FIG. 2 is a sectional view of a protective field transistor used in the above embodiment.

FIG. 3 is a connection diagram of an ESD withstand voltage test in a machine model.

FIG. 4 is a connection diagram of an ESD withstand voltage test on a human body model.

FIG. 5 is a graph of a frequency distribution of an ESD withstand voltage test of a conventional output buffer circuit protected by electrostatic discharge.

FIG. 6 is a graph showing the frequency distribution of the ESD withstand voltage test of this example.

FIG. 7 is a circuit diagram of a conventional output buffer circuit provided with electrostatic protection.

[Explanation of symbols]

10 ... P-type substrate, 12 ... N ⁺ source, 14 ... N ⁺ drain, 16 ... N well, 18 ... Channel stop, 20a, 20b ... Aluminum wiring layer, 22 ... Interlayer insulating film, 24 ... Field oxide film, 26 ... Passivation film, 30 ... Gate electrode, 32 ... Drain electrode, 34 ... Source electrode, 50 ... Integrated circuit, 52 ... Changeover switch, TP ... P-channel MOS transistor, TN ... N-channel MOS transistor, D1, D2 ... Protective diode, TFN Protective field transistor, P ... Pad, VDD ... Power supply, VSS ... Ground terminal, C1, C2 ... Capacitor (for ESD withstand voltage test), R ... Resistor (for ESD withstand voltage test).

Claims (1)

Claim: What is claimed is: 1. An output buffer circuit provided between an internal circuit of an integrated circuit and an output pad connected to the outside of the integrated circuit, wherein a gate electrode and a drain electrode are the output pad. The protective field transistor is connected to the conductive path to the ground and the source electrode is connected to the ground side, and the electrostatic pulse applied from the output pad is released to the ground side by the protective field transistor, An output buffer circuit having improved breakdown voltage.