JPH0513578A - Logical cell arrangement - Google Patents

Abstract

PURPOSE:To obtain high quality arrangement result and floor plan result which conforms to the requested signal transfer time and satisfies a plurality of objects. CONSTITUTION:A wiring length of each net is forecasted on the basis of the largest rectangular consisting of cells connected to such net. It is evaluated in what degree fine movement of cell or cell group gives influence on signal transfer time of net or on signal transfer time of path (steps S2 to S4). A candidate cell for movement is selected from the probability by obtaining easiness of selection of the candidate cell for movement which is effective to shorten the signal transfer time (steps S5, S6). The moving position of cell is determined and the cell is fine-moved to this position (step S7). Therefore, a signal transfer time of path can be shortened and it can be combined easily with the improvement for the other object on the occasion of automatic arrangement.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of arranging logic cells or cell groups when designing a layout of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Semiconductor integrated circuits (hereinafter referred to as LSI)
Typically has a configuration as shown in FIG. Input / output logic cells (hereinafter abbreviated as cells) on the periphery of the chip 1
Are arranged side by side, and inside the chip, cells 3 for realizing desired functions and wirings 5 connecting the cells are formed. The cell 3 in the chip has a logic gate (inverter, NAND gate, etc.) and a storage element (flip-flop).

On the other hand, the designing stage of an LSI comprises the steps S11 to S15 as shown in FIG. Further, the layout design S13 is a floor plan for determining the face of the chip, automatic placement for determining the placement position of the cell on the chip,
It is composed of automatic wiring for determining a wiring route between cells having a connection relationship.

In the layout design of an LSI, it is important to minimize the chip area and shorten the processing time, and as the LSI becomes finer, the layout design that guarantees the operation performance of the chip is important. This is because the propagation delay of the signal becomes extremely large as the size of the element forming the LSI becomes smaller and the width of the wiring connecting the elements becomes narrower, and the deterioration of the operating performance due to the delay cannot be ignored.

A typical problem in which signal propagation delay is a problem is between flip-flops (especially between flip-flops and input / output elements, or between flip-flops designed to propagate signals during one clock cycle). Between input and output elements). As shown in FIG. 8, a chain of nets connecting the cells between the flip-flops 7 and the cells is called a path route (hereinafter abbreviated as a path).

In order to suppress the signal propagation delay, it is necessary to satisfy the signal propagation time specifications (timing specifications) when deciding the layout positions of cells and cell groups in the automatic layout and floor plan in the layout design of LSI. It becomes important to

The signal propagation time is calculated as follows in the case of a single-stage logic gate as shown in FIG. In Figure 9, Ro is the output gate resistance, C _L is the wiring capacitance, Ci is the input gate capacitance.

(Signal propagation time) = ((input gate capacitance) +
(Wiring capacitance) ・ (Output gate resistance) In the case of multiple stages, (signal propagation time) = (Σ (input gate capacitance) + Σ (wiring capacitance)) ・ (output gate resistance) About the nets that connect to the constituent nets About the cells.

At this time, in order to determine the signal propagation time of the path, not only the cells constituting the path (thick line in FIG. 10) but also
All cells connected to the nets that make up the path (Fig. 10
(Thin line) is involved. For this reason, it is necessary to add the input capacitance of these cells to the input gate capacitance, and the wiring capacitance also needs to be estimated in consideration of the arrangement position of these cells.

The net wiring capacity is (net wiring capacity) = (capacity per unit length).
(Wiring length)

At the time of automatic placement / floor plan, the wiring length in the above formula needs to be estimated from the cell position.
The estimation method includes the maximum rectangle method (FIG. 11A), the source-sink method (FIG. 11B), and the complete graph method (FIG. 11).
(C)) etc.

In the maximum rectangle method (a), half of the perimeter of the maximum rectangle of the cells 11 forming the net 9 (thick line in the figure) is used as the predicted wiring length of the net 9.
In the source-sink method of (b), the cells 11 forming the net are
Source cell 11a and sink cell 1 of a and 11b
The total of the straight line distances to 1b is used as the predicted wiring length of the net. In the complete graph method of (c), the sum of squares of the straight line distances of all the branches of the complete graph connecting the cells 11 forming the net is used as the predicted wiring length of the net.

Of these, the maximum rectangle method is said to have good properties as a method for estimating the wiring length (Jackson,
M., Srinivasan, A., and Kuh, E., ”A Fast Algorithm for
Preformance-Driven Placement ", Proc.ICCAD90., IEEE,
pp.328-331, 1990). Conventionally, the following methods have been used to reduce the signal propagation delay. One is weighting for the net, and the other is to limit the path length.

In the weighting method for nets, a slack value (requested signal arrival time-predicted arrival time) is calculated for each net forming a path, and the net is weighted according to this slack value. It is something that goes (Burste
in, M., and Youssef, M., "Timing Influenced Layout Des
ign ", Proc.22nd Design Automation Conf., IEEE, pp.124
-130,1985). This method has the advantage that it can be easily applied to the conventional automatic placement because the unit of constraint is the net wiring length, but there is no guarantee that the required signal arrival time will be guaranteed.

Another method is to limit the path length according to the arrival time required for the path.
However, this method does not use the maximum rectangle method to estimate the net length to make the problem easier to handle (Prasitjutrakul, S., and Kubitz, WJ, "Path _De
lay Constrained Floorplanning: A Mathematical Progr
amming Approach for Initial Placement ", 26th ACM / IE
EE Design Automation Conf., Pp.364-369,1989). Therefore, the signal arrival time could not be accurately predicted. Further, in this method, since the problem formulation is complicated, the solution takes too much time, and the purpose other than satisfying the timing specifications (minimization of total wiring length, uniform cell density,
Difficult to use with improved processing of cell pin distribution uniformity (Jackson, M., and Kuh, E., "Performance
-Driven Placement of cell BasedIC's ", 26th ACM / IEEE
Design Automation Conf., Pp.364-369,1989. Jackson,
M., Srinivasan, A., and Kuh, E., "A Fast Algorithm for
Performance-Driven Placement ", Proc.ICCAD90., IEEE, p
p.328-331, 1990).

[0016]

As described above, in the conventional layout design, the required signal transmission time cannot be kept, and the maximum wiring method is not used, so that the wiring length of the net cannot be accurately predicted. Also, there was a problem that the solution took time.

The present invention has been made in view of such conventional circumstances, and an object thereof is to estimate the signal transmission time accurately by estimating the wiring length of the net by using the maximum rectangle method. It is an object of the present invention to provide a logic cell placement method capable of predictably satisfying a required signal transmission time and simultaneously satisfying a plurality of other purposes.

[0018]

In order to achieve the above object, the present invention relates to a wiring of a net which connects between logic cells or between cell groups consisting of a plurality of logic cells when designing a layout of a semiconductor integrated circuit. The length is predicted based on the maximum rectangle obtained from the arrangement position of the logic cells that form this net, the signal transmission time of this net is predicted from the wiring length of the predicted net, and from the signal transmission time of the predicted net, When the signal transmission time of a path route consisting of a chain of multiple nets is predicted and the placement position of each logic cell or cell group is slightly moved, the net formed by this logic cell or cell group changes. This logic cell or cell when the signal transmission time is calculated and it is assumed that the arrangement position of each logic cell or cell group has moved slightly. The changed signal transmission time of the path route formed by the loop is obtained, and the placement position is set to shorten the signal transmission time of the path route from the obtained changed signal transmission time of the net and the changed signal transmission time of the path route. Of the logical cell or cell group to be moved, the logical cell or cell group is stochastically selected using the calculated ease of selection, and the placement position of the selected logical cell or cell group is calculated. It is configured to move slightly.

[0019]

With the above structure, the present invention predicts the wiring length of each net based on the maximum rectangle obtained from the arrangement position of the cells or cell groups that form the net, thereby determining the signal propagation time of the path. Accurately predict. Assuming that a cell or cell group has moved slightly, how much the net signal propagation time changes and how much the path signal propagation time changes will be obtained. From this result, the ease of selecting a moving candidate cell that is highly effective in shortening the signal propagation time is calculated.

The movement candidate cells are stochastically selected by using the calculated ease of selection, and the selected movement candidate cells are slightly moved to the same position to be determined.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a flow chart showing the processing procedure of an embodiment relating to the logic cell placement method of the present invention. In the figure,
If you rewrite the word "cell" to a cell group,
Can be applied for floor plans.

The initial placement (step S1) initially gives the placement position of each cell, and generally the cells are often arranged randomly. Next, when it is assumed that one cell is slightly moved, an evaluation value (changed signal transmission time) of how much the signal transmission time of the net configured by this cell changes is obtained for each cell ( Step S2). At this time, the wiring length of the net is predicted in advance by using the maximum rectangle method, and the signal transmission time of the net is predicted.

(Signal transmission time of a certain net) = (capacity per unit length) · (wiring length) · (output resistance)

[0024]

[Outer 1]

Is calculated. The above equation represents the change amount of the signal transmission time due to the minute movement amount. This data is stored for each net, and f is stored in the program.
You can call by (net ID).

On the other hand, the signal propagation time of the path is (signal propagation time) = (Σ (input gate capacitance) + Σ (wiring capacitance)) · (output gate resistance) based on the predicted net wiring length. A net that connects to a net that forms a path is obtained for a cell (step S3).

When this is expressed by the above f (net ID), the term of the input gate capacitance is regarded as a constant, and can be expressed as (signal propagation time) = constant + Σf (wiring length) for the net that constitutes the path.

Next, when it is assumed that one cell slightly moves, an evaluation value of how much the signal propagation time of the entire path changes is obtained (step S4). This evaluation value is
Obtain for each cell that constitutes the path. Since the cell that constitutes the path is the only source (cell that supplies a signal) of the net that constitutes the path, this information is also possessed for each net. The basic idea is as follows.

For simplification, as shown in FIG. 2, each of the nets 1 to 3 forming the path is a two-terminal net consisting of only cells 1 to 4 forming the path. Also, the change in the signal propagation time of the net i per unit movement of the cell (f (i) above)
Is 1. In FIG. 2, even if the cell 2 slightly moves to the left or right by α, it does not affect the signal propagation time of the entire path.

[0030]

[Outside 2]

However, if the cell 3 slightly moves, (net 2 length ± α) + (net 3 length ± α) = net 2 length + net 3 length ± 2α Affect.

That is, cells i-1 and 1 immediately preceding cell i
When the next cell i + 1 is in the same direction toward the cell i (relationship between the cells 2, 3 and 4 in FIG. 2), moving the cell i is highly effective in shortening the signal propagation time of the path. The effect is low when the cell i is on the other side (relationship between cells 1, 2, and 3).

In general, by moving cell i,
The change in the signal propagation time of the path is

[0034]

[Outside 3]

It can be obtained by However, x _i is the position of cell i. The signal propagation time obtained in this way can be called by g (net ID) as data for net i whose source is cell i.

Next, the easiness of selecting the movement candidate cell is calculated (step S5). Evaluation value f of how much the signal transmission time of each net changes when each cell slightly moves
The following is calculated from (net ID) and an evaluation value g (net ID) of how much the signal propagation time of the entire path changes when each cell slightly moves.

(Ease of selection of cell c) = (f (cell c
Connected net i) + g (net i connected to cell c)) × (distance between center of net i and cell c) However, as shown in FIG. And the midpoint of cell i + 1. Also, cell c
The easiness of being selected is calculated separately in the x-direction and the y-direction, and then both are added.

Since the cell c may be included in a plurality of paths, the easiness of cell selection can be obtained by adding weights to the slack values (margins) of the paths and adding them together. This facilitates selection of cells included in the path having the smallest slack value.

For example, in the case of a cell (marked with a circle in the figure) connected to the net 2 arranged in the maximum rectangle T2 of the net 2 in FIG. 4, the contour lines of ease of selection are as shown in FIG. When the center of the net 2 to the origin, the partial eclipse into four parts (a) ~ (d) as shown in FIG. 5, the curve drawn each contour, (a) (1 + 2 ) x 2 + y 2 = 3x ² + y ² = constant (b) x ² + y ² = x ² + y ² = constant (c) x ² + (1 + 2) y ² = x ² + 3 y ² = constant (d) (1 + 2) x ² + ( 1 + 2) y ² = 3x ² + 3y ² = constant

The selection of the movement candidate cells is based on the ease of selection calculated in step S5, and the probability that the most easily selected cell (the cell located on the outermost contour line) is selected is normalized to 1. Then, a moving candidate cell is randomly selected, a random number in the [0, 1] section is generated, and if the random number is smaller than the ease of selection of the cell, the cell is moved, and if it is large, the cell is randomly reselected. By repeating such processing, the movement candidate cell is selected (step S6). The cells are randomly selected in order to eliminate bias in the selected cells.

After that, the moving position is calculated by moving a small distance toward the center of the net connecting the selected cells (step S7). The end condition is until the slack value of each path becomes sufficiently large, and steps S3 to S8 are repeated until this condition is satisfied.

[0042]

As described above, according to the logic cell placement method of the present invention, the wiring length of each net is predicted by using the maximum rectangle method, so that the signal propagation time of the path can be predicted accurately. You can This makes it possible to arrange logic cells that meet the timing specifications. Further, by probabilistically selecting a movement candidate cell and then determining the movement position, it becomes easy to use it in combination with an improvement process for a purpose other than the timing specification.

[Brief description of drawings]

FIG. 1 is a flowchart for explaining a processing procedure of an embodiment of the present invention.

FIG. 2 is a schematic diagram for explaining an influence on a signal propagation time of a path when a cell slightly moves.

FIG. 3 is a schematic diagram for explaining the center of a net.

FIG. 4 is a schematic diagram showing a maximum rectangle of a net and cells connected to the net.

FIG. 5 is a contour line graph showing the ease of selecting cells by contour lines.

FIG. 6 is a configuration diagram of a typical LSI.

FIG. 7 is a flowchart showing an LSI design process.

FIG. 8 is a circuit diagram showing paths between flip-flops.

FIG. 9 is a circuit diagram for explaining a signal propagation time in the case of a general logic gate.

FIG. 10 is a circuit diagram for explaining the signal propagation time of the entire path.

FIG. 11 is a simplified diagram for explaining a method for estimating a wiring length of a net.

Claims (1)

Claim: What is claimed is: 1. When designing a layout of a semiconductor integrated circuit, the wiring length of a net that connects between logic cells or between cell groups consisting of a plurality of logic cells is defined as the logic that constitutes this net. Predict based on the maximum rectangle obtained from the cell placement position, predict the signal transmission time of this net from the predicted wiring length of the net, and from the predicted signal transmission time of the net, a path route consisting of a chain of multiple nets Signal transmission time of each logic cell or cell group, and assuming that the arrangement position of each logic cell or cell group has moved slightly, the changed signal transmission time of the net formed by this logic cell or cell group is calculated. Alternatively, assuming that the placement position of the cell group has moved slightly, the path path formed by this logical cell or cell group The changed signal transmission time of is determined, and from the obtained changed signal transmission time of the net and the changed signal transmission time of the path route, the logical cell whose placement position is to be moved in order to shorten the signal transmission time of the path route or The feature is that the ease of selecting a cell group is calculated, a logical cell or cell group is stochastically selected using the calculated ease of selection, and the placement position of the selected logical cell or cell group is finely moved. Logic cell placement method.