JPH05129891A - Digital filter - Google Patents

Abstract

PURPOSE:To eliminate the need for at least one of a digital multiplier and a digital adder in the digital filter. CONSTITUTION:The filter is provided with a memory 4 storing the result of arithmetic operation to data D0, D1 and a coefficient selected by a coefficient selection input S and a memory 5 storing the result of arithmetic operation to data D2, D3 and a coefficient selected by the coefficient selection input S, and the data D0, D1 and the coefficient selected by the coefficient selection input S are given to the memory 4 as its address and the data D2, D3 and the coefficient selected by the coefficient selection input S are given to the memory 5 as its address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter suitable for processing high speed signals such as magnetic recording / reproducing signals and video signals.

[0002]

2. Description of the Related Art Conventionally, in order to process a high-speed signal such as a magnetic recording / reproducing signal or a video signal, a digital FIR filter, that is, a digital interpolation filter capable of switching tap coefficients for each sample for calculation is used.
FIG. 6 shows a configuration example of such a conventional 4-tap FIR filter. Four tap delay lines 1 to 4 are provided in cascade connection. The tap delay line 1 delays the 5-bit input data D0 by one clock, and the tap delay line 2 is output by the tap delay line 1. The data D1 is delayed by one clock, and the tap delay line 3 delays the data D2 output by the tap delay line 2 by one clock and outputs the data D3. The coefficient memories 12, 13, 14 and 15 are
It stores 32 different multiplication coefficients, and outputs the multiplication coefficient selected by the 5-bit coefficient selection signal S.

The data D0, D1, D2 and D3 are the multiplication coefficients output from the coefficient memories 12, 13 and 14 according to the coefficient selection signal S and the digital multipliers 21, 22 and 2.
Multiplied by 3 and 24. The outputs of the multipliers 21 and 22 are added by the digital adder 31, the output of the adder 31 and the output of the multiplier 23 are added by the digital adder 32, and the output of the adder 32 and the multiplier 24 are added.
And the output of are added by the digital adder 33.
The output of the adder 33 becomes an 8-bit interpolation output.

[0004]

In the above-mentioned conventional example, four digital multipliers and three digital adders are required.

Japanese Unexamined Patent Publication (Kokai) No. Hei 2-171016 discloses a technique for reducing the number of required multipliers by using multiple multipliers, but still a multiplier and an adder are required.

Further, Japanese Patent Laid-Open No. 2-73781 discloses that
A technique for reducing the number of multipliers by utilizing the symmetry of multiplication coefficients is disclosed, but a multiplier and an adder are still necessary.

The digital multiplier and the digital adder have problems that they are large in size and consume large power.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a digital filter which does not require the use of at least one of a digital multiplier and a digital adder.

[0009]

According to a first aspect of the present invention, there is provided a digital filter which calculates an operation result for input data (for example, data D0, D1, D2 and D3 of the embodiment and coefficients selected by a coefficient selection input S). It is characterized by including a stored memory (for example, the memory 4 or 5 of the embodiment of FIG. 1 or the memory 10 of the embodiment of FIG. 5) and supplying input data as an address of the memory.

The digital filter according to claim 2 is
The input data (for example, the data D0 in the embodiment) has a predetermined number of delay elements (for example, tap delay lines 1, 2, and 3 in the embodiment) that are cascaded to delay each by a predetermined time. A first multiplication result, which is a result of multiplication with the coefficient selected by the coefficient selection signal, and a predetermined delay element of the predetermined number of delay elements (for example,
A digital filter having a function of adding an output of the tap delay line 1) of the embodiment and a second multiplication result which is a multiplication result of a coefficient selected by a coefficient selection signal, the first multiplication result and the second multiplication A memory (for example, the memory 4 in the embodiment of FIG. 1) for storing the addition result and the addition result is provided, and the input data, the output of the predetermined delay element and the coefficient selection signal are supplied to the memory as an address signal. And

The digital filter according to claim 3 is
It has a plurality of delay elements (for example, tap delay lines 1, 2, and 3 of the embodiment) connected in cascade that delay input data (for example, the data D0 of the embodiment) by a predetermined time, respectively. A third multiplication result which is a multiplication result of the output of the first delay element (for example, the tap delay line 2 of the embodiment) and the coefficient selected by the coefficient selection signal, and the second delay of the plurality of delay elements. A digital filter having a function of adding the output of an element (for example, the tap delay line 3 of the embodiment) and a fourth multiplication result which is a multiplication result of the coefficient selected by the coefficient selection signal, the third multiplication result A memory (for example, the memory 5 of the embodiment of FIG. 1) for storing the addition result of the first and second multiplication results, and stores the outputs of the first and second delay elements and the coefficient selection signal. And supplying the address signal.

The digital filter according to claim 4 is
It has a plurality of cascaded delay elements (for example, tap delay lines 1, 2, and 3 of the embodiment) that delay input data (for example, the data D0 of the embodiment) by a predetermined time, respectively. A digital filter having a function of performing a predetermined operation on a multiplication result of each output of a delay element and a coefficient selected by a coefficient selection signal, and a memory for storing a result of the predetermined operation (for example, as shown in FIG. 5 memory 10) of the embodiment,
It is characterized in that the input data, the respective outputs of the plurality of delay elements and the coefficient selection signal are supplied to the memory as address signals.

[0013]

According to the digital filter of the present invention, when the input data is supplied to the memory as an address,
Since the operation result for the input data is output from the memory, if the operation result is a multiplication result, a digital multiplier is used. If the operation result is an addition result, a digital adder is used, and the operation result is a multiplication result and an addition result. If both are included, both the digital multiplier and the digital adder can be omitted. Therefore, a compact digital filter with low power consumption can be configured.

According to another aspect of the digital filter of the present invention, when the input data, the output of the predetermined delay element and the coefficient selection signal are supplied to the memory as an address signal, the memory outputs the first multiplication result and the second multiplication result. Since the addition result is output, two digital multipliers and one digital adder can be eliminated. Therefore, a compact digital filter with low power consumption can be configured.

According to another aspect of the digital filter of the present invention, when the outputs of the first and second delay elements and the coefficient selection signal are supplied to the memory as address signals, the third multiplication result and the fourth multiplication result are added from the memory. Since the result is output, both two digital multipliers and one digital adder can be eliminated. Therefore, a compact digital filter with low power consumption can be configured.

In the digital filter having the structure of the fourth aspect, when the input data, the respective outputs of the plurality of delay elements and the coefficient selection signal are supplied to the memory as an address signal, a predetermined calculation result is output from the memory.
If the calculation result includes both the multiplication result and the addition result, both the digital multiplier and the digital adder can be eliminated. Therefore, a compact digital filter with low power consumption can be configured.

[0017]

FIG. 1 shows the configuration of an embodiment of the digital filter of the present invention. This embodiment is an example in which the present invention is applied to an FIR interpolation filter. Similar to the conventional example of FIG. 6,
Four cascaded tap delay lines 1 to 4 are provided. The tap delay line 1 delays the 5-bit input data D0 by one clock, and the tap delay line 2 outputs the tap delay line 1. The data D1 is delayed by one clock, and the tap delay line 3 outputs the data D2 output from the tap delay line 2.
Is delayed by one clock to output data D3.

The 5-bit input data D0 (that is, ta
p0 data), the delayed 5-bit data D1 (that is, tap1 data), and the 5-bit coefficient selection signal S are supplied to the memory 4 as a 15-bit address signal A1. .. The delayed 5-bit data D2 (that is, tap2 data) and D3 (that is, tap3 data), and the 5-bit coefficient selection signal S are combined into a 15-bit address signal A2. It is supplied to the memory 5.

The memory 4 has a first result which is a multiplication result of the input data D0 and the coefficient selected by the coefficient selection signal S.
The second multiplication result (FIG. 6) which is the multiplication result (corresponding to the output of the multiplier 21 in FIG. 6) and the output D1 of the tap delay line 1 and the coefficient selected by the coefficient selection signal S.
(Corresponding to the output of the multiplier 22 of 1) is stored. Then, the memory 4 receives the supplied address signal A1.
The 8-bit intermediate operation result D4 corresponding to

The memory 5 outputs a third multiplication result (corresponding to the output of the multiplier 23 of FIG. 6) which is a multiplication result of the output D2 of the tap delay line 2 and the coefficient selected by the coefficient selection signal S, and the tap delay. The addition result of the fourth multiplication result (corresponding to the output of the multiplier 24 in FIG. 6) which is the multiplication result of the output D3 of the line 3 and the coefficient selected by the coefficient selection signal S is stored. The memory 5 then outputs the 8-bit intermediate operation result D5 according to the supplied address signal A2.
Is output. The final interpolation output can be obtained by adding the output of the memory 4 and the output of the memory 5 by the digital adder 6.

In this embodiment, the memories 4 and 5 have functions corresponding to two multipliers, one adder and two coefficient memories, respectively.

FIG. 2 shows the connection structure of the address and data signal lines of the memory 4. Of the 15 address lines a0 to a14, the data D is assigned to the address lines a0 to a4.
1 (that is, the data of the front (odd-numbered) tap) is supplied, data D0 (that is, the data of the rear (even-numbered) tap) is supplied to the address lines a5 to a9, and the address lines a10 to a14 are supplied. The coefficient selection signal S is supplied. The intermediate calculation result D4 is output from the eight data lines d0 to d7.

In the connection configuration of the address and data signal lines of the memory 5, the data D3 is supplied to the address lines a0 to a4 as the data of the front (odd number) taps, and the address lines a5 to a9 are supplied to the rear (even number). Th) tap data
Except that the data D2 is supplied as a data and the intermediate operation result D5 is output from the eight data lines d0 to d7.
The configuration is the same as that of FIG.

FIG. 3 shows an example of tap coefficient values switched by a 5-bit coefficient selection signal S. This coefficient data should be held in the coefficient memories 12 to 15 in the conventional embodiment shown in FIG. In the embodiment of FIG. 1, tap0
And tap1 are calculated in the memory 4. In this case, the product-sum operation result data to be stored in the memory 4 in advance is shown in FIG.

In the embodiment of FIG. 1 described above, one external adder 6 is used as the arithmetic unit in addition to the two memories 4 and 5, but by using a memory having a sufficiently large capacity, , It is possible to perform all arithmetic operations by one memory.

FIG. 5 shows the configuration of another embodiment of the digital filter of the present invention in which all arithmetic operations can be performed by one memory. In this embodiment, 5-bit input data D0 (that is, tap0 data), delayed 5-bit data D1 (that is, tap1 data), and delayed 5-bit data D2 (that is, ta).
p2 data), the delayed 5-bit data D3 (that is, tap3 data), and the 5-bit coefficient selection signal S are supplied to the memory 10 as a 25-bit address signal. The memory 5 includes the coefficient memories 12, 13, 14, and 15, the multipliers 21, 22, 23 and 24, and the adder 3 shown in FIG.
Performs 1, 32 and 33 functions. Therefore, since the digital multiplier and the adder are not necessary at all, the digital filter can be made very small and the power consumption can be greatly saved.

In the above embodiment, three delay lines are provided, but the present invention is not limited to this, and a required number of delay elements can be provided.

[0028]

According to the digital filter of the first aspect, since the memory for storing the calculation result for the input data is provided, if the calculation result is the multiplication result, the digital multiplier is used. If the calculation result is the addition result, For example, if the calculation result includes both the multiplication result and the addition result, the digital adder and the digital adder can be omitted. Therefore, a compact digital filter with low power consumption can be configured.

According to the digital filter of claim 2,
Since the memory for storing the addition result of the first and second multiplication results is provided, two digital multipliers and one digital adder can be eliminated. Therefore, a compact digital filter with low power consumption can be configured.

According to the digital filter of claim 3,
Since the memory for storing the addition result of the third and fourth multiplication results is provided, both two digital multipliers and one digital adder can be eliminated. Therefore, a compact digital filter with low power consumption can be configured.

According to the digital filter of claim 4,
Since the memory for storing the predetermined calculation result for the input data, each output of the plurality of delay elements and the coefficient selection signal is provided, if the calculation result includes both the multiplication result and the addition result, the digital multiplier and the digital multiplier are used. Both of the adders can be dispensed with. Therefore, a compact digital filter with low power consumption can be configured.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a digital filter of the present invention.

FIG. 2 is a block diagram showing details of address lines and data output lines of a memory 4 of FIG.

FIG. 3 is a table showing an example of tap coefficient values switched by a coefficient selection signal.

FIG. 4 is a memory map diagram showing product-sum operation result data to be stored in the memory 4 of FIG.

FIG. 5 is a block diagram showing the configuration of another embodiment of the digital filter of the present invention.

FIG. 6 is a block diagram showing a configuration example of a conventional digital filter.

[Explanation of Codes] 1, 2, 3 Tap Delay Lines 4, 5, 10 Memory

Claims (4)

[Claims] 1. A digital filter comprising a memory for storing a calculation result of input data, and supplying the input data as an address of the memory. 2. A first multiplication result, which is a multiplication result of the input data and a coefficient selected by a coefficient selection signal, having a predetermined number of delay elements connected in cascade to delay the input data by a predetermined time. A digital filter having a function of adding an output of a predetermined delay element of the predetermined number of delay elements and a second multiplication result which is a multiplication result of the coefficient selected by the coefficient selection signal. A memory for storing an addition result of the first multiplication result and the second multiplication result, and supplying the input data, the output of the predetermined delay element and the coefficient selection signal as an address signal to the memory. A digital filter characterized by. 3. A plurality of delay elements connected in cascade for delaying input data by a predetermined time, respectively, and an output of a first delay element of the plurality of delay elements and a coefficient selected by a coefficient selection signal. And a fourth multiplication result which is a multiplication result of the output of the second delay element of the plurality of delay elements and the coefficient selected by the coefficient selection signal. A digital filter having: a memory for storing an addition result of the third multiplication result and the fourth multiplication result, wherein the outputs of the first and second delay elements and the coefficient selection signal are sent to the memory as an address signal. A digital filter characterized by being supplied. 4. A plurality of delay elements connected in cascade, each delaying input data by a predetermined time, and outputs of each of the input data and the plurality of delay elements and a coefficient selected by a coefficient selection signal. A digital filter having a function of performing a predetermined operation on a multiplication result, comprising a memory for storing a result of the predetermined operation, the input data, outputs of the plurality of delay elements, and the coefficient selection signal. Is supplied as an address signal to the memory.