JPH05129606A - Manufacture of semiconductor element - Google Patents

Abstract

PURPOSE:To restrain deterioration of gate breakdown strength without thinning a film thickness of polysilicon of a gate electrode part by forming a gate electrode by laminating silicon-rich high-melting-point metal silicide on an upper layer of the polysilicon. CONSTITUTION:A gate oxide film 2 is formed on a silicon substrate 1 by thermal oxidation and a polysilicon film 3 which is doped with impurities and a silicon-rich high-melting-point metal silicide film 4 are deposited one by one. Thereafter, the high melting point metal silicide film 4 and the polysilicon film 3 are patterned one by one by photolithography and etching to form a gate electrode. In the process, the metal silicide film 4 is formed to a composition of 2.3 to 2.8. Thereby, it is possible to supply silicon which is necessary to cause silicide reaction selfmatchingly not from polysilicon of the gate electrode but from metal silicide of an upper layer thereof by laminating high melting point metal on the upper layer and by carrying out heat treatment.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a MOS field effect transistor.

[0002]

2. Description of the Related Art FIGS. 2A to 2C are sectional views showing steps in a conventional method of manufacturing a MOS field effect transistor.
This method is intended to reduce the resistance of the wiring by siliciding the gate electrode of the MOS transistor and the source / drain regions in a self-aligned manner, and is generally called the salicide process. The outline of the process will be described below with reference to FIG.

First, the gate oxide film 1 is formed on the silicon substrate 99.
00 by thermal oxidation and then a polysilicon film 15
After forming about 00 to 3000 Å, the polysilicon film is patterned to form the gate electrode 200. (Fig. 2-
a) Next, low concentration source / drain regions are formed by ion implantation. (FIG. 2-b) Next, an oxide film 400 is formed by a CVD method or the like (FIG. 2-c), and the oxide film 400 is etched by anisotropic dry etching to form a sidewall 500 on the side wall of the gate electrode. .. (Fig.2-d)
Next, the exposed Si surface is thermally oxidized at a temperature of 800 to 1000 ° C. to form an oxide film 600 of about 300 to 500 Å. Then, a high concentration source / drain region 700 is formed by ion implantation. (Fig.2-e) Next 800 ~
Heat treatment is performed at 1000 ° C. to activate the implanted impurities. (FIG. 2F) After that, the thermal oxide film 600 is removed by etching using a hydrofluoric acid solution to deposit a refractory metal film 800. (FIG. 2-g) Then, by performing heat treatment at 600 to 1000 ° C., a silicidation reaction occurs and the refractory metal silicide 900 is formed on the gate electrode and the source / drain regions in a self-aligned manner. (FIG. 2-h) The salicide process is then completed by etching away the unreacted refractory metal 1000. (Fig. 2
-I)

[0004]

However, in the manufacturing method described above, the silicon required in the silicidation reaction between the refractory metal and the polysilicon is supplied from the polysilicon in the gate electrode portion. Will be done. As a result, there has been a problem that the film thickness of the polysilicon in the gate electrode portion becomes thin after the silicidation reaction and the gate breakdown voltage deteriorates. The present invention provides a manufacturing method which solves the problem that the conventional technique has, that is, the film thickness of the polysilicon in the gate electrode portion becomes thin and the gate breakdown voltage deteriorates due to the silicidation reaction. ..

[0005]

In order to solve the above-mentioned problems, the present invention sequentially forms polysilicon and silicon-rich refractory metal silicide on a silicon substrate through an insulating film and then patterns the desired polysilicon. The gate electrode is left at the position, then the insulating film is selectively left on the side wall of the gate electrode, the refractory metal film is formed on the gate electrode, and then the refractory metal film is heated to a high temperature. By changing to the melting point metal silicide, the silicon required for the silicidation reaction is supplied from the silicon-rich high melting point metal silicide instead of polysilicon, and the thickness of the polysilicon becomes thin and the gate breakdown voltage deteriorates. This is to prevent this.

[0006]

According to the present invention, since the manufacturing method as described above is introduced, it is possible to prevent the polysilicon film of the gate electrode from being thinned, and therefore the above problems can be eliminated.

[0007]

FIG. 1 is a process sectional view showing an embodiment of the present invention. The outline of the process will be described below with reference to FIG.

First, a gate oxide film 2 is formed on a silicon substrate 1.
Is formed by thermal oxidation, and then an impurity-doped polysilicon film 3 and a silicon-rich refractory metal silicide film 4 are sequentially deposited, and then the refractory metal silicide film 4 and the polysilicon film 3 are formed by photolithography and etching. The gate electrode is formed by sequentially patterning. (Fig. 1-
a) At this time, the silicon-rich refractory metal silicide film 4
Has a composition such that silicon is 2.3 to 2.8 with respect to the refractory metal 1 such as W, Mo or Ta. If the amount of silicon is about 3 or more, the problem of film peeling occurs.

Next, an impurity 5 for forming low-concentration source / drain regions is implanted into the substrate by ion implantation.
(FIG. 1-b) Next, a non-doped silicon oxide film 6 or a silicon oxide film 6 containing impurities such as B and P is formed by a CVD method or the like.
Accumulate about 000 to 4000Å. (FIG. 1-c) Next, the non-doped silicon oxide film or the silicon oxide film 6 containing impurities is anisotropically etched, for example, by reactive ion etching (RIE), The side wall 7 is selectively left on the side wall of the gate electrode. (FIG. 1-d) Next, an oxide film 8 for preventing channeling is formed in a thickness of 800-100.
It is formed by thermal oxidation at 0 ° C. Then, an impurity 9 for forming high-concentration source / drain regions is implanted into the substrate by ion implantation. (FIG. 1-e) Next, heat treatment at 800 to 1000 ° C. is performed to activate the ion-implanted impurities, and the low-concentration diffusion layer 1 is activated.
0 and the high concentration diffusion layer 11 are formed. (FIG. 1-f) Next, after removing the thermal oxide film 8 with a hydrofluoric acid solution or the like, the refractory metal 12 is deposited to about 100 to 500 Å. (Fig. 1
-G) Then, by performing heat treatment at 600 to 1000 ° C., a silicidation reaction occurs between the refractory metal and the silicon-rich refractory metal silicide, and between the refractory metal and the silicon substrate. Source·
Refractory metal silicide 13 is formed on the drain. (FIG. 1-h) Then, the unreacted refractory metal 14 is removed to complete the self-aligned silicide structure. As is clear from the figure (Fig. 1-i), the gate electrode is 3
It has a layered structure.

[0010]

As described above, according to the present invention, the gate electrode is formed not by the conventional polysilicon single layer but by laminating the silicon rich refractory metal silicide on the polysilicon upper layer. Silicon required for stacking a refractory metal in the upper layer and causing a silicidation reaction by heat treatment is supplied not from the polysilicon of the gate electrode but from the silicon-rich refractory metal silicide of the upper layer. It becomes possible. As a result, the film thickness of the polysilicon of the gate electrode portion is not reduced, and the deterioration of the gate breakdown voltage can be suppressed, so that a transistor with higher performance can be formed.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process according to the present invention.

FIG. 2 is a sectional view of a conventional manufacturing process.

[Explanation of symbols]

 1 semiconductor substrate 2 gate oxide film 3 polysilicon 4 silicon rich refractory metal silicide 5 low concentration impurity 6 oxide film 7 sidewall 8 thermal oxide film 9 high concentration impurity 10 low concentration diffusion layer 11 high concentration diffusion layer 12 high melting point metal 13 refractory metal silicide 14 unreacted refractory metal 99 semiconductor substrate 100 gate oxide film 200 polysilicon 300 low concentration impurity 400 oxide film 500 sidewall 600 thermal oxide film 700 high concentration impurity 800 refractory metal 900 refractory metal silicide 1000 not Reaction refractory metal

Claims (2)

[Claims] 1. A step of sequentially forming polysilicon containing impurities and a silicon-rich refractory metal silicide on an Si substrate through an insulating film, and then patterning the gate electrode to leave the gate electrode at a desired position, A step of selectively leaving an insulating film on the side wall of the gate electrode; a step of forming a refractory metal film on the gate electrode; and a step of heat treatment to contact the refractory metal film with the silicon-rich refractory metal silicide. A method of manufacturing a semiconductor device, which comprises sequentially performing a step of changing to a refractory metal silicide in a region. 2. The composition of the silicon-rich refractory metal silicide is such that silicon is 2.3 with respect to refractory metal 1.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device has a thickness of 1 to 2.8.